xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/cxd2099.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * cxd2099.c: Driver for the Sony CXD2099AR Common Interface Controller
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2010-2013 Digital Devices GmbH
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
8*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License
9*4882a593Smuzhiyun  * version 2 only, as published by the Free Software Foundation.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful,
12*4882a593Smuzhiyun  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14*4882a593Smuzhiyun  * GNU General Public License for more details.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/i2c.h>
21*4882a593Smuzhiyun #include <linux/regmap.h>
22*4882a593Smuzhiyun #include <linux/wait.h>
23*4882a593Smuzhiyun #include <linux/delay.h>
24*4882a593Smuzhiyun #include <linux/mutex.h>
25*4882a593Smuzhiyun #include <linux/io.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "cxd2099.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static int buffermode;
30*4882a593Smuzhiyun module_param(buffermode, int, 0444);
31*4882a593Smuzhiyun MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)");
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun struct cxd {
36*4882a593Smuzhiyun 	struct dvb_ca_en50221 en;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	struct cxd2099_cfg cfg;
39*4882a593Smuzhiyun 	struct i2c_client *client;
40*4882a593Smuzhiyun 	struct regmap *regmap;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	u8     regs[0x23];
43*4882a593Smuzhiyun 	u8     lastaddress;
44*4882a593Smuzhiyun 	u8     clk_reg_f;
45*4882a593Smuzhiyun 	u8     clk_reg_b;
46*4882a593Smuzhiyun 	int    mode;
47*4882a593Smuzhiyun 	int    ready;
48*4882a593Smuzhiyun 	int    dr;
49*4882a593Smuzhiyun 	int    write_busy;
50*4882a593Smuzhiyun 	int    slot_stat;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	u8     amem[1024];
53*4882a593Smuzhiyun 	int    amem_read;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	int    cammode;
56*4882a593Smuzhiyun 	struct mutex lock; /* device access lock */
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	u8     rbuf[1028];
59*4882a593Smuzhiyun 	u8     wbuf[1028];
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
read_block(struct cxd * ci,u8 adr,u8 * data,u16 n)62*4882a593Smuzhiyun static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	int status = 0;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	if (ci->lastaddress != adr)
67*4882a593Smuzhiyun 		status = regmap_write(ci->regmap, 0, adr);
68*4882a593Smuzhiyun 	if (!status) {
69*4882a593Smuzhiyun 		ci->lastaddress = adr;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 		while (n) {
72*4882a593Smuzhiyun 			int len = n;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 			if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
75*4882a593Smuzhiyun 				len = ci->cfg.max_i2c;
76*4882a593Smuzhiyun 			status = regmap_raw_read(ci->regmap, 1, data, len);
77*4882a593Smuzhiyun 			if (status)
78*4882a593Smuzhiyun 				return status;
79*4882a593Smuzhiyun 			data += len;
80*4882a593Smuzhiyun 			n -= len;
81*4882a593Smuzhiyun 		}
82*4882a593Smuzhiyun 	}
83*4882a593Smuzhiyun 	return status;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
read_reg(struct cxd * ci,u8 reg,u8 * val)86*4882a593Smuzhiyun static int read_reg(struct cxd *ci, u8 reg, u8 *val)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	return read_block(ci, reg, val, 1);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
read_pccard(struct cxd * ci,u16 address,u8 * data,u8 n)91*4882a593Smuzhiyun static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	int status;
94*4882a593Smuzhiyun 	u8 addr[2] = {address & 0xff, address >> 8};
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	status = regmap_raw_write(ci->regmap, 2, addr, 2);
97*4882a593Smuzhiyun 	if (!status)
98*4882a593Smuzhiyun 		status = regmap_raw_read(ci->regmap, 3, data, n);
99*4882a593Smuzhiyun 	return status;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
write_pccard(struct cxd * ci,u16 address,u8 * data,u8 n)102*4882a593Smuzhiyun static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	int status;
105*4882a593Smuzhiyun 	u8 addr[2] = {address & 0xff, address >> 8};
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	status = regmap_raw_write(ci->regmap, 2, addr, 2);
108*4882a593Smuzhiyun 	if (!status) {
109*4882a593Smuzhiyun 		u8 buf[256];
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 		memcpy(buf, data, n);
112*4882a593Smuzhiyun 		status = regmap_raw_write(ci->regmap, 3, buf, n);
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 	return status;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
read_io(struct cxd * ci,u16 address,unsigned int * val)117*4882a593Smuzhiyun static int read_io(struct cxd *ci, u16 address, unsigned int *val)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	int status;
120*4882a593Smuzhiyun 	u8 addr[2] = {address & 0xff, address >> 8};
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	status = regmap_raw_write(ci->regmap, 2, addr, 2);
123*4882a593Smuzhiyun 	if (!status)
124*4882a593Smuzhiyun 		status = regmap_read(ci->regmap, 3, val);
125*4882a593Smuzhiyun 	return status;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun 
write_io(struct cxd * ci,u16 address,u8 val)128*4882a593Smuzhiyun static int write_io(struct cxd *ci, u16 address, u8 val)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	int status;
131*4882a593Smuzhiyun 	u8 addr[2] = {address & 0xff, address >> 8};
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	status = regmap_raw_write(ci->regmap, 2, addr, 2);
134*4882a593Smuzhiyun 	if (!status)
135*4882a593Smuzhiyun 		status = regmap_write(ci->regmap, 3, val);
136*4882a593Smuzhiyun 	return status;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
write_regm(struct cxd * ci,u8 reg,u8 val,u8 mask)139*4882a593Smuzhiyun static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	int status = 0;
142*4882a593Smuzhiyun 	unsigned int regval;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	if (ci->lastaddress != reg)
145*4882a593Smuzhiyun 		status = regmap_write(ci->regmap, 0, reg);
146*4882a593Smuzhiyun 	if (!status && reg >= 6 && reg <= 8 && mask != 0xff) {
147*4882a593Smuzhiyun 		status = regmap_read(ci->regmap, 1, &regval);
148*4882a593Smuzhiyun 		ci->regs[reg] = regval;
149*4882a593Smuzhiyun 	}
150*4882a593Smuzhiyun 	ci->lastaddress = reg;
151*4882a593Smuzhiyun 	ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
152*4882a593Smuzhiyun 	if (!status)
153*4882a593Smuzhiyun 		status = regmap_write(ci->regmap, 1, ci->regs[reg]);
154*4882a593Smuzhiyun 	if (reg == 0x20)
155*4882a593Smuzhiyun 		ci->regs[reg] &= 0x7f;
156*4882a593Smuzhiyun 	return status;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
write_reg(struct cxd * ci,u8 reg,u8 val)159*4882a593Smuzhiyun static int write_reg(struct cxd *ci, u8 reg, u8 val)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	return write_regm(ci, reg, val, 0xff);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
write_block(struct cxd * ci,u8 adr,u8 * data,u16 n)164*4882a593Smuzhiyun static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	int status = 0;
167*4882a593Smuzhiyun 	u8 *buf = ci->wbuf;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	if (ci->lastaddress != adr)
170*4882a593Smuzhiyun 		status = regmap_write(ci->regmap, 0, adr);
171*4882a593Smuzhiyun 	if (status)
172*4882a593Smuzhiyun 		return status;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	ci->lastaddress = adr;
175*4882a593Smuzhiyun 	while (n) {
176*4882a593Smuzhiyun 		int len = n;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 		if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
179*4882a593Smuzhiyun 			len = ci->cfg.max_i2c - 1;
180*4882a593Smuzhiyun 		memcpy(buf, data, len);
181*4882a593Smuzhiyun 		status = regmap_raw_write(ci->regmap, 1, buf, len);
182*4882a593Smuzhiyun 		if (status)
183*4882a593Smuzhiyun 			return status;
184*4882a593Smuzhiyun 		n -= len;
185*4882a593Smuzhiyun 		data += len;
186*4882a593Smuzhiyun 	}
187*4882a593Smuzhiyun 	return status;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
set_mode(struct cxd * ci,int mode)190*4882a593Smuzhiyun static void set_mode(struct cxd *ci, int mode)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun 	if (mode == ci->mode)
193*4882a593Smuzhiyun 		return;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	switch (mode) {
196*4882a593Smuzhiyun 	case 0x00: /* IO mem */
197*4882a593Smuzhiyun 		write_regm(ci, 0x06, 0x00, 0x07);
198*4882a593Smuzhiyun 		break;
199*4882a593Smuzhiyun 	case 0x01: /* ATT mem */
200*4882a593Smuzhiyun 		write_regm(ci, 0x06, 0x02, 0x07);
201*4882a593Smuzhiyun 		break;
202*4882a593Smuzhiyun 	default:
203*4882a593Smuzhiyun 		break;
204*4882a593Smuzhiyun 	}
205*4882a593Smuzhiyun 	ci->mode = mode;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
cam_mode(struct cxd * ci,int mode)208*4882a593Smuzhiyun static void cam_mode(struct cxd *ci, int mode)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	u8 dummy;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	if (mode == ci->cammode)
213*4882a593Smuzhiyun 		return;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	switch (mode) {
216*4882a593Smuzhiyun 	case 0x00:
217*4882a593Smuzhiyun 		write_regm(ci, 0x20, 0x80, 0x80);
218*4882a593Smuzhiyun 		break;
219*4882a593Smuzhiyun 	case 0x01:
220*4882a593Smuzhiyun 		if (!ci->en.read_data)
221*4882a593Smuzhiyun 			return;
222*4882a593Smuzhiyun 		ci->write_busy = 0;
223*4882a593Smuzhiyun 		dev_info(&ci->client->dev, "enable cam buffer mode\n");
224*4882a593Smuzhiyun 		write_reg(ci, 0x0d, 0x00);
225*4882a593Smuzhiyun 		write_reg(ci, 0x0e, 0x01);
226*4882a593Smuzhiyun 		write_regm(ci, 0x08, 0x40, 0x40);
227*4882a593Smuzhiyun 		read_reg(ci, 0x12, &dummy);
228*4882a593Smuzhiyun 		write_regm(ci, 0x08, 0x80, 0x80);
229*4882a593Smuzhiyun 		break;
230*4882a593Smuzhiyun 	default:
231*4882a593Smuzhiyun 		break;
232*4882a593Smuzhiyun 	}
233*4882a593Smuzhiyun 	ci->cammode = mode;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
init(struct cxd * ci)236*4882a593Smuzhiyun static int init(struct cxd *ci)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	int status;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
241*4882a593Smuzhiyun 	ci->mode = -1;
242*4882a593Smuzhiyun 	do {
243*4882a593Smuzhiyun 		status = write_reg(ci, 0x00, 0x00);
244*4882a593Smuzhiyun 		if (status < 0)
245*4882a593Smuzhiyun 			break;
246*4882a593Smuzhiyun 		status = write_reg(ci, 0x01, 0x00);
247*4882a593Smuzhiyun 		if (status < 0)
248*4882a593Smuzhiyun 			break;
249*4882a593Smuzhiyun 		status = write_reg(ci, 0x02, 0x10);
250*4882a593Smuzhiyun 		if (status < 0)
251*4882a593Smuzhiyun 			break;
252*4882a593Smuzhiyun 		status = write_reg(ci, 0x03, 0x00);
253*4882a593Smuzhiyun 		if (status < 0)
254*4882a593Smuzhiyun 			break;
255*4882a593Smuzhiyun 		status = write_reg(ci, 0x05, 0xFF);
256*4882a593Smuzhiyun 		if (status < 0)
257*4882a593Smuzhiyun 			break;
258*4882a593Smuzhiyun 		status = write_reg(ci, 0x06, 0x1F);
259*4882a593Smuzhiyun 		if (status < 0)
260*4882a593Smuzhiyun 			break;
261*4882a593Smuzhiyun 		status = write_reg(ci, 0x07, 0x1F);
262*4882a593Smuzhiyun 		if (status < 0)
263*4882a593Smuzhiyun 			break;
264*4882a593Smuzhiyun 		status = write_reg(ci, 0x08, 0x28);
265*4882a593Smuzhiyun 		if (status < 0)
266*4882a593Smuzhiyun 			break;
267*4882a593Smuzhiyun 		status = write_reg(ci, 0x14, 0x20);
268*4882a593Smuzhiyun 		if (status < 0)
269*4882a593Smuzhiyun 			break;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 		/* TOSTRT = 8, Mode B (gated clock), falling Edge,
272*4882a593Smuzhiyun 		 * Serial, POL=HIGH, MSB
273*4882a593Smuzhiyun 		 */
274*4882a593Smuzhiyun 		status = write_reg(ci, 0x0A, 0xA7);
275*4882a593Smuzhiyun 		if (status < 0)
276*4882a593Smuzhiyun 			break;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 		status = write_reg(ci, 0x0B, 0x33);
279*4882a593Smuzhiyun 		if (status < 0)
280*4882a593Smuzhiyun 			break;
281*4882a593Smuzhiyun 		status = write_reg(ci, 0x0C, 0x33);
282*4882a593Smuzhiyun 		if (status < 0)
283*4882a593Smuzhiyun 			break;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 		status = write_regm(ci, 0x14, 0x00, 0x0F);
286*4882a593Smuzhiyun 		if (status < 0)
287*4882a593Smuzhiyun 			break;
288*4882a593Smuzhiyun 		status = write_reg(ci, 0x15, ci->clk_reg_b);
289*4882a593Smuzhiyun 		if (status < 0)
290*4882a593Smuzhiyun 			break;
291*4882a593Smuzhiyun 		status = write_regm(ci, 0x16, 0x00, 0x0F);
292*4882a593Smuzhiyun 		if (status < 0)
293*4882a593Smuzhiyun 			break;
294*4882a593Smuzhiyun 		status = write_reg(ci, 0x17, ci->clk_reg_f);
295*4882a593Smuzhiyun 		if (status < 0)
296*4882a593Smuzhiyun 			break;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 		if (ci->cfg.clock_mode == 2) {
299*4882a593Smuzhiyun 			/* bitrate*2^13/ 72000 */
300*4882a593Smuzhiyun 			u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 			if (ci->cfg.polarity) {
303*4882a593Smuzhiyun 				status = write_reg(ci, 0x09, 0x6f);
304*4882a593Smuzhiyun 				if (status < 0)
305*4882a593Smuzhiyun 					break;
306*4882a593Smuzhiyun 			} else {
307*4882a593Smuzhiyun 				status = write_reg(ci, 0x09, 0x6d);
308*4882a593Smuzhiyun 				if (status < 0)
309*4882a593Smuzhiyun 					break;
310*4882a593Smuzhiyun 			}
311*4882a593Smuzhiyun 			status = write_reg(ci, 0x20, 0x08);
312*4882a593Smuzhiyun 			if (status < 0)
313*4882a593Smuzhiyun 				break;
314*4882a593Smuzhiyun 			status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
315*4882a593Smuzhiyun 			if (status < 0)
316*4882a593Smuzhiyun 				break;
317*4882a593Smuzhiyun 			status = write_reg(ci, 0x22, reg & 0xff);
318*4882a593Smuzhiyun 			if (status < 0)
319*4882a593Smuzhiyun 				break;
320*4882a593Smuzhiyun 		} else if (ci->cfg.clock_mode == 1) {
321*4882a593Smuzhiyun 			if (ci->cfg.polarity) {
322*4882a593Smuzhiyun 				status = write_reg(ci, 0x09, 0x6f); /* D */
323*4882a593Smuzhiyun 				if (status < 0)
324*4882a593Smuzhiyun 					break;
325*4882a593Smuzhiyun 			} else {
326*4882a593Smuzhiyun 				status = write_reg(ci, 0x09, 0x6d);
327*4882a593Smuzhiyun 				if (status < 0)
328*4882a593Smuzhiyun 					break;
329*4882a593Smuzhiyun 			}
330*4882a593Smuzhiyun 			status = write_reg(ci, 0x20, 0x68);
331*4882a593Smuzhiyun 			if (status < 0)
332*4882a593Smuzhiyun 				break;
333*4882a593Smuzhiyun 			status = write_reg(ci, 0x21, 0x00);
334*4882a593Smuzhiyun 			if (status < 0)
335*4882a593Smuzhiyun 				break;
336*4882a593Smuzhiyun 			status = write_reg(ci, 0x22, 0x02);
337*4882a593Smuzhiyun 			if (status < 0)
338*4882a593Smuzhiyun 				break;
339*4882a593Smuzhiyun 		} else {
340*4882a593Smuzhiyun 			if (ci->cfg.polarity) {
341*4882a593Smuzhiyun 				status = write_reg(ci, 0x09, 0x4f); /* C */
342*4882a593Smuzhiyun 				if (status < 0)
343*4882a593Smuzhiyun 					break;
344*4882a593Smuzhiyun 			} else {
345*4882a593Smuzhiyun 				status = write_reg(ci, 0x09, 0x4d);
346*4882a593Smuzhiyun 				if (status < 0)
347*4882a593Smuzhiyun 					break;
348*4882a593Smuzhiyun 			}
349*4882a593Smuzhiyun 			status = write_reg(ci, 0x20, 0x28);
350*4882a593Smuzhiyun 			if (status < 0)
351*4882a593Smuzhiyun 				break;
352*4882a593Smuzhiyun 			status = write_reg(ci, 0x21, 0x00);
353*4882a593Smuzhiyun 			if (status < 0)
354*4882a593Smuzhiyun 				break;
355*4882a593Smuzhiyun 			status = write_reg(ci, 0x22, 0x07);
356*4882a593Smuzhiyun 			if (status < 0)
357*4882a593Smuzhiyun 				break;
358*4882a593Smuzhiyun 		}
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 		status = write_regm(ci, 0x20, 0x80, 0x80);
361*4882a593Smuzhiyun 		if (status < 0)
362*4882a593Smuzhiyun 			break;
363*4882a593Smuzhiyun 		status = write_regm(ci, 0x03, 0x02, 0x02);
364*4882a593Smuzhiyun 		if (status < 0)
365*4882a593Smuzhiyun 			break;
366*4882a593Smuzhiyun 		status = write_reg(ci, 0x01, 0x04);
367*4882a593Smuzhiyun 		if (status < 0)
368*4882a593Smuzhiyun 			break;
369*4882a593Smuzhiyun 		status = write_reg(ci, 0x00, 0x31);
370*4882a593Smuzhiyun 		if (status < 0)
371*4882a593Smuzhiyun 			break;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 		/* Put TS in bypass */
374*4882a593Smuzhiyun 		status = write_regm(ci, 0x09, 0x08, 0x08);
375*4882a593Smuzhiyun 		if (status < 0)
376*4882a593Smuzhiyun 			break;
377*4882a593Smuzhiyun 		ci->cammode = -1;
378*4882a593Smuzhiyun 		cam_mode(ci, 0);
379*4882a593Smuzhiyun 	} while (0);
380*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	return 0;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun 
read_attribute_mem(struct dvb_ca_en50221 * ca,int slot,int address)385*4882a593Smuzhiyun static int read_attribute_mem(struct dvb_ca_en50221 *ca,
386*4882a593Smuzhiyun 			      int slot, int address)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
389*4882a593Smuzhiyun 	u8 val;
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
392*4882a593Smuzhiyun 	set_mode(ci, 1);
393*4882a593Smuzhiyun 	read_pccard(ci, address, &val, 1);
394*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
395*4882a593Smuzhiyun 	return val;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun 
write_attribute_mem(struct dvb_ca_en50221 * ca,int slot,int address,u8 value)398*4882a593Smuzhiyun static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
399*4882a593Smuzhiyun 			       int address, u8 value)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
404*4882a593Smuzhiyun 	set_mode(ci, 1);
405*4882a593Smuzhiyun 	write_pccard(ci, address, &value, 1);
406*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
407*4882a593Smuzhiyun 	return 0;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun 
read_cam_control(struct dvb_ca_en50221 * ca,int slot,u8 address)410*4882a593Smuzhiyun static int read_cam_control(struct dvb_ca_en50221 *ca,
411*4882a593Smuzhiyun 			    int slot, u8 address)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
414*4882a593Smuzhiyun 	unsigned int val;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
417*4882a593Smuzhiyun 	set_mode(ci, 0);
418*4882a593Smuzhiyun 	read_io(ci, address, &val);
419*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
420*4882a593Smuzhiyun 	return val;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun 
write_cam_control(struct dvb_ca_en50221 * ca,int slot,u8 address,u8 value)423*4882a593Smuzhiyun static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
424*4882a593Smuzhiyun 			     u8 address, u8 value)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
429*4882a593Smuzhiyun 	set_mode(ci, 0);
430*4882a593Smuzhiyun 	write_io(ci, address, value);
431*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
432*4882a593Smuzhiyun 	return 0;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun 
slot_reset(struct dvb_ca_en50221 * ca,int slot)435*4882a593Smuzhiyun static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	if (ci->cammode)
440*4882a593Smuzhiyun 		read_data(ca, slot, ci->rbuf, 0);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
443*4882a593Smuzhiyun 	cam_mode(ci, 0);
444*4882a593Smuzhiyun 	write_reg(ci, 0x00, 0x21);
445*4882a593Smuzhiyun 	write_reg(ci, 0x06, 0x1F);
446*4882a593Smuzhiyun 	write_reg(ci, 0x00, 0x31);
447*4882a593Smuzhiyun 	write_regm(ci, 0x20, 0x80, 0x80);
448*4882a593Smuzhiyun 	write_reg(ci, 0x03, 0x02);
449*4882a593Smuzhiyun 	ci->ready = 0;
450*4882a593Smuzhiyun 	ci->mode = -1;
451*4882a593Smuzhiyun 	{
452*4882a593Smuzhiyun 		int i;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 		for (i = 0; i < 100; i++) {
455*4882a593Smuzhiyun 			usleep_range(10000, 11000);
456*4882a593Smuzhiyun 			if (ci->ready)
457*4882a593Smuzhiyun 				break;
458*4882a593Smuzhiyun 		}
459*4882a593Smuzhiyun 	}
460*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
461*4882a593Smuzhiyun 	return 0;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun 
slot_shutdown(struct dvb_ca_en50221 * ca,int slot)464*4882a593Smuzhiyun static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	dev_dbg(&ci->client->dev, "%s\n", __func__);
469*4882a593Smuzhiyun 	if (ci->cammode)
470*4882a593Smuzhiyun 		read_data(ca, slot, ci->rbuf, 0);
471*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
472*4882a593Smuzhiyun 	write_reg(ci, 0x00, 0x21);
473*4882a593Smuzhiyun 	write_reg(ci, 0x06, 0x1F);
474*4882a593Smuzhiyun 	msleep(300);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	write_regm(ci, 0x09, 0x08, 0x08);
477*4882a593Smuzhiyun 	write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
478*4882a593Smuzhiyun 	write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	ci->mode = -1;
481*4882a593Smuzhiyun 	ci->write_busy = 0;
482*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
483*4882a593Smuzhiyun 	return 0;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun 
slot_ts_enable(struct dvb_ca_en50221 * ca,int slot)486*4882a593Smuzhiyun static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
487*4882a593Smuzhiyun {
488*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
491*4882a593Smuzhiyun 	write_regm(ci, 0x09, 0x00, 0x08);
492*4882a593Smuzhiyun 	set_mode(ci, 0);
493*4882a593Smuzhiyun 	cam_mode(ci, 1);
494*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
495*4882a593Smuzhiyun 	return 0;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun 
campoll(struct cxd * ci)498*4882a593Smuzhiyun static int campoll(struct cxd *ci)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun 	u8 istat;
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	read_reg(ci, 0x04, &istat);
503*4882a593Smuzhiyun 	if (!istat)
504*4882a593Smuzhiyun 		return 0;
505*4882a593Smuzhiyun 	write_reg(ci, 0x05, istat);
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	if (istat & 0x40)
508*4882a593Smuzhiyun 		ci->dr = 1;
509*4882a593Smuzhiyun 	if (istat & 0x20)
510*4882a593Smuzhiyun 		ci->write_busy = 0;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	if (istat & 2) {
513*4882a593Smuzhiyun 		u8 slotstat;
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 		read_reg(ci, 0x01, &slotstat);
516*4882a593Smuzhiyun 		if (!(2 & slotstat)) {
517*4882a593Smuzhiyun 			if (!ci->slot_stat) {
518*4882a593Smuzhiyun 				ci->slot_stat |=
519*4882a593Smuzhiyun 					      DVB_CA_EN50221_POLL_CAM_PRESENT;
520*4882a593Smuzhiyun 				write_regm(ci, 0x03, 0x08, 0x08);
521*4882a593Smuzhiyun 			}
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 		} else {
524*4882a593Smuzhiyun 			if (ci->slot_stat) {
525*4882a593Smuzhiyun 				ci->slot_stat = 0;
526*4882a593Smuzhiyun 				write_regm(ci, 0x03, 0x00, 0x08);
527*4882a593Smuzhiyun 				dev_info(&ci->client->dev, "NO CAM\n");
528*4882a593Smuzhiyun 				ci->ready = 0;
529*4882a593Smuzhiyun 			}
530*4882a593Smuzhiyun 		}
531*4882a593Smuzhiyun 		if ((istat & 8) &&
532*4882a593Smuzhiyun 		    ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
533*4882a593Smuzhiyun 			ci->ready = 1;
534*4882a593Smuzhiyun 			ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
535*4882a593Smuzhiyun 		}
536*4882a593Smuzhiyun 	}
537*4882a593Smuzhiyun 	return 0;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun 
poll_slot_status(struct dvb_ca_en50221 * ca,int slot,int open)540*4882a593Smuzhiyun static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
543*4882a593Smuzhiyun 	u8 slotstat;
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
546*4882a593Smuzhiyun 	campoll(ci);
547*4882a593Smuzhiyun 	read_reg(ci, 0x01, &slotstat);
548*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	return ci->slot_stat;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
read_data(struct dvb_ca_en50221 * ca,int slot,u8 * ebuf,int ecount)553*4882a593Smuzhiyun static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
556*4882a593Smuzhiyun 	u8 msb, lsb;
557*4882a593Smuzhiyun 	u16 len;
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
560*4882a593Smuzhiyun 	campoll(ci);
561*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	if (!ci->dr)
564*4882a593Smuzhiyun 		return 0;
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
567*4882a593Smuzhiyun 	read_reg(ci, 0x0f, &msb);
568*4882a593Smuzhiyun 	read_reg(ci, 0x10, &lsb);
569*4882a593Smuzhiyun 	len = ((u16)msb << 8) | lsb;
570*4882a593Smuzhiyun 	if (len > ecount || len < 2) {
571*4882a593Smuzhiyun 		/* read it anyway or cxd may hang */
572*4882a593Smuzhiyun 		read_block(ci, 0x12, ci->rbuf, len);
573*4882a593Smuzhiyun 		mutex_unlock(&ci->lock);
574*4882a593Smuzhiyun 		return -EIO;
575*4882a593Smuzhiyun 	}
576*4882a593Smuzhiyun 	read_block(ci, 0x12, ebuf, len);
577*4882a593Smuzhiyun 	ci->dr = 0;
578*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
579*4882a593Smuzhiyun 	return len;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun 
write_data(struct dvb_ca_en50221 * ca,int slot,u8 * ebuf,int ecount)582*4882a593Smuzhiyun static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun 	struct cxd *ci = ca->data;
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	if (ci->write_busy)
587*4882a593Smuzhiyun 		return -EAGAIN;
588*4882a593Smuzhiyun 	mutex_lock(&ci->lock);
589*4882a593Smuzhiyun 	write_reg(ci, 0x0d, ecount >> 8);
590*4882a593Smuzhiyun 	write_reg(ci, 0x0e, ecount & 0xff);
591*4882a593Smuzhiyun 	write_block(ci, 0x11, ebuf, ecount);
592*4882a593Smuzhiyun 	ci->write_busy = 1;
593*4882a593Smuzhiyun 	mutex_unlock(&ci->lock);
594*4882a593Smuzhiyun 	return ecount;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun static const struct dvb_ca_en50221 en_templ = {
598*4882a593Smuzhiyun 	.read_attribute_mem  = read_attribute_mem,
599*4882a593Smuzhiyun 	.write_attribute_mem = write_attribute_mem,
600*4882a593Smuzhiyun 	.read_cam_control    = read_cam_control,
601*4882a593Smuzhiyun 	.write_cam_control   = write_cam_control,
602*4882a593Smuzhiyun 	.slot_reset          = slot_reset,
603*4882a593Smuzhiyun 	.slot_shutdown       = slot_shutdown,
604*4882a593Smuzhiyun 	.slot_ts_enable      = slot_ts_enable,
605*4882a593Smuzhiyun 	.poll_slot_status    = poll_slot_status,
606*4882a593Smuzhiyun 	.read_data           = read_data,
607*4882a593Smuzhiyun 	.write_data          = write_data,
608*4882a593Smuzhiyun };
609*4882a593Smuzhiyun 
cxd2099_probe(struct i2c_client * client,const struct i2c_device_id * id)610*4882a593Smuzhiyun static int cxd2099_probe(struct i2c_client *client,
611*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun 	struct cxd *ci;
614*4882a593Smuzhiyun 	struct cxd2099_cfg *cfg = client->dev.platform_data;
615*4882a593Smuzhiyun 	static const struct regmap_config rm_cfg = {
616*4882a593Smuzhiyun 		.reg_bits = 8,
617*4882a593Smuzhiyun 		.val_bits = 8,
618*4882a593Smuzhiyun 	};
619*4882a593Smuzhiyun 	unsigned int val;
620*4882a593Smuzhiyun 	int ret;
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun 	ci = kzalloc(sizeof(*ci), GFP_KERNEL);
623*4882a593Smuzhiyun 	if (!ci) {
624*4882a593Smuzhiyun 		ret = -ENOMEM;
625*4882a593Smuzhiyun 		goto err;
626*4882a593Smuzhiyun 	}
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	ci->client = client;
629*4882a593Smuzhiyun 	memcpy(&ci->cfg, cfg, sizeof(ci->cfg));
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	ci->regmap = regmap_init_i2c(client, &rm_cfg);
632*4882a593Smuzhiyun 	if (IS_ERR(ci->regmap)) {
633*4882a593Smuzhiyun 		ret = PTR_ERR(ci->regmap);
634*4882a593Smuzhiyun 		goto err_kfree;
635*4882a593Smuzhiyun 	}
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	ret = regmap_read(ci->regmap, 0x00, &val);
638*4882a593Smuzhiyun 	if (ret < 0) {
639*4882a593Smuzhiyun 		dev_info(&client->dev, "No CXD2099AR detected at 0x%02x\n",
640*4882a593Smuzhiyun 			 client->addr);
641*4882a593Smuzhiyun 		goto err_rmexit;
642*4882a593Smuzhiyun 	}
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	mutex_init(&ci->lock);
645*4882a593Smuzhiyun 	ci->lastaddress = 0xff;
646*4882a593Smuzhiyun 	ci->clk_reg_b = 0x4a;
647*4882a593Smuzhiyun 	ci->clk_reg_f = 0x1b;
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	ci->en = en_templ;
650*4882a593Smuzhiyun 	ci->en.data = ci;
651*4882a593Smuzhiyun 	init(ci);
652*4882a593Smuzhiyun 	dev_info(&client->dev, "Attached CXD2099AR at 0x%02x\n", client->addr);
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	*cfg->en = &ci->en;
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	if (!buffermode) {
657*4882a593Smuzhiyun 		ci->en.read_data = NULL;
658*4882a593Smuzhiyun 		ci->en.write_data = NULL;
659*4882a593Smuzhiyun 	} else {
660*4882a593Smuzhiyun 		dev_info(&client->dev, "Using CXD2099AR buffer mode");
661*4882a593Smuzhiyun 	}
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	i2c_set_clientdata(client, ci);
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	return 0;
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun err_rmexit:
668*4882a593Smuzhiyun 	regmap_exit(ci->regmap);
669*4882a593Smuzhiyun err_kfree:
670*4882a593Smuzhiyun 	kfree(ci);
671*4882a593Smuzhiyun err:
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 	return ret;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun 
cxd2099_remove(struct i2c_client * client)676*4882a593Smuzhiyun static int cxd2099_remove(struct i2c_client *client)
677*4882a593Smuzhiyun {
678*4882a593Smuzhiyun 	struct cxd *ci = i2c_get_clientdata(client);
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	regmap_exit(ci->regmap);
681*4882a593Smuzhiyun 	kfree(ci);
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	return 0;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun static const struct i2c_device_id cxd2099_id[] = {
687*4882a593Smuzhiyun 	{"cxd2099", 0},
688*4882a593Smuzhiyun 	{}
689*4882a593Smuzhiyun };
690*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, cxd2099_id);
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun static struct i2c_driver cxd2099_driver = {
693*4882a593Smuzhiyun 	.driver = {
694*4882a593Smuzhiyun 		.name	= "cxd2099",
695*4882a593Smuzhiyun 	},
696*4882a593Smuzhiyun 	.probe		= cxd2099_probe,
697*4882a593Smuzhiyun 	.remove		= cxd2099_remove,
698*4882a593Smuzhiyun 	.id_table	= cxd2099_id,
699*4882a593Smuzhiyun };
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun module_i2c_driver(cxd2099_driver);
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun MODULE_DESCRIPTION("Sony CXD2099AR Common Interface controller driver");
704*4882a593Smuzhiyun MODULE_AUTHOR("Ralph Metzler");
705*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
706