xref: /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/cx22702.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun     Conexant 22702 DVB OFDM demodulator driver
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun     based on:
6*4882a593Smuzhiyun 	Alps TDMB7 DVB OFDM demodulator driver
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun     Copyright (C) 2001-2002 Convergence Integrated Media GmbH
9*4882a593Smuzhiyun 	  Holger Waechtler <holger@convergence.de>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun     Copyright (C) 2004 Steven Toth <stoth@linuxtv.org>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/string.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <media/dvb_frontend.h>
23*4882a593Smuzhiyun #include "cx22702.h"
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun struct cx22702_state {
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	struct i2c_adapter *i2c;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	/* configuration settings */
30*4882a593Smuzhiyun 	const struct cx22702_config *config;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	struct dvb_frontend frontend;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	/* previous uncorrected block counter */
35*4882a593Smuzhiyun 	u8 prevUCBlocks;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun static int debug;
39*4882a593Smuzhiyun module_param(debug, int, 0644);
40*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Enable verbose debug messages");
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define dprintk	if (debug) printk
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* Register values to initialise the demod */
45*4882a593Smuzhiyun static const u8 init_tab[] = {
46*4882a593Smuzhiyun 	0x00, 0x00, /* Stop acquisition */
47*4882a593Smuzhiyun 	0x0B, 0x06,
48*4882a593Smuzhiyun 	0x09, 0x01,
49*4882a593Smuzhiyun 	0x0D, 0x41,
50*4882a593Smuzhiyun 	0x16, 0x32,
51*4882a593Smuzhiyun 	0x20, 0x0A,
52*4882a593Smuzhiyun 	0x21, 0x17,
53*4882a593Smuzhiyun 	0x24, 0x3e,
54*4882a593Smuzhiyun 	0x26, 0xff,
55*4882a593Smuzhiyun 	0x27, 0x10,
56*4882a593Smuzhiyun 	0x28, 0x00,
57*4882a593Smuzhiyun 	0x29, 0x00,
58*4882a593Smuzhiyun 	0x2a, 0x10,
59*4882a593Smuzhiyun 	0x2b, 0x00,
60*4882a593Smuzhiyun 	0x2c, 0x10,
61*4882a593Smuzhiyun 	0x2d, 0x00,
62*4882a593Smuzhiyun 	0x48, 0xd4,
63*4882a593Smuzhiyun 	0x49, 0x56,
64*4882a593Smuzhiyun 	0x6b, 0x1e,
65*4882a593Smuzhiyun 	0xc8, 0x02,
66*4882a593Smuzhiyun 	0xf9, 0x00,
67*4882a593Smuzhiyun 	0xfa, 0x00,
68*4882a593Smuzhiyun 	0xfb, 0x00,
69*4882a593Smuzhiyun 	0xfc, 0x00,
70*4882a593Smuzhiyun 	0xfd, 0x00,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
cx22702_writereg(struct cx22702_state * state,u8 reg,u8 data)73*4882a593Smuzhiyun static int cx22702_writereg(struct cx22702_state *state, u8 reg, u8 data)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	int ret;
76*4882a593Smuzhiyun 	u8 buf[] = { reg, data };
77*4882a593Smuzhiyun 	struct i2c_msg msg = {
78*4882a593Smuzhiyun 		.addr = state->config->demod_address, .flags = 0,
79*4882a593Smuzhiyun 			.buf = buf, .len = 2 };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	ret = i2c_transfer(state->i2c, &msg, 1);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	if (unlikely(ret != 1)) {
84*4882a593Smuzhiyun 		printk(KERN_ERR
85*4882a593Smuzhiyun 			"%s: error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
86*4882a593Smuzhiyun 			__func__, reg, data, ret);
87*4882a593Smuzhiyun 		return -1;
88*4882a593Smuzhiyun 	}
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
cx22702_readreg(struct cx22702_state * state,u8 reg)93*4882a593Smuzhiyun static u8 cx22702_readreg(struct cx22702_state *state, u8 reg)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	int ret;
96*4882a593Smuzhiyun 	u8 data;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	struct i2c_msg msg[] = {
99*4882a593Smuzhiyun 		{ .addr = state->config->demod_address, .flags = 0,
100*4882a593Smuzhiyun 			.buf = &reg, .len = 1 },
101*4882a593Smuzhiyun 		{ .addr = state->config->demod_address, .flags = I2C_M_RD,
102*4882a593Smuzhiyun 			.buf = &data, .len = 1 } };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ret = i2c_transfer(state->i2c, msg, 2);
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	if (unlikely(ret != 2)) {
107*4882a593Smuzhiyun 		printk(KERN_ERR "%s: error (reg == 0x%02x, ret == %i)\n",
108*4882a593Smuzhiyun 			__func__, reg, ret);
109*4882a593Smuzhiyun 		return 0;
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return data;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
cx22702_set_inversion(struct cx22702_state * state,int inversion)115*4882a593Smuzhiyun static int cx22702_set_inversion(struct cx22702_state *state, int inversion)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	u8 val;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	val = cx22702_readreg(state, 0x0C);
120*4882a593Smuzhiyun 	switch (inversion) {
121*4882a593Smuzhiyun 	case INVERSION_AUTO:
122*4882a593Smuzhiyun 		return -EOPNOTSUPP;
123*4882a593Smuzhiyun 	case INVERSION_ON:
124*4882a593Smuzhiyun 		val |= 0x01;
125*4882a593Smuzhiyun 		break;
126*4882a593Smuzhiyun 	case INVERSION_OFF:
127*4882a593Smuzhiyun 		val &= 0xfe;
128*4882a593Smuzhiyun 		break;
129*4882a593Smuzhiyun 	default:
130*4882a593Smuzhiyun 		return -EINVAL;
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 	return cx22702_writereg(state, 0x0C, val);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /* Retrieve the demod settings */
cx22702_get_tps(struct cx22702_state * state,struct dtv_frontend_properties * p)136*4882a593Smuzhiyun static int cx22702_get_tps(struct cx22702_state *state,
137*4882a593Smuzhiyun 			   struct dtv_frontend_properties *p)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	u8 val;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* Make sure the TPS regs are valid */
142*4882a593Smuzhiyun 	if (!(cx22702_readreg(state, 0x0A) & 0x20))
143*4882a593Smuzhiyun 		return -EAGAIN;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	val = cx22702_readreg(state, 0x01);
146*4882a593Smuzhiyun 	switch ((val & 0x18) >> 3) {
147*4882a593Smuzhiyun 	case 0:
148*4882a593Smuzhiyun 		p->modulation = QPSK;
149*4882a593Smuzhiyun 		break;
150*4882a593Smuzhiyun 	case 1:
151*4882a593Smuzhiyun 		p->modulation = QAM_16;
152*4882a593Smuzhiyun 		break;
153*4882a593Smuzhiyun 	case 2:
154*4882a593Smuzhiyun 		p->modulation = QAM_64;
155*4882a593Smuzhiyun 		break;
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun 	switch (val & 0x07) {
158*4882a593Smuzhiyun 	case 0:
159*4882a593Smuzhiyun 		p->hierarchy = HIERARCHY_NONE;
160*4882a593Smuzhiyun 		break;
161*4882a593Smuzhiyun 	case 1:
162*4882a593Smuzhiyun 		p->hierarchy = HIERARCHY_1;
163*4882a593Smuzhiyun 		break;
164*4882a593Smuzhiyun 	case 2:
165*4882a593Smuzhiyun 		p->hierarchy = HIERARCHY_2;
166*4882a593Smuzhiyun 		break;
167*4882a593Smuzhiyun 	case 3:
168*4882a593Smuzhiyun 		p->hierarchy = HIERARCHY_4;
169*4882a593Smuzhiyun 		break;
170*4882a593Smuzhiyun 	}
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	val = cx22702_readreg(state, 0x02);
174*4882a593Smuzhiyun 	switch ((val & 0x38) >> 3) {
175*4882a593Smuzhiyun 	case 0:
176*4882a593Smuzhiyun 		p->code_rate_HP = FEC_1_2;
177*4882a593Smuzhiyun 		break;
178*4882a593Smuzhiyun 	case 1:
179*4882a593Smuzhiyun 		p->code_rate_HP = FEC_2_3;
180*4882a593Smuzhiyun 		break;
181*4882a593Smuzhiyun 	case 2:
182*4882a593Smuzhiyun 		p->code_rate_HP = FEC_3_4;
183*4882a593Smuzhiyun 		break;
184*4882a593Smuzhiyun 	case 3:
185*4882a593Smuzhiyun 		p->code_rate_HP = FEC_5_6;
186*4882a593Smuzhiyun 		break;
187*4882a593Smuzhiyun 	case 4:
188*4882a593Smuzhiyun 		p->code_rate_HP = FEC_7_8;
189*4882a593Smuzhiyun 		break;
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 	switch (val & 0x07) {
192*4882a593Smuzhiyun 	case 0:
193*4882a593Smuzhiyun 		p->code_rate_LP = FEC_1_2;
194*4882a593Smuzhiyun 		break;
195*4882a593Smuzhiyun 	case 1:
196*4882a593Smuzhiyun 		p->code_rate_LP = FEC_2_3;
197*4882a593Smuzhiyun 		break;
198*4882a593Smuzhiyun 	case 2:
199*4882a593Smuzhiyun 		p->code_rate_LP = FEC_3_4;
200*4882a593Smuzhiyun 		break;
201*4882a593Smuzhiyun 	case 3:
202*4882a593Smuzhiyun 		p->code_rate_LP = FEC_5_6;
203*4882a593Smuzhiyun 		break;
204*4882a593Smuzhiyun 	case 4:
205*4882a593Smuzhiyun 		p->code_rate_LP = FEC_7_8;
206*4882a593Smuzhiyun 		break;
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	val = cx22702_readreg(state, 0x03);
210*4882a593Smuzhiyun 	switch ((val & 0x0c) >> 2) {
211*4882a593Smuzhiyun 	case 0:
212*4882a593Smuzhiyun 		p->guard_interval = GUARD_INTERVAL_1_32;
213*4882a593Smuzhiyun 		break;
214*4882a593Smuzhiyun 	case 1:
215*4882a593Smuzhiyun 		p->guard_interval = GUARD_INTERVAL_1_16;
216*4882a593Smuzhiyun 		break;
217*4882a593Smuzhiyun 	case 2:
218*4882a593Smuzhiyun 		p->guard_interval = GUARD_INTERVAL_1_8;
219*4882a593Smuzhiyun 		break;
220*4882a593Smuzhiyun 	case 3:
221*4882a593Smuzhiyun 		p->guard_interval = GUARD_INTERVAL_1_4;
222*4882a593Smuzhiyun 		break;
223*4882a593Smuzhiyun 	}
224*4882a593Smuzhiyun 	switch (val & 0x03) {
225*4882a593Smuzhiyun 	case 0:
226*4882a593Smuzhiyun 		p->transmission_mode = TRANSMISSION_MODE_2K;
227*4882a593Smuzhiyun 		break;
228*4882a593Smuzhiyun 	case 1:
229*4882a593Smuzhiyun 		p->transmission_mode = TRANSMISSION_MODE_8K;
230*4882a593Smuzhiyun 		break;
231*4882a593Smuzhiyun 	}
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	return 0;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
cx22702_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)236*4882a593Smuzhiyun static int cx22702_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
239*4882a593Smuzhiyun 	u8 val;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	dprintk("%s(%d)\n", __func__, enable);
242*4882a593Smuzhiyun 	val = cx22702_readreg(state, 0x0D);
243*4882a593Smuzhiyun 	if (enable)
244*4882a593Smuzhiyun 		val &= 0xfe;
245*4882a593Smuzhiyun 	else
246*4882a593Smuzhiyun 		val |= 0x01;
247*4882a593Smuzhiyun 	return cx22702_writereg(state, 0x0D, val);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
cx22702_set_tps(struct dvb_frontend * fe)251*4882a593Smuzhiyun static int cx22702_set_tps(struct dvb_frontend *fe)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
254*4882a593Smuzhiyun 	u8 val;
255*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	if (fe->ops.tuner_ops.set_params) {
258*4882a593Smuzhiyun 		fe->ops.tuner_ops.set_params(fe);
259*4882a593Smuzhiyun 		if (fe->ops.i2c_gate_ctrl)
260*4882a593Smuzhiyun 			fe->ops.i2c_gate_ctrl(fe, 0);
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	/* set inversion */
264*4882a593Smuzhiyun 	cx22702_set_inversion(state, p->inversion);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	/* set bandwidth */
267*4882a593Smuzhiyun 	val = cx22702_readreg(state, 0x0C) & 0xcf;
268*4882a593Smuzhiyun 	switch (p->bandwidth_hz) {
269*4882a593Smuzhiyun 	case 6000000:
270*4882a593Smuzhiyun 		val |= 0x20;
271*4882a593Smuzhiyun 		break;
272*4882a593Smuzhiyun 	case 7000000:
273*4882a593Smuzhiyun 		val |= 0x10;
274*4882a593Smuzhiyun 		break;
275*4882a593Smuzhiyun 	case 8000000:
276*4882a593Smuzhiyun 		break;
277*4882a593Smuzhiyun 	default:
278*4882a593Smuzhiyun 		dprintk("%s: invalid bandwidth\n", __func__);
279*4882a593Smuzhiyun 		return -EINVAL;
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 	cx22702_writereg(state, 0x0C, val);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	p->code_rate_LP = FEC_AUTO; /* temp hack as manual not working */
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	/* use auto configuration? */
286*4882a593Smuzhiyun 	if ((p->hierarchy == HIERARCHY_AUTO) ||
287*4882a593Smuzhiyun 	   (p->modulation == QAM_AUTO) ||
288*4882a593Smuzhiyun 	   (p->code_rate_HP == FEC_AUTO) ||
289*4882a593Smuzhiyun 	   (p->code_rate_LP == FEC_AUTO) ||
290*4882a593Smuzhiyun 	   (p->guard_interval == GUARD_INTERVAL_AUTO) ||
291*4882a593Smuzhiyun 	   (p->transmission_mode == TRANSMISSION_MODE_AUTO)) {
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 		/* TPS Source - use hardware driven values */
294*4882a593Smuzhiyun 		cx22702_writereg(state, 0x06, 0x10);
295*4882a593Smuzhiyun 		cx22702_writereg(state, 0x07, 0x9);
296*4882a593Smuzhiyun 		cx22702_writereg(state, 0x08, 0xC1);
297*4882a593Smuzhiyun 		cx22702_writereg(state, 0x0B, cx22702_readreg(state, 0x0B)
298*4882a593Smuzhiyun 			& 0xfc);
299*4882a593Smuzhiyun 		cx22702_writereg(state, 0x0C,
300*4882a593Smuzhiyun 			(cx22702_readreg(state, 0x0C) & 0xBF) | 0x40);
301*4882a593Smuzhiyun 		cx22702_writereg(state, 0x00, 0x01); /* Begin acquisition */
302*4882a593Smuzhiyun 		dprintk("%s: Autodetecting\n", __func__);
303*4882a593Smuzhiyun 		return 0;
304*4882a593Smuzhiyun 	}
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	/* manually programmed values */
307*4882a593Smuzhiyun 	switch (p->modulation) {		/* mask 0x18 */
308*4882a593Smuzhiyun 	case QPSK:
309*4882a593Smuzhiyun 		val = 0x00;
310*4882a593Smuzhiyun 		break;
311*4882a593Smuzhiyun 	case QAM_16:
312*4882a593Smuzhiyun 		val = 0x08;
313*4882a593Smuzhiyun 		break;
314*4882a593Smuzhiyun 	case QAM_64:
315*4882a593Smuzhiyun 		val = 0x10;
316*4882a593Smuzhiyun 		break;
317*4882a593Smuzhiyun 	default:
318*4882a593Smuzhiyun 		dprintk("%s: invalid modulation\n", __func__);
319*4882a593Smuzhiyun 		return -EINVAL;
320*4882a593Smuzhiyun 	}
321*4882a593Smuzhiyun 	switch (p->hierarchy) {	/* mask 0x07 */
322*4882a593Smuzhiyun 	case HIERARCHY_NONE:
323*4882a593Smuzhiyun 		break;
324*4882a593Smuzhiyun 	case HIERARCHY_1:
325*4882a593Smuzhiyun 		val |= 0x01;
326*4882a593Smuzhiyun 		break;
327*4882a593Smuzhiyun 	case HIERARCHY_2:
328*4882a593Smuzhiyun 		val |= 0x02;
329*4882a593Smuzhiyun 		break;
330*4882a593Smuzhiyun 	case HIERARCHY_4:
331*4882a593Smuzhiyun 		val |= 0x03;
332*4882a593Smuzhiyun 		break;
333*4882a593Smuzhiyun 	default:
334*4882a593Smuzhiyun 		dprintk("%s: invalid hierarchy\n", __func__);
335*4882a593Smuzhiyun 		return -EINVAL;
336*4882a593Smuzhiyun 	}
337*4882a593Smuzhiyun 	cx22702_writereg(state, 0x06, val);
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	switch (p->code_rate_HP) {		/* mask 0x38 */
340*4882a593Smuzhiyun 	case FEC_NONE:
341*4882a593Smuzhiyun 	case FEC_1_2:
342*4882a593Smuzhiyun 		val = 0x00;
343*4882a593Smuzhiyun 		break;
344*4882a593Smuzhiyun 	case FEC_2_3:
345*4882a593Smuzhiyun 		val = 0x08;
346*4882a593Smuzhiyun 		break;
347*4882a593Smuzhiyun 	case FEC_3_4:
348*4882a593Smuzhiyun 		val = 0x10;
349*4882a593Smuzhiyun 		break;
350*4882a593Smuzhiyun 	case FEC_5_6:
351*4882a593Smuzhiyun 		val = 0x18;
352*4882a593Smuzhiyun 		break;
353*4882a593Smuzhiyun 	case FEC_7_8:
354*4882a593Smuzhiyun 		val = 0x20;
355*4882a593Smuzhiyun 		break;
356*4882a593Smuzhiyun 	default:
357*4882a593Smuzhiyun 		dprintk("%s: invalid code_rate_HP\n", __func__);
358*4882a593Smuzhiyun 		return -EINVAL;
359*4882a593Smuzhiyun 	}
360*4882a593Smuzhiyun 	switch (p->code_rate_LP) {		/* mask 0x07 */
361*4882a593Smuzhiyun 	case FEC_NONE:
362*4882a593Smuzhiyun 	case FEC_1_2:
363*4882a593Smuzhiyun 		break;
364*4882a593Smuzhiyun 	case FEC_2_3:
365*4882a593Smuzhiyun 		val |= 0x01;
366*4882a593Smuzhiyun 		break;
367*4882a593Smuzhiyun 	case FEC_3_4:
368*4882a593Smuzhiyun 		val |= 0x02;
369*4882a593Smuzhiyun 		break;
370*4882a593Smuzhiyun 	case FEC_5_6:
371*4882a593Smuzhiyun 		val |= 0x03;
372*4882a593Smuzhiyun 		break;
373*4882a593Smuzhiyun 	case FEC_7_8:
374*4882a593Smuzhiyun 		val |= 0x04;
375*4882a593Smuzhiyun 		break;
376*4882a593Smuzhiyun 	default:
377*4882a593Smuzhiyun 		dprintk("%s: invalid code_rate_LP\n", __func__);
378*4882a593Smuzhiyun 		return -EINVAL;
379*4882a593Smuzhiyun 	}
380*4882a593Smuzhiyun 	cx22702_writereg(state, 0x07, val);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	switch (p->guard_interval) {		/* mask 0x0c */
383*4882a593Smuzhiyun 	case GUARD_INTERVAL_1_32:
384*4882a593Smuzhiyun 		val = 0x00;
385*4882a593Smuzhiyun 		break;
386*4882a593Smuzhiyun 	case GUARD_INTERVAL_1_16:
387*4882a593Smuzhiyun 		val = 0x04;
388*4882a593Smuzhiyun 		break;
389*4882a593Smuzhiyun 	case GUARD_INTERVAL_1_8:
390*4882a593Smuzhiyun 		val = 0x08;
391*4882a593Smuzhiyun 		break;
392*4882a593Smuzhiyun 	case GUARD_INTERVAL_1_4:
393*4882a593Smuzhiyun 		val = 0x0c;
394*4882a593Smuzhiyun 		break;
395*4882a593Smuzhiyun 	default:
396*4882a593Smuzhiyun 		dprintk("%s: invalid guard_interval\n", __func__);
397*4882a593Smuzhiyun 		return -EINVAL;
398*4882a593Smuzhiyun 	}
399*4882a593Smuzhiyun 	switch (p->transmission_mode) {		/* mask 0x03 */
400*4882a593Smuzhiyun 	case TRANSMISSION_MODE_2K:
401*4882a593Smuzhiyun 		break;
402*4882a593Smuzhiyun 	case TRANSMISSION_MODE_8K:
403*4882a593Smuzhiyun 		val |= 0x1;
404*4882a593Smuzhiyun 		break;
405*4882a593Smuzhiyun 	default:
406*4882a593Smuzhiyun 		dprintk("%s: invalid transmission_mode\n", __func__);
407*4882a593Smuzhiyun 		return -EINVAL;
408*4882a593Smuzhiyun 	}
409*4882a593Smuzhiyun 	cx22702_writereg(state, 0x08, val);
410*4882a593Smuzhiyun 	cx22702_writereg(state, 0x0B,
411*4882a593Smuzhiyun 		(cx22702_readreg(state, 0x0B) & 0xfc) | 0x02);
412*4882a593Smuzhiyun 	cx22702_writereg(state, 0x0C,
413*4882a593Smuzhiyun 		(cx22702_readreg(state, 0x0C) & 0xBF) | 0x40);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	/* Begin channel acquisition */
416*4882a593Smuzhiyun 	cx22702_writereg(state, 0x00, 0x01);
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	return 0;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun /* Reset the demod hardware and reset all of the configuration registers
422*4882a593Smuzhiyun    to a default state. */
cx22702_init(struct dvb_frontend * fe)423*4882a593Smuzhiyun static int cx22702_init(struct dvb_frontend *fe)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun 	int i;
426*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	cx22702_writereg(state, 0x00, 0x02);
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	msleep(10);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(init_tab); i += 2)
433*4882a593Smuzhiyun 		cx22702_writereg(state, init_tab[i], init_tab[i + 1]);
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	cx22702_writereg(state, 0xf8, (state->config->output_mode << 1)
436*4882a593Smuzhiyun 		& 0x02);
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	cx22702_i2c_gate_ctrl(fe, 0);
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	return 0;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun 
cx22702_read_status(struct dvb_frontend * fe,enum fe_status * status)443*4882a593Smuzhiyun static int cx22702_read_status(struct dvb_frontend *fe, enum fe_status *status)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
446*4882a593Smuzhiyun 	u8 reg0A;
447*4882a593Smuzhiyun 	u8 reg23;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	*status = 0;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	reg0A = cx22702_readreg(state, 0x0A);
452*4882a593Smuzhiyun 	reg23 = cx22702_readreg(state, 0x23);
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	dprintk("%s: status demod=0x%02x agc=0x%02x\n"
455*4882a593Smuzhiyun 		, __func__, reg0A, reg23);
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	if (reg0A & 0x10) {
458*4882a593Smuzhiyun 		*status |= FE_HAS_LOCK;
459*4882a593Smuzhiyun 		*status |= FE_HAS_VITERBI;
460*4882a593Smuzhiyun 		*status |= FE_HAS_SYNC;
461*4882a593Smuzhiyun 	}
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	if (reg0A & 0x20)
464*4882a593Smuzhiyun 		*status |= FE_HAS_CARRIER;
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	if (reg23 < 0xf0)
467*4882a593Smuzhiyun 		*status |= FE_HAS_SIGNAL;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	return 0;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun 
cx22702_read_ber(struct dvb_frontend * fe,u32 * ber)472*4882a593Smuzhiyun static int cx22702_read_ber(struct dvb_frontend *fe, u32 *ber)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	if (cx22702_readreg(state, 0xE4) & 0x02) {
477*4882a593Smuzhiyun 		/* Realtime statistics */
478*4882a593Smuzhiyun 		*ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
479*4882a593Smuzhiyun 			| (cx22702_readreg(state, 0xDF) & 0x7F);
480*4882a593Smuzhiyun 	} else {
481*4882a593Smuzhiyun 		/* Averagtine statistics */
482*4882a593Smuzhiyun 		*ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
483*4882a593Smuzhiyun 			| cx22702_readreg(state, 0xDF);
484*4882a593Smuzhiyun 	}
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	return 0;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun 
cx22702_read_signal_strength(struct dvb_frontend * fe,u16 * signal_strength)489*4882a593Smuzhiyun static int cx22702_read_signal_strength(struct dvb_frontend *fe,
490*4882a593Smuzhiyun 	u16 *signal_strength)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
493*4882a593Smuzhiyun 	u8 reg23;
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	/*
496*4882a593Smuzhiyun 	 * Experience suggests that the strength signal register works as
497*4882a593Smuzhiyun 	 * follows:
498*4882a593Smuzhiyun 	 * - In the absence of signal, value is 0xff.
499*4882a593Smuzhiyun 	 * - In the presence of a weak signal, bit 7 is set, not sure what
500*4882a593Smuzhiyun 	 *   the lower 7 bits mean.
501*4882a593Smuzhiyun 	 * - In the presence of a strong signal, the register holds a 7-bit
502*4882a593Smuzhiyun 	 *   value (bit 7 is cleared), with greater values standing for
503*4882a593Smuzhiyun 	 *   weaker signals.
504*4882a593Smuzhiyun 	 */
505*4882a593Smuzhiyun 	reg23 = cx22702_readreg(state, 0x23);
506*4882a593Smuzhiyun 	if (reg23 & 0x80) {
507*4882a593Smuzhiyun 		*signal_strength = 0;
508*4882a593Smuzhiyun 	} else {
509*4882a593Smuzhiyun 		reg23 = ~reg23 & 0x7f;
510*4882a593Smuzhiyun 		/* Scale to 16 bit */
511*4882a593Smuzhiyun 		*signal_strength = (reg23 << 9) | (reg23 << 2) | (reg23 >> 5);
512*4882a593Smuzhiyun 	}
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	return 0;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun 
cx22702_read_snr(struct dvb_frontend * fe,u16 * snr)517*4882a593Smuzhiyun static int cx22702_read_snr(struct dvb_frontend *fe, u16 *snr)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	u16 rs_ber;
522*4882a593Smuzhiyun 	if (cx22702_readreg(state, 0xE4) & 0x02) {
523*4882a593Smuzhiyun 		/* Realtime statistics */
524*4882a593Smuzhiyun 		rs_ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 7
525*4882a593Smuzhiyun 			| (cx22702_readreg(state, 0xDF) & 0x7F);
526*4882a593Smuzhiyun 	} else {
527*4882a593Smuzhiyun 		/* Averagine statistics */
528*4882a593Smuzhiyun 		rs_ber = (cx22702_readreg(state, 0xDE) & 0x7F) << 8
529*4882a593Smuzhiyun 			| cx22702_readreg(state, 0xDF);
530*4882a593Smuzhiyun 	}
531*4882a593Smuzhiyun 	*snr = ~rs_ber;
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 	return 0;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun 
cx22702_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)536*4882a593Smuzhiyun static int cx22702_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
537*4882a593Smuzhiyun {
538*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	u8 _ucblocks;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	/* RS Uncorrectable Packet Count then reset */
543*4882a593Smuzhiyun 	_ucblocks = cx22702_readreg(state, 0xE3);
544*4882a593Smuzhiyun 	if (state->prevUCBlocks < _ucblocks)
545*4882a593Smuzhiyun 		*ucblocks = (_ucblocks - state->prevUCBlocks);
546*4882a593Smuzhiyun 	else
547*4882a593Smuzhiyun 		*ucblocks = state->prevUCBlocks - _ucblocks;
548*4882a593Smuzhiyun 	state->prevUCBlocks = _ucblocks;
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	return 0;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
cx22702_get_frontend(struct dvb_frontend * fe,struct dtv_frontend_properties * c)553*4882a593Smuzhiyun static int cx22702_get_frontend(struct dvb_frontend *fe,
554*4882a593Smuzhiyun 				struct dtv_frontend_properties *c)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	u8 reg0C = cx22702_readreg(state, 0x0C);
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	c->inversion = reg0C & 0x1 ? INVERSION_ON : INVERSION_OFF;
561*4882a593Smuzhiyun 	return cx22702_get_tps(state, c);
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun 
cx22702_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * tune)564*4882a593Smuzhiyun static int cx22702_get_tune_settings(struct dvb_frontend *fe,
565*4882a593Smuzhiyun 	struct dvb_frontend_tune_settings *tune)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun 	tune->min_delay_ms = 1000;
568*4882a593Smuzhiyun 	return 0;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun 
cx22702_release(struct dvb_frontend * fe)571*4882a593Smuzhiyun static void cx22702_release(struct dvb_frontend *fe)
572*4882a593Smuzhiyun {
573*4882a593Smuzhiyun 	struct cx22702_state *state = fe->demodulator_priv;
574*4882a593Smuzhiyun 	kfree(state);
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun static const struct dvb_frontend_ops cx22702_ops;
578*4882a593Smuzhiyun 
cx22702_attach(const struct cx22702_config * config,struct i2c_adapter * i2c)579*4882a593Smuzhiyun struct dvb_frontend *cx22702_attach(const struct cx22702_config *config,
580*4882a593Smuzhiyun 	struct i2c_adapter *i2c)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun 	struct cx22702_state *state = NULL;
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	/* allocate memory for the internal state */
585*4882a593Smuzhiyun 	state = kzalloc(sizeof(struct cx22702_state), GFP_KERNEL);
586*4882a593Smuzhiyun 	if (state == NULL)
587*4882a593Smuzhiyun 		goto error;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	/* setup the state */
590*4882a593Smuzhiyun 	state->config = config;
591*4882a593Smuzhiyun 	state->i2c = i2c;
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	/* check if the demod is there */
594*4882a593Smuzhiyun 	if (cx22702_readreg(state, 0x1f) != 0x3)
595*4882a593Smuzhiyun 		goto error;
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	/* create dvb_frontend */
598*4882a593Smuzhiyun 	memcpy(&state->frontend.ops, &cx22702_ops,
599*4882a593Smuzhiyun 		sizeof(struct dvb_frontend_ops));
600*4882a593Smuzhiyun 	state->frontend.demodulator_priv = state;
601*4882a593Smuzhiyun 	return &state->frontend;
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun error:
604*4882a593Smuzhiyun 	kfree(state);
605*4882a593Smuzhiyun 	return NULL;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun EXPORT_SYMBOL(cx22702_attach);
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun static const struct dvb_frontend_ops cx22702_ops = {
610*4882a593Smuzhiyun 	.delsys = { SYS_DVBT },
611*4882a593Smuzhiyun 	.info = {
612*4882a593Smuzhiyun 		.name			= "Conexant CX22702 DVB-T",
613*4882a593Smuzhiyun 		.frequency_min_hz	= 177 * MHz,
614*4882a593Smuzhiyun 		.frequency_max_hz	= 858 * MHz,
615*4882a593Smuzhiyun 		.frequency_stepsize_hz	= 166666,
616*4882a593Smuzhiyun 		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
617*4882a593Smuzhiyun 		FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
618*4882a593Smuzhiyun 		FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
619*4882a593Smuzhiyun 		FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
620*4882a593Smuzhiyun 		FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
621*4882a593Smuzhiyun 	},
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	.release = cx22702_release,
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	.init = cx22702_init,
626*4882a593Smuzhiyun 	.i2c_gate_ctrl = cx22702_i2c_gate_ctrl,
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	.set_frontend = cx22702_set_tps,
629*4882a593Smuzhiyun 	.get_frontend = cx22702_get_frontend,
630*4882a593Smuzhiyun 	.get_tune_settings = cx22702_get_tune_settings,
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	.read_status = cx22702_read_status,
633*4882a593Smuzhiyun 	.read_ber = cx22702_read_ber,
634*4882a593Smuzhiyun 	.read_signal_strength = cx22702_read_signal_strength,
635*4882a593Smuzhiyun 	.read_snr = cx22702_read_snr,
636*4882a593Smuzhiyun 	.read_ucblocks = cx22702_read_ucblocks,
637*4882a593Smuzhiyun };
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun MODULE_DESCRIPTION("Conexant CX22702 DVB-T Demodulator driver");
640*4882a593Smuzhiyun MODULE_AUTHOR("Steven Toth");
641*4882a593Smuzhiyun MODULE_LICENSE("GPL");
642