1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * bsru6.h - ALPS BSRU6 tuner support (moved from budget-ci.c)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * the project's page is at https://linuxtv.org
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef BSRU6_H
9*4882a593Smuzhiyun #define BSRU6_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun static u8 alps_bsru6_inittab[] = {
12*4882a593Smuzhiyun 0x01, 0x15,
13*4882a593Smuzhiyun 0x02, 0x30,
14*4882a593Smuzhiyun 0x03, 0x00,
15*4882a593Smuzhiyun 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
16*4882a593Smuzhiyun 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
17*4882a593Smuzhiyun 0x06, 0x40, /* DAC not used, set to high impendance mode */
18*4882a593Smuzhiyun 0x07, 0x00, /* DAC LSB */
19*4882a593Smuzhiyun 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
20*4882a593Smuzhiyun 0x09, 0x00, /* FIFO */
21*4882a593Smuzhiyun 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
22*4882a593Smuzhiyun 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
23*4882a593Smuzhiyun 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
24*4882a593Smuzhiyun 0x10, 0x3f, // AGC2 0x3d
25*4882a593Smuzhiyun 0x11, 0x84,
26*4882a593Smuzhiyun 0x12, 0xb9,
27*4882a593Smuzhiyun 0x15, 0xc9, // lock detector threshold
28*4882a593Smuzhiyun 0x16, 0x00,
29*4882a593Smuzhiyun 0x17, 0x00,
30*4882a593Smuzhiyun 0x18, 0x00,
31*4882a593Smuzhiyun 0x19, 0x00,
32*4882a593Smuzhiyun 0x1a, 0x00,
33*4882a593Smuzhiyun 0x1f, 0x50,
34*4882a593Smuzhiyun 0x20, 0x00,
35*4882a593Smuzhiyun 0x21, 0x00,
36*4882a593Smuzhiyun 0x22, 0x00,
37*4882a593Smuzhiyun 0x23, 0x00,
38*4882a593Smuzhiyun 0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
39*4882a593Smuzhiyun 0x29, 0x1e, // 1/2 threshold
40*4882a593Smuzhiyun 0x2a, 0x14, // 2/3 threshold
41*4882a593Smuzhiyun 0x2b, 0x0f, // 3/4 threshold
42*4882a593Smuzhiyun 0x2c, 0x09, // 5/6 threshold
43*4882a593Smuzhiyun 0x2d, 0x05, // 7/8 threshold
44*4882a593Smuzhiyun 0x2e, 0x01,
45*4882a593Smuzhiyun 0x31, 0x1f, // test all FECs
46*4882a593Smuzhiyun 0x32, 0x19, // viterbi and synchro search
47*4882a593Smuzhiyun 0x33, 0xfc, // rs control
48*4882a593Smuzhiyun 0x34, 0x93, // error control
49*4882a593Smuzhiyun 0x0f, 0x52,
50*4882a593Smuzhiyun 0xff, 0xff
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
alps_bsru6_set_symbol_rate(struct dvb_frontend * fe,u32 srate,u32 ratio)53*4882a593Smuzhiyun static int alps_bsru6_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun u8 aclk = 0;
56*4882a593Smuzhiyun u8 bclk = 0;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (srate < 1500000) {
59*4882a593Smuzhiyun aclk = 0xb7;
60*4882a593Smuzhiyun bclk = 0x47;
61*4882a593Smuzhiyun } else if (srate < 3000000) {
62*4882a593Smuzhiyun aclk = 0xb7;
63*4882a593Smuzhiyun bclk = 0x4b;
64*4882a593Smuzhiyun } else if (srate < 7000000) {
65*4882a593Smuzhiyun aclk = 0xb7;
66*4882a593Smuzhiyun bclk = 0x4f;
67*4882a593Smuzhiyun } else if (srate < 14000000) {
68*4882a593Smuzhiyun aclk = 0xb7;
69*4882a593Smuzhiyun bclk = 0x53;
70*4882a593Smuzhiyun } else if (srate < 30000000) {
71*4882a593Smuzhiyun aclk = 0xb6;
72*4882a593Smuzhiyun bclk = 0x53;
73*4882a593Smuzhiyun } else if (srate < 45000000) {
74*4882a593Smuzhiyun aclk = 0xb4;
75*4882a593Smuzhiyun bclk = 0x51;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun stv0299_writereg(fe, 0x13, aclk);
79*4882a593Smuzhiyun stv0299_writereg(fe, 0x14, bclk);
80*4882a593Smuzhiyun stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
81*4882a593Smuzhiyun stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
82*4882a593Smuzhiyun stv0299_writereg(fe, 0x21, ratio & 0xf0);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
alps_bsru6_tuner_set_params(struct dvb_frontend * fe)87*4882a593Smuzhiyun static int alps_bsru6_tuner_set_params(struct dvb_frontend *fe)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct dtv_frontend_properties *p = &fe->dtv_property_cache;
90*4882a593Smuzhiyun u8 buf[4];
91*4882a593Smuzhiyun u32 div;
92*4882a593Smuzhiyun struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
93*4882a593Smuzhiyun struct i2c_adapter *i2c = fe->tuner_priv;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun if ((p->frequency < 950000) || (p->frequency > 2150000))
96*4882a593Smuzhiyun return -EINVAL;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun div = (p->frequency + (125 - 1)) / 125; /* round correctly */
99*4882a593Smuzhiyun buf[0] = (div >> 8) & 0x7f;
100*4882a593Smuzhiyun buf[1] = div & 0xff;
101*4882a593Smuzhiyun buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
102*4882a593Smuzhiyun buf[3] = 0xC4;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (p->frequency > 1530000)
105*4882a593Smuzhiyun buf[3] = 0xc0;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
108*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 1);
109*4882a593Smuzhiyun if (i2c_transfer(i2c, &msg, 1) != 1)
110*4882a593Smuzhiyun return -EIO;
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static struct stv0299_config alps_bsru6_config = {
115*4882a593Smuzhiyun .demod_address = 0x68,
116*4882a593Smuzhiyun .inittab = alps_bsru6_inittab,
117*4882a593Smuzhiyun .mclk = 88000000UL,
118*4882a593Smuzhiyun .invert = 1,
119*4882a593Smuzhiyun .skip_reinit = 0,
120*4882a593Smuzhiyun .lock_output = STV0299_LOCKOUTPUT_1,
121*4882a593Smuzhiyun .volt13_op0_op1 = STV0299_VOLT13_OP1,
122*4882a593Smuzhiyun .min_delay_ms = 100,
123*4882a593Smuzhiyun .set_symbol_rate = alps_bsru6_set_symbol_rate,
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #endif
127