1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
4*4882a593Smuzhiyun * ATBM8830, ATBM8831
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <asm/div64.h>
10*4882a593Smuzhiyun #include <media/dvb_frontend.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "atbm8830.h"
13*4882a593Smuzhiyun #include "atbm8830_priv.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define dprintk(args...) \
16*4882a593Smuzhiyun do { \
17*4882a593Smuzhiyun if (debug) \
18*4882a593Smuzhiyun printk(KERN_DEBUG "atbm8830: " args); \
19*4882a593Smuzhiyun } while (0)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static int debug;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun module_param(debug, int, 0644);
24*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
25*4882a593Smuzhiyun
atbm8830_write_reg(struct atbm_state * priv,u16 reg,u8 data)26*4882a593Smuzhiyun static int atbm8830_write_reg(struct atbm_state *priv, u16 reg, u8 data)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun int ret = 0;
29*4882a593Smuzhiyun u8 dev_addr;
30*4882a593Smuzhiyun u8 buf1[] = { reg >> 8, reg & 0xFF };
31*4882a593Smuzhiyun u8 buf2[] = { data };
32*4882a593Smuzhiyun struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
33*4882a593Smuzhiyun struct i2c_msg msg2 = { .flags = 0, .buf = buf2, .len = 1 };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun dev_addr = priv->config->demod_address;
36*4882a593Smuzhiyun msg1.addr = dev_addr;
37*4882a593Smuzhiyun msg2.addr = dev_addr;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (debug >= 2)
40*4882a593Smuzhiyun dprintk("%s: reg=0x%04X, data=0x%02X\n", __func__, reg, data);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun ret = i2c_transfer(priv->i2c, &msg1, 1);
43*4882a593Smuzhiyun if (ret != 1)
44*4882a593Smuzhiyun return -EIO;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun ret = i2c_transfer(priv->i2c, &msg2, 1);
47*4882a593Smuzhiyun return (ret != 1) ? -EIO : 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
atbm8830_read_reg(struct atbm_state * priv,u16 reg,u8 * p_data)50*4882a593Smuzhiyun static int atbm8830_read_reg(struct atbm_state *priv, u16 reg, u8 *p_data)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int ret;
53*4882a593Smuzhiyun u8 dev_addr;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun u8 buf1[] = { reg >> 8, reg & 0xFF };
56*4882a593Smuzhiyun u8 buf2[] = { 0 };
57*4882a593Smuzhiyun struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
58*4882a593Smuzhiyun struct i2c_msg msg2 = { .flags = I2C_M_RD, .buf = buf2, .len = 1 };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun dev_addr = priv->config->demod_address;
61*4882a593Smuzhiyun msg1.addr = dev_addr;
62*4882a593Smuzhiyun msg2.addr = dev_addr;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun ret = i2c_transfer(priv->i2c, &msg1, 1);
65*4882a593Smuzhiyun if (ret != 1) {
66*4882a593Smuzhiyun dprintk("%s: error reg=0x%04x, ret=%i\n", __func__, reg, ret);
67*4882a593Smuzhiyun return -EIO;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun ret = i2c_transfer(priv->i2c, &msg2, 1);
71*4882a593Smuzhiyun if (ret != 1)
72*4882a593Smuzhiyun return -EIO;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun *p_data = buf2[0];
75*4882a593Smuzhiyun if (debug >= 2)
76*4882a593Smuzhiyun dprintk("%s: reg=0x%04X, data=0x%02X\n",
77*4882a593Smuzhiyun __func__, reg, buf2[0]);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Lock register latch so that multi-register read is atomic */
atbm8830_reglatch_lock(struct atbm_state * priv,int lock)83*4882a593Smuzhiyun static inline int atbm8830_reglatch_lock(struct atbm_state *priv, int lock)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun return atbm8830_write_reg(priv, REG_READ_LATCH, lock ? 1 : 0);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
set_osc_freq(struct atbm_state * priv,u32 freq)88*4882a593Smuzhiyun static int set_osc_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun u32 val;
91*4882a593Smuzhiyun u64 t;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* 0x100000 * freq / 30.4MHz */
94*4882a593Smuzhiyun t = (u64)0x100000 * freq;
95*4882a593Smuzhiyun do_div(t, 30400);
96*4882a593Smuzhiyun val = t;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_OSC_CLK, val);
99*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_OSC_CLK + 1, val >> 8);
100*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_OSC_CLK + 2, val >> 16);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
set_if_freq(struct atbm_state * priv,u32 freq)105*4882a593Smuzhiyun static int set_if_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun u32 fs = priv->config->osc_clk_freq;
109*4882a593Smuzhiyun u64 t;
110*4882a593Smuzhiyun u32 val;
111*4882a593Smuzhiyun u8 dat;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (freq != 0) {
114*4882a593Smuzhiyun /* 2 * PI * (freq - fs) / fs * (2 ^ 22) */
115*4882a593Smuzhiyun t = (u64) 2 * 31416 * (freq - fs);
116*4882a593Smuzhiyun t <<= 22;
117*4882a593Smuzhiyun do_div(t, fs);
118*4882a593Smuzhiyun do_div(t, 1000);
119*4882a593Smuzhiyun val = t;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 1);
122*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_IF_FREQ, val);
123*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_IF_FREQ+1, val >> 8);
124*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_IF_FREQ+2, val >> 16);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
127*4882a593Smuzhiyun dat &= 0xFC;
128*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
129*4882a593Smuzhiyun } else {
130*4882a593Smuzhiyun /* Zero IF */
131*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 0);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
134*4882a593Smuzhiyun dat &= 0xFC;
135*4882a593Smuzhiyun dat |= 0x02;
136*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun if (priv->config->zif_swap_iq)
139*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x03);
140*4882a593Smuzhiyun else
141*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x01);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
is_locked(struct atbm_state * priv,u8 * locked)147*4882a593Smuzhiyun static int is_locked(struct atbm_state *priv, u8 *locked)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun u8 status;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun atbm8830_read_reg(priv, REG_LOCK_STATUS, &status);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (locked != NULL)
154*4882a593Smuzhiyun *locked = (status == 1);
155*4882a593Smuzhiyun return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
set_agc_config(struct atbm_state * priv,u8 min,u8 max,u8 hold_loop)158*4882a593Smuzhiyun static int set_agc_config(struct atbm_state *priv,
159*4882a593Smuzhiyun u8 min, u8 max, u8 hold_loop)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun /* no effect if both min and max are zero */
162*4882a593Smuzhiyun if (!min && !max)
163*4882a593Smuzhiyun return 0;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_AGC_MIN, min);
166*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_AGC_MAX, max);
167*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_AGC_HOLD_LOOP, hold_loop);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return 0;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
set_static_channel_mode(struct atbm_state * priv)172*4882a593Smuzhiyun static int set_static_channel_mode(struct atbm_state *priv)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun int i;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun for (i = 0; i < 5; i++)
177*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x099B + i, 0x08);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x095B, 0x7F);
180*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x09CB, 0x01);
181*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x09CC, 0x7F);
182*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x09CD, 0x7F);
183*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x0E01, 0x20);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* For single carrier */
186*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x0B03, 0x0A);
187*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x0935, 0x10);
188*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x0936, 0x08);
189*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x093E, 0x08);
190*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x096E, 0x06);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* frame_count_max0 */
193*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x0B09, 0x00);
194*4882a593Smuzhiyun /* frame_count_max1 */
195*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x0B0A, 0x08);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun return 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
set_ts_config(struct atbm_state * priv)200*4882a593Smuzhiyun static int set_ts_config(struct atbm_state *priv)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun const struct atbm8830_config *cfg = priv->config;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /*Set parallel/serial ts mode*/
205*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_TS_SERIAL, cfg->serial_ts ? 1 : 0);
206*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_TS_CLK_MODE, cfg->serial_ts ? 1 : 0);
207*4882a593Smuzhiyun /*Set ts sampling edge*/
208*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_TS_SAMPLE_EDGE,
209*4882a593Smuzhiyun cfg->ts_sampling_edge ? 1 : 0);
210*4882a593Smuzhiyun /*Set ts clock freerun*/
211*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_TS_CLK_FREERUN,
212*4882a593Smuzhiyun cfg->ts_clk_gated ? 0 : 1);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun return 0;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
atbm8830_init(struct dvb_frontend * fe)217*4882a593Smuzhiyun static int atbm8830_init(struct dvb_frontend *fe)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun struct atbm_state *priv = fe->demodulator_priv;
220*4882a593Smuzhiyun const struct atbm8830_config *cfg = priv->config;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /*Set oscillator frequency*/
223*4882a593Smuzhiyun set_osc_freq(priv, cfg->osc_clk_freq);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /*Set IF frequency*/
226*4882a593Smuzhiyun set_if_freq(priv, cfg->if_freq);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /*Set AGC Config*/
229*4882a593Smuzhiyun set_agc_config(priv, cfg->agc_min, cfg->agc_max,
230*4882a593Smuzhiyun cfg->agc_hold_loop);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /*Set static channel mode*/
233*4882a593Smuzhiyun set_static_channel_mode(priv);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun set_ts_config(priv);
236*4882a593Smuzhiyun /*Turn off DSP reset*/
237*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x000A, 0);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /*SW version test*/
240*4882a593Smuzhiyun atbm8830_write_reg(priv, 0x020C, 11);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /* Run */
243*4882a593Smuzhiyun atbm8830_write_reg(priv, REG_DEMOD_RUN, 1);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun return 0;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun
atbm8830_release(struct dvb_frontend * fe)249*4882a593Smuzhiyun static void atbm8830_release(struct dvb_frontend *fe)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun struct atbm_state *state = fe->demodulator_priv;
252*4882a593Smuzhiyun dprintk("%s\n", __func__);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun kfree(state);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
atbm8830_set_fe(struct dvb_frontend * fe)257*4882a593Smuzhiyun static int atbm8830_set_fe(struct dvb_frontend *fe)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun struct atbm_state *priv = fe->demodulator_priv;
260*4882a593Smuzhiyun int i;
261*4882a593Smuzhiyun u8 locked = 0;
262*4882a593Smuzhiyun dprintk("%s\n", __func__);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* set frequency */
265*4882a593Smuzhiyun if (fe->ops.tuner_ops.set_params) {
266*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
267*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 1);
268*4882a593Smuzhiyun fe->ops.tuner_ops.set_params(fe);
269*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
270*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 0);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun /* start auto lock */
274*4882a593Smuzhiyun for (i = 0; i < 10; i++) {
275*4882a593Smuzhiyun mdelay(100);
276*4882a593Smuzhiyun dprintk("Try %d\n", i);
277*4882a593Smuzhiyun is_locked(priv, &locked);
278*4882a593Smuzhiyun if (locked != 0) {
279*4882a593Smuzhiyun dprintk("ATBM8830 locked!\n");
280*4882a593Smuzhiyun break;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun return 0;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
atbm8830_get_fe(struct dvb_frontend * fe,struct dtv_frontend_properties * c)287*4882a593Smuzhiyun static int atbm8830_get_fe(struct dvb_frontend *fe,
288*4882a593Smuzhiyun struct dtv_frontend_properties *c)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun dprintk("%s\n", __func__);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun /* TODO: get real readings from device */
293*4882a593Smuzhiyun /* inversion status */
294*4882a593Smuzhiyun c->inversion = INVERSION_OFF;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun /* bandwidth */
297*4882a593Smuzhiyun c->bandwidth_hz = 8000000;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun c->code_rate_HP = FEC_AUTO;
300*4882a593Smuzhiyun c->code_rate_LP = FEC_AUTO;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun c->modulation = QAM_AUTO;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* transmission mode */
305*4882a593Smuzhiyun c->transmission_mode = TRANSMISSION_MODE_AUTO;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun /* guard interval */
308*4882a593Smuzhiyun c->guard_interval = GUARD_INTERVAL_AUTO;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /* hierarchy */
311*4882a593Smuzhiyun c->hierarchy = HIERARCHY_NONE;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun return 0;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
atbm8830_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * fesettings)316*4882a593Smuzhiyun static int atbm8830_get_tune_settings(struct dvb_frontend *fe,
317*4882a593Smuzhiyun struct dvb_frontend_tune_settings *fesettings)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun fesettings->min_delay_ms = 0;
320*4882a593Smuzhiyun fesettings->step_size = 0;
321*4882a593Smuzhiyun fesettings->max_drift = 0;
322*4882a593Smuzhiyun return 0;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
atbm8830_read_status(struct dvb_frontend * fe,enum fe_status * fe_status)325*4882a593Smuzhiyun static int atbm8830_read_status(struct dvb_frontend *fe,
326*4882a593Smuzhiyun enum fe_status *fe_status)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun struct atbm_state *priv = fe->demodulator_priv;
329*4882a593Smuzhiyun u8 locked = 0;
330*4882a593Smuzhiyun u8 agc_locked = 0;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun dprintk("%s\n", __func__);
333*4882a593Smuzhiyun *fe_status = 0;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun is_locked(priv, &locked);
336*4882a593Smuzhiyun if (locked) {
337*4882a593Smuzhiyun *fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
338*4882a593Smuzhiyun FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun atbm8830_read_reg(priv, REG_AGC_LOCK, &agc_locked);
343*4882a593Smuzhiyun dprintk("AGC Lock: %d\n", agc_locked);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun return 0;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
atbm8830_read_ber(struct dvb_frontend * fe,u32 * ber)348*4882a593Smuzhiyun static int atbm8830_read_ber(struct dvb_frontend *fe, u32 *ber)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun struct atbm_state *priv = fe->demodulator_priv;
351*4882a593Smuzhiyun u32 frame_err;
352*4882a593Smuzhiyun u8 t;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun dprintk("%s\n", __func__);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun atbm8830_reglatch_lock(priv, 1);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun atbm8830_read_reg(priv, REG_FRAME_ERR_CNT + 1, &t);
359*4882a593Smuzhiyun frame_err = t & 0x7F;
360*4882a593Smuzhiyun frame_err <<= 8;
361*4882a593Smuzhiyun atbm8830_read_reg(priv, REG_FRAME_ERR_CNT, &t);
362*4882a593Smuzhiyun frame_err |= t;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun atbm8830_reglatch_lock(priv, 0);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun *ber = frame_err * 100 / 32767;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun dprintk("%s: ber=0x%x\n", __func__, *ber);
369*4882a593Smuzhiyun return 0;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
atbm8830_read_signal_strength(struct dvb_frontend * fe,u16 * signal)372*4882a593Smuzhiyun static int atbm8830_read_signal_strength(struct dvb_frontend *fe, u16 *signal)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun struct atbm_state *priv = fe->demodulator_priv;
375*4882a593Smuzhiyun u32 pwm;
376*4882a593Smuzhiyun u8 t;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun dprintk("%s\n", __func__);
379*4882a593Smuzhiyun atbm8830_reglatch_lock(priv, 1);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun atbm8830_read_reg(priv, REG_AGC_PWM_VAL + 1, &t);
382*4882a593Smuzhiyun pwm = t & 0x03;
383*4882a593Smuzhiyun pwm <<= 8;
384*4882a593Smuzhiyun atbm8830_read_reg(priv, REG_AGC_PWM_VAL, &t);
385*4882a593Smuzhiyun pwm |= t;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun atbm8830_reglatch_lock(priv, 0);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun dprintk("AGC PWM = 0x%02X\n", pwm);
390*4882a593Smuzhiyun pwm = 0x400 - pwm;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun *signal = pwm * 0x10000 / 0x400;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun return 0;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
atbm8830_read_snr(struct dvb_frontend * fe,u16 * snr)397*4882a593Smuzhiyun static int atbm8830_read_snr(struct dvb_frontend *fe, u16 *snr)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun dprintk("%s\n", __func__);
400*4882a593Smuzhiyun *snr = 0;
401*4882a593Smuzhiyun return 0;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
atbm8830_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)404*4882a593Smuzhiyun static int atbm8830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun dprintk("%s\n", __func__);
407*4882a593Smuzhiyun *ucblocks = 0;
408*4882a593Smuzhiyun return 0;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
atbm8830_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)411*4882a593Smuzhiyun static int atbm8830_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun struct atbm_state *priv = fe->demodulator_priv;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun return atbm8830_write_reg(priv, REG_I2C_GATE, enable ? 1 : 0);
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun static const struct dvb_frontend_ops atbm8830_ops = {
419*4882a593Smuzhiyun .delsys = { SYS_DTMB },
420*4882a593Smuzhiyun .info = {
421*4882a593Smuzhiyun .name = "AltoBeam ATBM8830/8831 DMB-TH",
422*4882a593Smuzhiyun .frequency_min_hz = 474 * MHz,
423*4882a593Smuzhiyun .frequency_max_hz = 858 * MHz,
424*4882a593Smuzhiyun .frequency_stepsize_hz = 10 * kHz,
425*4882a593Smuzhiyun .caps =
426*4882a593Smuzhiyun FE_CAN_FEC_AUTO |
427*4882a593Smuzhiyun FE_CAN_QAM_AUTO |
428*4882a593Smuzhiyun FE_CAN_TRANSMISSION_MODE_AUTO |
429*4882a593Smuzhiyun FE_CAN_GUARD_INTERVAL_AUTO
430*4882a593Smuzhiyun },
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun .release = atbm8830_release,
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun .init = atbm8830_init,
435*4882a593Smuzhiyun .sleep = NULL,
436*4882a593Smuzhiyun .write = NULL,
437*4882a593Smuzhiyun .i2c_gate_ctrl = atbm8830_i2c_gate_ctrl,
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun .set_frontend = atbm8830_set_fe,
440*4882a593Smuzhiyun .get_frontend = atbm8830_get_fe,
441*4882a593Smuzhiyun .get_tune_settings = atbm8830_get_tune_settings,
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun .read_status = atbm8830_read_status,
444*4882a593Smuzhiyun .read_ber = atbm8830_read_ber,
445*4882a593Smuzhiyun .read_signal_strength = atbm8830_read_signal_strength,
446*4882a593Smuzhiyun .read_snr = atbm8830_read_snr,
447*4882a593Smuzhiyun .read_ucblocks = atbm8830_read_ucblocks,
448*4882a593Smuzhiyun };
449*4882a593Smuzhiyun
atbm8830_attach(const struct atbm8830_config * config,struct i2c_adapter * i2c)450*4882a593Smuzhiyun struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
451*4882a593Smuzhiyun struct i2c_adapter *i2c)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun struct atbm_state *priv = NULL;
454*4882a593Smuzhiyun u8 data = 0;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun dprintk("%s()\n", __func__);
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun if (config == NULL || i2c == NULL)
459*4882a593Smuzhiyun return NULL;
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun priv = kzalloc(sizeof(struct atbm_state), GFP_KERNEL);
462*4882a593Smuzhiyun if (priv == NULL)
463*4882a593Smuzhiyun goto error_out;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun priv->config = config;
466*4882a593Smuzhiyun priv->i2c = i2c;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun /* check if the demod is there */
469*4882a593Smuzhiyun if (atbm8830_read_reg(priv, REG_CHIP_ID, &data) != 0) {
470*4882a593Smuzhiyun dprintk("%s atbm8830/8831 not found at i2c addr 0x%02X\n",
471*4882a593Smuzhiyun __func__, priv->config->demod_address);
472*4882a593Smuzhiyun goto error_out;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun dprintk("atbm8830 chip id: 0x%02X\n", data);
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun memcpy(&priv->frontend.ops, &atbm8830_ops,
477*4882a593Smuzhiyun sizeof(struct dvb_frontend_ops));
478*4882a593Smuzhiyun priv->frontend.demodulator_priv = priv;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun atbm8830_init(&priv->frontend);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun atbm8830_i2c_gate_ctrl(&priv->frontend, 1);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun return &priv->frontend;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun error_out:
487*4882a593Smuzhiyun dprintk("%s() error_out\n", __func__);
488*4882a593Smuzhiyun kfree(priv);
489*4882a593Smuzhiyun return NULL;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun EXPORT_SYMBOL(atbm8830_attach);
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver");
495*4882a593Smuzhiyun MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
496*4882a593Smuzhiyun MODULE_LICENSE("GPL");
497