1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Afatech AF9033 demodulator driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 6*4882a593Smuzhiyun * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef AF9033_H 10*4882a593Smuzhiyun #define AF9033_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * I2C address: 0x1c, 0x1d, 0x1e, 0x1f 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct af9033_config { 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * clock Hz 18*4882a593Smuzhiyun * 12000000, 22000000, 24000000, 34000000, 32000000, 28000000, 26000000, 19*4882a593Smuzhiyun * 30000000, 36000000, 20480000, 16384000 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun u32 clock; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * ADC multiplier 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define AF9033_ADC_MULTIPLIER_1X 0 27*4882a593Smuzhiyun #define AF9033_ADC_MULTIPLIER_2X 1 28*4882a593Smuzhiyun u8 adc_multiplier; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * tuner 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun #define AF9033_TUNER_TUA9001 0x27 /* Infineon TUA 9001 */ 34*4882a593Smuzhiyun #define AF9033_TUNER_FC0011 0x28 /* Fitipower FC0011 */ 35*4882a593Smuzhiyun #define AF9033_TUNER_FC0012 0x2e /* Fitipower FC0012 */ 36*4882a593Smuzhiyun #define AF9033_TUNER_MXL5007T 0xa0 /* MaxLinear MxL5007T */ 37*4882a593Smuzhiyun #define AF9033_TUNER_TDA18218 0xa1 /* NXP TDA 18218HN */ 38*4882a593Smuzhiyun #define AF9033_TUNER_FC2580 0x32 /* FCI FC2580 */ 39*4882a593Smuzhiyun /* 50-5f Omega */ 40*4882a593Smuzhiyun #define AF9033_TUNER_IT9135_38 0x38 /* Omega */ 41*4882a593Smuzhiyun #define AF9033_TUNER_IT9135_51 0x51 /* Omega LNA config 1 */ 42*4882a593Smuzhiyun #define AF9033_TUNER_IT9135_52 0x52 /* Omega LNA config 2 */ 43*4882a593Smuzhiyun /* 60-6f Omega v2 */ 44*4882a593Smuzhiyun #define AF9033_TUNER_IT9135_60 0x60 /* Omega v2 */ 45*4882a593Smuzhiyun #define AF9033_TUNER_IT9135_61 0x61 /* Omega v2 LNA config 1 */ 46*4882a593Smuzhiyun #define AF9033_TUNER_IT9135_62 0x62 /* Omega v2 LNA config 2 */ 47*4882a593Smuzhiyun u8 tuner; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * TS settings 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define AF9033_TS_MODE_USB 0 53*4882a593Smuzhiyun #define AF9033_TS_MODE_PARALLEL 1 54*4882a593Smuzhiyun #define AF9033_TS_MODE_SERIAL 2 55*4882a593Smuzhiyun u8 ts_mode:2; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * input spectrum inversion 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun bool spec_inv; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun bool dyn0_clk; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * PID filter ops 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun struct af9033_ops *ops; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * frontend 74*4882a593Smuzhiyun * returned by that driver 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun struct dvb_frontend **fe; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * regmap for IT913x integrated tuner driver 80*4882a593Smuzhiyun * returned by that driver 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun struct regmap *regmap; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun struct af9033_ops { 86*4882a593Smuzhiyun int (*pid_filter_ctrl)(struct dvb_frontend *fe, int onoff); 87*4882a593Smuzhiyun int (*pid_filter)(struct dvb_frontend *fe, int index, u16 pid, 88*4882a593Smuzhiyun int onoff); 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* AF9033_H */ 92