1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * SECO X86 Boards CEC register defines 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Ettore Chimenti <ek5.chimenti@gmail.com> 6*4882a593Smuzhiyun * Copyright (C) 2018, SECO Spa. 7*4882a593Smuzhiyun * Copyright (C) 2018, Aidilab Srl. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __SECO_CEC_H__ 11*4882a593Smuzhiyun #define __SECO_CEC_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define SECOCEC_MAX_ADDRS 1 14*4882a593Smuzhiyun #define SECOCEC_DEV_NAME "secocec" 15*4882a593Smuzhiyun #define SECOCEC_LATEST_FW 0x0f0b 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define SMBTIMEOUT 0xfff 18*4882a593Smuzhiyun #define SMB_POLL_UDELAY 10 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SMBUS_WRITE 0 21*4882a593Smuzhiyun #define SMBUS_READ 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CMD_BYTE_DATA 0 24*4882a593Smuzhiyun #define CMD_WORD_DATA 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * SMBus definitons for Braswell 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define BRA_DONE_STATUS BIT(7) 31*4882a593Smuzhiyun #define BRA_INUSE_STS BIT(6) 32*4882a593Smuzhiyun #define BRA_FAILED_OP BIT(4) 33*4882a593Smuzhiyun #define BRA_BUS_ERR BIT(3) 34*4882a593Smuzhiyun #define BRA_DEV_ERR BIT(2) 35*4882a593Smuzhiyun #define BRA_INTR BIT(1) 36*4882a593Smuzhiyun #define BRA_HOST_BUSY BIT(0) 37*4882a593Smuzhiyun #define BRA_HSTS_ERR_MASK (BRA_FAILED_OP | BRA_BUS_ERR | BRA_DEV_ERR) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define BRA_PEC_EN BIT(7) 40*4882a593Smuzhiyun #define BRA_START BIT(6) 41*4882a593Smuzhiyun #define BRA_LAST__BYTE BIT(5) 42*4882a593Smuzhiyun #define BRA_INTREN BIT(0) 43*4882a593Smuzhiyun #define BRA_SMB_CMD (7 << 2) 44*4882a593Smuzhiyun #define BRA_SMB_CMD_QUICK (0 << 2) 45*4882a593Smuzhiyun #define BRA_SMB_CMD_BYTE (1 << 2) 46*4882a593Smuzhiyun #define BRA_SMB_CMD_BYTE_DATA (2 << 2) 47*4882a593Smuzhiyun #define BRA_SMB_CMD_WORD_DATA (3 << 2) 48*4882a593Smuzhiyun #define BRA_SMB_CMD_PROCESS_CALL (4 << 2) 49*4882a593Smuzhiyun #define BRA_SMB_CMD_BLOCK (5 << 2) 50*4882a593Smuzhiyun #define BRA_SMB_CMD_I2CREAD (6 << 2) 51*4882a593Smuzhiyun #define BRA_SMB_CMD_BLOCK_PROCESS (7 << 2) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define BRA_SMB_BASE_ADDR 0x2040 54*4882a593Smuzhiyun #define HSTS (BRA_SMB_BASE_ADDR + 0) 55*4882a593Smuzhiyun #define HCNT (BRA_SMB_BASE_ADDR + 2) 56*4882a593Smuzhiyun #define HCMD (BRA_SMB_BASE_ADDR + 3) 57*4882a593Smuzhiyun #define XMIT_SLVA (BRA_SMB_BASE_ADDR + 4) 58*4882a593Smuzhiyun #define HDAT0 (BRA_SMB_BASE_ADDR + 5) 59*4882a593Smuzhiyun #define HDAT1 (BRA_SMB_BASE_ADDR + 6) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * Microcontroller Address 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define SECOCEC_MICRO_ADDRESS 0x40 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * STM32 SMBus Registers 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define SECOCEC_VERSION 0x00 72*4882a593Smuzhiyun #define SECOCEC_ENABLE_REG_1 0x01 73*4882a593Smuzhiyun #define SECOCEC_ENABLE_REG_2 0x02 74*4882a593Smuzhiyun #define SECOCEC_STATUS_REG_1 0x03 75*4882a593Smuzhiyun #define SECOCEC_STATUS_REG_2 0x04 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define SECOCEC_STATUS 0x28 78*4882a593Smuzhiyun #define SECOCEC_DEVICE_LA 0x29 79*4882a593Smuzhiyun #define SECOCEC_READ_OPERATION_ID 0x2a 80*4882a593Smuzhiyun #define SECOCEC_READ_DATA_LENGTH 0x2b 81*4882a593Smuzhiyun #define SECOCEC_READ_DATA_00 0x2c 82*4882a593Smuzhiyun #define SECOCEC_READ_DATA_02 0x2d 83*4882a593Smuzhiyun #define SECOCEC_READ_DATA_04 0x2e 84*4882a593Smuzhiyun #define SECOCEC_READ_DATA_06 0x2f 85*4882a593Smuzhiyun #define SECOCEC_READ_DATA_08 0x30 86*4882a593Smuzhiyun #define SECOCEC_READ_DATA_10 0x31 87*4882a593Smuzhiyun #define SECOCEC_READ_DATA_12 0x32 88*4882a593Smuzhiyun #define SECOCEC_READ_BYTE0 0x33 89*4882a593Smuzhiyun #define SECOCEC_WRITE_OPERATION_ID 0x34 90*4882a593Smuzhiyun #define SECOCEC_WRITE_DATA_LENGTH 0x35 91*4882a593Smuzhiyun #define SECOCEC_WRITE_DATA_00 0x36 92*4882a593Smuzhiyun #define SECOCEC_WRITE_DATA_02 0x37 93*4882a593Smuzhiyun #define SECOCEC_WRITE_DATA_04 0x38 94*4882a593Smuzhiyun #define SECOCEC_WRITE_DATA_06 0x39 95*4882a593Smuzhiyun #define SECOCEC_WRITE_DATA_08 0x3a 96*4882a593Smuzhiyun #define SECOCEC_WRITE_DATA_10 0x3b 97*4882a593Smuzhiyun #define SECOCEC_WRITE_DATA_12 0x3c 98*4882a593Smuzhiyun #define SECOCEC_WRITE_BYTE0 0x3d 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define SECOCEC_IR_READ_DATA 0x3e 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * IR 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define SECOCEC_IR_COMMAND_MASK 0x007F 107*4882a593Smuzhiyun #define SECOCEC_IR_COMMAND_SHL 0 108*4882a593Smuzhiyun #define SECOCEC_IR_ADDRESS_MASK 0x1F00 109*4882a593Smuzhiyun #define SECOCEC_IR_ADDRESS_SHL 8 110*4882a593Smuzhiyun #define SECOCEC_IR_TOGGLE_MASK 0x8000 111*4882a593Smuzhiyun #define SECOCEC_IR_TOGGLE_SHL 15 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* 114*4882a593Smuzhiyun * Enabling register 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define SECOCEC_ENABLE_REG_1_CEC 0x1000 118*4882a593Smuzhiyun #define SECOCEC_ENABLE_REG_1_IR 0x2000 119*4882a593Smuzhiyun #define SECOCEC_ENABLE_REG_1_IR_PASSTHROUGH 0x4000 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* 122*4882a593Smuzhiyun * Status register 123*4882a593Smuzhiyun */ 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define SECOCEC_STATUS_REG_1_CEC SECOCEC_ENABLE_REG_1_CEC 126*4882a593Smuzhiyun #define SECOCEC_STATUS_REG_1_IR SECOCEC_ENABLE_REG_1_IR 127*4882a593Smuzhiyun #define SECOCEC_STATUS_REG_1_IR_PASSTHR SECOCEC_ENABLE_REG_1_IR_PASSTHR 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* 130*4882a593Smuzhiyun * Status data 131*4882a593Smuzhiyun */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define SECOCEC_STATUS_MSG_RECEIVED_MASK BIT(0) 134*4882a593Smuzhiyun #define SECOCEC_STATUS_RX_ERROR_MASK BIT(1) 135*4882a593Smuzhiyun #define SECOCEC_STATUS_MSG_SENT_MASK BIT(2) 136*4882a593Smuzhiyun #define SECOCEC_STATUS_TX_ERROR_MASK BIT(3) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define SECOCEC_STATUS_TX_NACK_ERROR BIT(4) 139*4882a593Smuzhiyun #define SECOCEC_STATUS_RX_OVERFLOW_MASK BIT(5) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* __SECO_CEC_H__ */ 142