1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* drivers/media/platform/s5p-cec/regs-cec.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2010 Samsung Electronics 5*4882a593Smuzhiyun * http://www.samsung.com/ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * register header file for Samsung TVOUT driver 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __EXYNOS_REGS__H 11*4882a593Smuzhiyun #define __EXYNOS_REGS__H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Register part 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define S5P_CEC_STATUS_0 (0x0000) 17*4882a593Smuzhiyun #define S5P_CEC_STATUS_1 (0x0004) 18*4882a593Smuzhiyun #define S5P_CEC_STATUS_2 (0x0008) 19*4882a593Smuzhiyun #define S5P_CEC_STATUS_3 (0x000C) 20*4882a593Smuzhiyun #define S5P_CEC_IRQ_MASK (0x0010) 21*4882a593Smuzhiyun #define S5P_CEC_IRQ_CLEAR (0x0014) 22*4882a593Smuzhiyun #define S5P_CEC_LOGIC_ADDR (0x0020) 23*4882a593Smuzhiyun #define S5P_CEC_DIVISOR_0 (0x0030) 24*4882a593Smuzhiyun #define S5P_CEC_DIVISOR_1 (0x0034) 25*4882a593Smuzhiyun #define S5P_CEC_DIVISOR_2 (0x0038) 26*4882a593Smuzhiyun #define S5P_CEC_DIVISOR_3 (0x003C) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define S5P_CEC_TX_CTRL (0x0040) 29*4882a593Smuzhiyun #define S5P_CEC_TX_BYTES (0x0044) 30*4882a593Smuzhiyun #define S5P_CEC_TX_STAT0 (0x0060) 31*4882a593Smuzhiyun #define S5P_CEC_TX_STAT1 (0x0064) 32*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF0 (0x0080) 33*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF1 (0x0084) 34*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF2 (0x0088) 35*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF3 (0x008C) 36*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF4 (0x0090) 37*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF5 (0x0094) 38*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF6 (0x0098) 39*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF7 (0x009C) 40*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF8 (0x00A0) 41*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF9 (0x00A4) 42*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF10 (0x00A8) 43*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF11 (0x00AC) 44*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF12 (0x00B0) 45*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF13 (0x00B4) 46*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF14 (0x00B8) 47*4882a593Smuzhiyun #define S5P_CEC_TX_BUFF15 (0x00BC) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define S5P_CEC_RX_CTRL (0x00C0) 50*4882a593Smuzhiyun #define S5P_CEC_RX_STAT0 (0x00E0) 51*4882a593Smuzhiyun #define S5P_CEC_RX_STAT1 (0x00E4) 52*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF0 (0x0100) 53*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF1 (0x0104) 54*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF2 (0x0108) 55*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF3 (0x010C) 56*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF4 (0x0110) 57*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF5 (0x0114) 58*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF6 (0x0118) 59*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF7 (0x011C) 60*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF8 (0x0120) 61*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF9 (0x0124) 62*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF10 (0x0128) 63*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF11 (0x012C) 64*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF12 (0x0130) 65*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF13 (0x0134) 66*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF14 (0x0138) 67*4882a593Smuzhiyun #define S5P_CEC_RX_BUFF15 (0x013C) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define S5P_CEC_RX_FILTER_CTRL (0x0180) 70*4882a593Smuzhiyun #define S5P_CEC_RX_FILTER_TH (0x0184) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * Bit definition part 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun #define S5P_CEC_IRQ_TX_DONE (1<<0) 76*4882a593Smuzhiyun #define S5P_CEC_IRQ_TX_ERROR (1<<1) 77*4882a593Smuzhiyun #define S5P_CEC_IRQ_RX_DONE (1<<4) 78*4882a593Smuzhiyun #define S5P_CEC_IRQ_RX_ERROR (1<<5) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define S5P_CEC_TX_CTRL_START (1<<0) 81*4882a593Smuzhiyun #define S5P_CEC_TX_CTRL_BCAST (1<<1) 82*4882a593Smuzhiyun #define S5P_CEC_TX_CTRL_RETRY (0x04<<4) 83*4882a593Smuzhiyun #define S5P_CEC_TX_CTRL_RESET (1<<7) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define S5P_CEC_RX_CTRL_ENABLE (1<<0) 86*4882a593Smuzhiyun #define S5P_CEC_RX_CTRL_RESET (1<<7) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define S5P_CEC_LOGIC_ADDR_MASK (0xF) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* PMU Registers for PHY */ 91*4882a593Smuzhiyun #define EXYNOS_HDMI_PHY_CONTROL 0x700 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* __EXYNOS_REGS__H */ 94