xref: /OK3568_Linux_fs/kernel/drivers/mailbox/platform_mhu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2016 BayLibre SAS.
4*4882a593Smuzhiyun  * Author: Neil Armstrong <narmstrong@baylibre.com>
5*4882a593Smuzhiyun  * Synchronised with arm_mhu.c from :
6*4882a593Smuzhiyun  * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
7*4882a593Smuzhiyun  * Copyright (C) 2015 Linaro Ltd.
8*4882a593Smuzhiyun  * Author: Jassi Brar <jaswinder.singh@linaro.org>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/spinlock.h>
13*4882a593Smuzhiyun #include <linux/mutex.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/io.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/mailbox_controller.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define INTR_SET_OFS	0x0
23*4882a593Smuzhiyun #define INTR_STAT_OFS	0x4
24*4882a593Smuzhiyun #define INTR_CLR_OFS	0x8
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define MHU_SEC_OFFSET	0x0
27*4882a593Smuzhiyun #define MHU_LP_OFFSET	0xc
28*4882a593Smuzhiyun #define MHU_HP_OFFSET	0x18
29*4882a593Smuzhiyun #define TX_REG_OFFSET	0x24
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define MHU_CHANS	3
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun struct platform_mhu_link {
34*4882a593Smuzhiyun 	int irq;
35*4882a593Smuzhiyun 	void __iomem *tx_reg;
36*4882a593Smuzhiyun 	void __iomem *rx_reg;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun struct platform_mhu {
40*4882a593Smuzhiyun 	void __iomem *base;
41*4882a593Smuzhiyun 	struct platform_mhu_link mlink[MHU_CHANS];
42*4882a593Smuzhiyun 	struct mbox_chan chan[MHU_CHANS];
43*4882a593Smuzhiyun 	struct mbox_controller mbox;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
platform_mhu_rx_interrupt(int irq,void * p)46*4882a593Smuzhiyun static irqreturn_t platform_mhu_rx_interrupt(int irq, void *p)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	struct mbox_chan *chan = p;
49*4882a593Smuzhiyun 	struct platform_mhu_link *mlink = chan->con_priv;
50*4882a593Smuzhiyun 	u32 val;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
53*4882a593Smuzhiyun 	if (!val)
54*4882a593Smuzhiyun 		return IRQ_NONE;
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	mbox_chan_received_data(chan, (void *)&val);
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	return IRQ_HANDLED;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
platform_mhu_last_tx_done(struct mbox_chan * chan)63*4882a593Smuzhiyun static bool platform_mhu_last_tx_done(struct mbox_chan *chan)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	struct platform_mhu_link *mlink = chan->con_priv;
66*4882a593Smuzhiyun 	u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	return (val == 0);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
platform_mhu_send_data(struct mbox_chan * chan,void * data)71*4882a593Smuzhiyun static int platform_mhu_send_data(struct mbox_chan *chan, void *data)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	struct platform_mhu_link *mlink = chan->con_priv;
74*4882a593Smuzhiyun 	u32 *arg = data;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
platform_mhu_startup(struct mbox_chan * chan)81*4882a593Smuzhiyun static int platform_mhu_startup(struct mbox_chan *chan)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	struct platform_mhu_link *mlink = chan->con_priv;
84*4882a593Smuzhiyun 	u32 val;
85*4882a593Smuzhiyun 	int ret;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
88*4882a593Smuzhiyun 	writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	ret = request_irq(mlink->irq, platform_mhu_rx_interrupt,
91*4882a593Smuzhiyun 			  IRQF_SHARED, "platform_mhu_link", chan);
92*4882a593Smuzhiyun 	if (ret) {
93*4882a593Smuzhiyun 		dev_err(chan->mbox->dev,
94*4882a593Smuzhiyun 			"Unable to acquire IRQ %d\n", mlink->irq);
95*4882a593Smuzhiyun 		return ret;
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
platform_mhu_shutdown(struct mbox_chan * chan)101*4882a593Smuzhiyun static void platform_mhu_shutdown(struct mbox_chan *chan)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	struct platform_mhu_link *mlink = chan->con_priv;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	free_irq(mlink->irq, chan);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun static const struct mbox_chan_ops platform_mhu_ops = {
109*4882a593Smuzhiyun 	.send_data = platform_mhu_send_data,
110*4882a593Smuzhiyun 	.startup = platform_mhu_startup,
111*4882a593Smuzhiyun 	.shutdown = platform_mhu_shutdown,
112*4882a593Smuzhiyun 	.last_tx_done = platform_mhu_last_tx_done,
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
platform_mhu_probe(struct platform_device * pdev)115*4882a593Smuzhiyun static int platform_mhu_probe(struct platform_device *pdev)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	int i, err;
118*4882a593Smuzhiyun 	struct platform_mhu *mhu;
119*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
120*4882a593Smuzhiyun 	struct resource *res;
121*4882a593Smuzhiyun 	int platform_mhu_reg[MHU_CHANS] = {
122*4882a593Smuzhiyun 		MHU_SEC_OFFSET, MHU_LP_OFFSET, MHU_HP_OFFSET
123*4882a593Smuzhiyun 	};
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	/* Allocate memory for device */
126*4882a593Smuzhiyun 	mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
127*4882a593Smuzhiyun 	if (!mhu)
128*4882a593Smuzhiyun 		return -ENOMEM;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
131*4882a593Smuzhiyun 	mhu->base = devm_ioremap_resource(dev, res);
132*4882a593Smuzhiyun 	if (IS_ERR(mhu->base)) {
133*4882a593Smuzhiyun 		dev_err(dev, "ioremap failed\n");
134*4882a593Smuzhiyun 		return PTR_ERR(mhu->base);
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	for (i = 0; i < MHU_CHANS; i++) {
138*4882a593Smuzhiyun 		mhu->chan[i].con_priv = &mhu->mlink[i];
139*4882a593Smuzhiyun 		mhu->mlink[i].irq = platform_get_irq(pdev, i);
140*4882a593Smuzhiyun 		if (mhu->mlink[i].irq < 0) {
141*4882a593Smuzhiyun 			dev_err(dev, "failed to get irq%d\n", i);
142*4882a593Smuzhiyun 			return mhu->mlink[i].irq;
143*4882a593Smuzhiyun 		}
144*4882a593Smuzhiyun 		mhu->mlink[i].rx_reg = mhu->base + platform_mhu_reg[i];
145*4882a593Smuzhiyun 		mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
146*4882a593Smuzhiyun 	}
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	mhu->mbox.dev = dev;
149*4882a593Smuzhiyun 	mhu->mbox.chans = &mhu->chan[0];
150*4882a593Smuzhiyun 	mhu->mbox.num_chans = MHU_CHANS;
151*4882a593Smuzhiyun 	mhu->mbox.ops = &platform_mhu_ops;
152*4882a593Smuzhiyun 	mhu->mbox.txdone_irq = false;
153*4882a593Smuzhiyun 	mhu->mbox.txdone_poll = true;
154*4882a593Smuzhiyun 	mhu->mbox.txpoll_period = 1;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	platform_set_drvdata(pdev, mhu);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	err = devm_mbox_controller_register(dev, &mhu->mbox);
159*4882a593Smuzhiyun 	if (err) {
160*4882a593Smuzhiyun 		dev_err(dev, "Failed to register mailboxes %d\n", err);
161*4882a593Smuzhiyun 		return err;
162*4882a593Smuzhiyun 	}
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	dev_info(dev, "Platform MHU Mailbox registered\n");
165*4882a593Smuzhiyun 	return 0;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun static const struct of_device_id platform_mhu_dt_ids[] = {
169*4882a593Smuzhiyun 	{ .compatible = "amlogic,meson-gxbb-mhu", },
170*4882a593Smuzhiyun 	{ /* sentinel */ },
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, platform_mhu_dt_ids);
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun static struct platform_driver platform_mhu_driver = {
175*4882a593Smuzhiyun 	.probe	= platform_mhu_probe,
176*4882a593Smuzhiyun 	.driver = {
177*4882a593Smuzhiyun 		.name = "platform-mhu",
178*4882a593Smuzhiyun 		.of_match_table	= platform_mhu_dt_ids,
179*4882a593Smuzhiyun 	},
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun module_platform_driver(platform_mhu_driver);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
185*4882a593Smuzhiyun MODULE_ALIAS("platform:platform-mhu");
186*4882a593Smuzhiyun MODULE_DESCRIPTION("Platform MHU Driver");
187*4882a593Smuzhiyun MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
188