1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * APM X-Gene SLIMpro MailBox Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015, Applied Micro Circuits Corporation
6*4882a593Smuzhiyun * Author: Feng Kan fkan@apm.com
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/acpi.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/mailbox_controller.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/spinlock.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define MBOX_CON_NAME "slimpro-mbox"
19*4882a593Smuzhiyun #define MBOX_REG_SET_OFFSET 0x1000
20*4882a593Smuzhiyun #define MBOX_CNT 8
21*4882a593Smuzhiyun #define MBOX_STATUS_AVAIL_MASK BIT(16)
22*4882a593Smuzhiyun #define MBOX_STATUS_ACK_MASK BIT(0)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Configuration and Status Registers */
25*4882a593Smuzhiyun #define REG_DB_IN 0x00
26*4882a593Smuzhiyun #define REG_DB_DIN0 0x04
27*4882a593Smuzhiyun #define REG_DB_DIN1 0x08
28*4882a593Smuzhiyun #define REG_DB_OUT 0x10
29*4882a593Smuzhiyun #define REG_DB_DOUT0 0x14
30*4882a593Smuzhiyun #define REG_DB_DOUT1 0x18
31*4882a593Smuzhiyun #define REG_DB_STAT 0x20
32*4882a593Smuzhiyun #define REG_DB_STATMASK 0x24
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /**
35*4882a593Smuzhiyun * X-Gene SlimPRO mailbox channel information
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * @dev: Device to which it is attached
38*4882a593Smuzhiyun * @chan: Pointer to mailbox communication channel
39*4882a593Smuzhiyun * @reg: Base address to access channel registers
40*4882a593Smuzhiyun * @irq: Interrupt number of the channel
41*4882a593Smuzhiyun * @rx_msg: Received message storage
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun struct slimpro_mbox_chan {
44*4882a593Smuzhiyun struct device *dev;
45*4882a593Smuzhiyun struct mbox_chan *chan;
46*4882a593Smuzhiyun void __iomem *reg;
47*4882a593Smuzhiyun int irq;
48*4882a593Smuzhiyun u32 rx_msg[3];
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /**
52*4882a593Smuzhiyun * X-Gene SlimPRO Mailbox controller data
53*4882a593Smuzhiyun *
54*4882a593Smuzhiyun * X-Gene SlimPRO Mailbox controller has 8 commnunication channels.
55*4882a593Smuzhiyun * Each channel has a separate IRQ number assgined to it.
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun * @mb_ctrl: Representation of the commnunication channel controller
58*4882a593Smuzhiyun * @mc: Array of SlimPRO mailbox channels of the controller
59*4882a593Smuzhiyun * @chans: Array of mailbox communication channels
60*4882a593Smuzhiyun *
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun struct slimpro_mbox {
63*4882a593Smuzhiyun struct mbox_controller mb_ctrl;
64*4882a593Smuzhiyun struct slimpro_mbox_chan mc[MBOX_CNT];
65*4882a593Smuzhiyun struct mbox_chan chans[MBOX_CNT];
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
mb_chan_send_msg(struct slimpro_mbox_chan * mb_chan,u32 * msg)68*4882a593Smuzhiyun static void mb_chan_send_msg(struct slimpro_mbox_chan *mb_chan, u32 *msg)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun writel(msg[1], mb_chan->reg + REG_DB_DOUT0);
71*4882a593Smuzhiyun writel(msg[2], mb_chan->reg + REG_DB_DOUT1);
72*4882a593Smuzhiyun writel(msg[0], mb_chan->reg + REG_DB_OUT);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
mb_chan_recv_msg(struct slimpro_mbox_chan * mb_chan)75*4882a593Smuzhiyun static void mb_chan_recv_msg(struct slimpro_mbox_chan *mb_chan)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun mb_chan->rx_msg[1] = readl(mb_chan->reg + REG_DB_DIN0);
78*4882a593Smuzhiyun mb_chan->rx_msg[2] = readl(mb_chan->reg + REG_DB_DIN1);
79*4882a593Smuzhiyun mb_chan->rx_msg[0] = readl(mb_chan->reg + REG_DB_IN);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
mb_chan_status_ack(struct slimpro_mbox_chan * mb_chan)82*4882a593Smuzhiyun static int mb_chan_status_ack(struct slimpro_mbox_chan *mb_chan)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun u32 val = readl(mb_chan->reg + REG_DB_STAT);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (val & MBOX_STATUS_ACK_MASK) {
87*4882a593Smuzhiyun writel(MBOX_STATUS_ACK_MASK, mb_chan->reg + REG_DB_STAT);
88*4882a593Smuzhiyun return 1;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
mb_chan_status_avail(struct slimpro_mbox_chan * mb_chan)93*4882a593Smuzhiyun static int mb_chan_status_avail(struct slimpro_mbox_chan *mb_chan)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun u32 val = readl(mb_chan->reg + REG_DB_STAT);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (val & MBOX_STATUS_AVAIL_MASK) {
98*4882a593Smuzhiyun mb_chan_recv_msg(mb_chan);
99*4882a593Smuzhiyun writel(MBOX_STATUS_AVAIL_MASK, mb_chan->reg + REG_DB_STAT);
100*4882a593Smuzhiyun return 1;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
slimpro_mbox_irq(int irq,void * id)105*4882a593Smuzhiyun static irqreturn_t slimpro_mbox_irq(int irq, void *id)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct slimpro_mbox_chan *mb_chan = id;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (mb_chan_status_ack(mb_chan))
110*4882a593Smuzhiyun mbox_chan_txdone(mb_chan->chan, 0);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (mb_chan_status_avail(mb_chan))
113*4882a593Smuzhiyun mbox_chan_received_data(mb_chan->chan, mb_chan->rx_msg);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return IRQ_HANDLED;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
slimpro_mbox_send_data(struct mbox_chan * chan,void * msg)118*4882a593Smuzhiyun static int slimpro_mbox_send_data(struct mbox_chan *chan, void *msg)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun struct slimpro_mbox_chan *mb_chan = chan->con_priv;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun mb_chan_send_msg(mb_chan, msg);
123*4882a593Smuzhiyun return 0;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
slimpro_mbox_startup(struct mbox_chan * chan)126*4882a593Smuzhiyun static int slimpro_mbox_startup(struct mbox_chan *chan)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun struct slimpro_mbox_chan *mb_chan = chan->con_priv;
129*4882a593Smuzhiyun int rc;
130*4882a593Smuzhiyun u32 val;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun rc = devm_request_irq(mb_chan->dev, mb_chan->irq, slimpro_mbox_irq, 0,
133*4882a593Smuzhiyun MBOX_CON_NAME, mb_chan);
134*4882a593Smuzhiyun if (unlikely(rc)) {
135*4882a593Smuzhiyun dev_err(mb_chan->dev, "failed to register mailbox interrupt %d\n",
136*4882a593Smuzhiyun mb_chan->irq);
137*4882a593Smuzhiyun return rc;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Enable HW interrupt */
141*4882a593Smuzhiyun writel(MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK,
142*4882a593Smuzhiyun mb_chan->reg + REG_DB_STAT);
143*4882a593Smuzhiyun /* Unmask doorbell status interrupt */
144*4882a593Smuzhiyun val = readl(mb_chan->reg + REG_DB_STATMASK);
145*4882a593Smuzhiyun val &= ~(MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK);
146*4882a593Smuzhiyun writel(val, mb_chan->reg + REG_DB_STATMASK);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
slimpro_mbox_shutdown(struct mbox_chan * chan)151*4882a593Smuzhiyun static void slimpro_mbox_shutdown(struct mbox_chan *chan)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun struct slimpro_mbox_chan *mb_chan = chan->con_priv;
154*4882a593Smuzhiyun u32 val;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* Mask doorbell status interrupt */
157*4882a593Smuzhiyun val = readl(mb_chan->reg + REG_DB_STATMASK);
158*4882a593Smuzhiyun val |= (MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK);
159*4882a593Smuzhiyun writel(val, mb_chan->reg + REG_DB_STATMASK);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun devm_free_irq(mb_chan->dev, mb_chan->irq, mb_chan);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static const struct mbox_chan_ops slimpro_mbox_ops = {
165*4882a593Smuzhiyun .send_data = slimpro_mbox_send_data,
166*4882a593Smuzhiyun .startup = slimpro_mbox_startup,
167*4882a593Smuzhiyun .shutdown = slimpro_mbox_shutdown,
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
slimpro_mbox_probe(struct platform_device * pdev)170*4882a593Smuzhiyun static int slimpro_mbox_probe(struct platform_device *pdev)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun struct slimpro_mbox *ctx;
173*4882a593Smuzhiyun struct resource *regs;
174*4882a593Smuzhiyun void __iomem *mb_base;
175*4882a593Smuzhiyun int rc;
176*4882a593Smuzhiyun int i;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ctx = devm_kzalloc(&pdev->dev, sizeof(struct slimpro_mbox), GFP_KERNEL);
179*4882a593Smuzhiyun if (!ctx)
180*4882a593Smuzhiyun return -ENOMEM;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun platform_set_drvdata(pdev, ctx);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
185*4882a593Smuzhiyun mb_base = devm_ioremap_resource(&pdev->dev, regs);
186*4882a593Smuzhiyun if (IS_ERR(mb_base))
187*4882a593Smuzhiyun return PTR_ERR(mb_base);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* Setup mailbox links */
190*4882a593Smuzhiyun for (i = 0; i < MBOX_CNT; i++) {
191*4882a593Smuzhiyun ctx->mc[i].irq = platform_get_irq(pdev, i);
192*4882a593Smuzhiyun if (ctx->mc[i].irq < 0) {
193*4882a593Smuzhiyun if (i == 0) {
194*4882a593Smuzhiyun dev_err(&pdev->dev, "no available IRQ\n");
195*4882a593Smuzhiyun return -EINVAL;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun dev_info(&pdev->dev, "no IRQ for channel %d\n", i);
198*4882a593Smuzhiyun break;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun ctx->mc[i].dev = &pdev->dev;
202*4882a593Smuzhiyun ctx->mc[i].reg = mb_base + i * MBOX_REG_SET_OFFSET;
203*4882a593Smuzhiyun ctx->mc[i].chan = &ctx->chans[i];
204*4882a593Smuzhiyun ctx->chans[i].con_priv = &ctx->mc[i];
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* Setup mailbox controller */
208*4882a593Smuzhiyun ctx->mb_ctrl.dev = &pdev->dev;
209*4882a593Smuzhiyun ctx->mb_ctrl.chans = ctx->chans;
210*4882a593Smuzhiyun ctx->mb_ctrl.txdone_irq = true;
211*4882a593Smuzhiyun ctx->mb_ctrl.ops = &slimpro_mbox_ops;
212*4882a593Smuzhiyun ctx->mb_ctrl.num_chans = i;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun rc = devm_mbox_controller_register(&pdev->dev, &ctx->mb_ctrl);
215*4882a593Smuzhiyun if (rc) {
216*4882a593Smuzhiyun dev_err(&pdev->dev,
217*4882a593Smuzhiyun "APM X-Gene SLIMpro MailBox register failed:%d\n", rc);
218*4882a593Smuzhiyun return rc;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun dev_info(&pdev->dev, "APM X-Gene SLIMpro MailBox registered\n");
222*4882a593Smuzhiyun return 0;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static const struct of_device_id slimpro_of_match[] = {
226*4882a593Smuzhiyun {.compatible = "apm,xgene-slimpro-mbox" },
227*4882a593Smuzhiyun { },
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, slimpro_of_match);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun #ifdef CONFIG_ACPI
232*4882a593Smuzhiyun static const struct acpi_device_id slimpro_acpi_ids[] = {
233*4882a593Smuzhiyun {"APMC0D01", 0},
234*4882a593Smuzhiyun {}
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, slimpro_acpi_ids);
237*4882a593Smuzhiyun #endif
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static struct platform_driver slimpro_mbox_driver = {
240*4882a593Smuzhiyun .probe = slimpro_mbox_probe,
241*4882a593Smuzhiyun .driver = {
242*4882a593Smuzhiyun .name = "xgene-slimpro-mbox",
243*4882a593Smuzhiyun .of_match_table = of_match_ptr(slimpro_of_match),
244*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(slimpro_acpi_ids)
245*4882a593Smuzhiyun },
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
slimpro_mbox_init(void)248*4882a593Smuzhiyun static int __init slimpro_mbox_init(void)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun return platform_driver_register(&slimpro_mbox_driver);
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
slimpro_mbox_exit(void)253*4882a593Smuzhiyun static void __exit slimpro_mbox_exit(void)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun platform_driver_unregister(&slimpro_mbox_driver);
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun subsys_initcall(slimpro_mbox_init);
259*4882a593Smuzhiyun module_exit(slimpro_mbox_exit);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun MODULE_DESCRIPTION("APM X-Gene SLIMpro Mailbox Driver");
262*4882a593Smuzhiyun MODULE_LICENSE("GPL");
263