1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Hisilicon's Hi6220 mailbox driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015 Hisilicon Limited.
6*4882a593Smuzhiyun * Copyright (c) 2015 Linaro Limited.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Leo Yan <leo.yan@linaro.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/kfifo.h>
16*4882a593Smuzhiyun #include <linux/mailbox_controller.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define MBOX_CHAN_MAX 32
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define MBOX_TX 0x1
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Mailbox message length: 8 words */
26*4882a593Smuzhiyun #define MBOX_MSG_LEN 8
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Mailbox Registers */
29*4882a593Smuzhiyun #define MBOX_OFF(m) (0x40 * (m))
30*4882a593Smuzhiyun #define MBOX_MODE_REG(m) (MBOX_OFF(m) + 0x0)
31*4882a593Smuzhiyun #define MBOX_DATA_REG(m) (MBOX_OFF(m) + 0x4)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define MBOX_STATE_MASK (0xF << 4)
34*4882a593Smuzhiyun #define MBOX_STATE_IDLE (0x1 << 4)
35*4882a593Smuzhiyun #define MBOX_STATE_TX (0x2 << 4)
36*4882a593Smuzhiyun #define MBOX_STATE_RX (0x4 << 4)
37*4882a593Smuzhiyun #define MBOX_STATE_ACK (0x8 << 4)
38*4882a593Smuzhiyun #define MBOX_ACK_CONFIG_MASK (0x1 << 0)
39*4882a593Smuzhiyun #define MBOX_ACK_AUTOMATIC (0x1 << 0)
40*4882a593Smuzhiyun #define MBOX_ACK_IRQ (0x0 << 0)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* IPC registers */
43*4882a593Smuzhiyun #define ACK_INT_RAW_REG(i) ((i) + 0x400)
44*4882a593Smuzhiyun #define ACK_INT_MSK_REG(i) ((i) + 0x404)
45*4882a593Smuzhiyun #define ACK_INT_STAT_REG(i) ((i) + 0x408)
46*4882a593Smuzhiyun #define ACK_INT_CLR_REG(i) ((i) + 0x40c)
47*4882a593Smuzhiyun #define ACK_INT_ENA_REG(i) ((i) + 0x500)
48*4882a593Smuzhiyun #define ACK_INT_DIS_REG(i) ((i) + 0x504)
49*4882a593Smuzhiyun #define DST_INT_RAW_REG(i) ((i) + 0x420)
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun struct hi6220_mbox_chan {
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * Description for channel's hardware info:
56*4882a593Smuzhiyun * - direction: tx or rx
57*4882a593Smuzhiyun * - dst irq: peer core's irq number
58*4882a593Smuzhiyun * - ack irq: local irq number
59*4882a593Smuzhiyun * - slot number
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun unsigned int dir, dst_irq, ack_irq;
62*4882a593Smuzhiyun unsigned int slot;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct hi6220_mbox *parent;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct hi6220_mbox {
68*4882a593Smuzhiyun struct device *dev;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun int irq;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* flag of enabling tx's irq mode */
73*4882a593Smuzhiyun bool tx_irq_mode;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* region for ipc event */
76*4882a593Smuzhiyun void __iomem *ipc;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* region for mailbox */
79*4882a593Smuzhiyun void __iomem *base;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun unsigned int chan_num;
82*4882a593Smuzhiyun struct hi6220_mbox_chan *mchan;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun void *irq_map_chan[MBOX_CHAN_MAX];
85*4882a593Smuzhiyun struct mbox_chan *chan;
86*4882a593Smuzhiyun struct mbox_controller controller;
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
mbox_set_state(struct hi6220_mbox * mbox,unsigned int slot,u32 val)89*4882a593Smuzhiyun static void mbox_set_state(struct hi6220_mbox *mbox,
90*4882a593Smuzhiyun unsigned int slot, u32 val)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun u32 status;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun status = readl(mbox->base + MBOX_MODE_REG(slot));
95*4882a593Smuzhiyun status = (status & ~MBOX_STATE_MASK) | val;
96*4882a593Smuzhiyun writel(status, mbox->base + MBOX_MODE_REG(slot));
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
mbox_set_mode(struct hi6220_mbox * mbox,unsigned int slot,u32 val)99*4882a593Smuzhiyun static void mbox_set_mode(struct hi6220_mbox *mbox,
100*4882a593Smuzhiyun unsigned int slot, u32 val)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun u32 mode;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun mode = readl(mbox->base + MBOX_MODE_REG(slot));
105*4882a593Smuzhiyun mode = (mode & ~MBOX_ACK_CONFIG_MASK) | val;
106*4882a593Smuzhiyun writel(mode, mbox->base + MBOX_MODE_REG(slot));
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
hi6220_mbox_last_tx_done(struct mbox_chan * chan)109*4882a593Smuzhiyun static bool hi6220_mbox_last_tx_done(struct mbox_chan *chan)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct hi6220_mbox_chan *mchan = chan->con_priv;
112*4882a593Smuzhiyun struct hi6220_mbox *mbox = mchan->parent;
113*4882a593Smuzhiyun u32 state;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* Only set idle state for polling mode */
116*4882a593Smuzhiyun BUG_ON(mbox->tx_irq_mode);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun state = readl(mbox->base + MBOX_MODE_REG(mchan->slot));
119*4882a593Smuzhiyun return ((state & MBOX_STATE_MASK) == MBOX_STATE_IDLE);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
hi6220_mbox_send_data(struct mbox_chan * chan,void * msg)122*4882a593Smuzhiyun static int hi6220_mbox_send_data(struct mbox_chan *chan, void *msg)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct hi6220_mbox_chan *mchan = chan->con_priv;
125*4882a593Smuzhiyun struct hi6220_mbox *mbox = mchan->parent;
126*4882a593Smuzhiyun unsigned int slot = mchan->slot;
127*4882a593Smuzhiyun u32 *buf = msg;
128*4882a593Smuzhiyun int i;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* indicate as a TX channel */
131*4882a593Smuzhiyun mchan->dir = MBOX_TX;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun mbox_set_state(mbox, slot, MBOX_STATE_TX);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun if (mbox->tx_irq_mode)
136*4882a593Smuzhiyun mbox_set_mode(mbox, slot, MBOX_ACK_IRQ);
137*4882a593Smuzhiyun else
138*4882a593Smuzhiyun mbox_set_mode(mbox, slot, MBOX_ACK_AUTOMATIC);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun for (i = 0; i < MBOX_MSG_LEN; i++)
141*4882a593Smuzhiyun writel(buf[i], mbox->base + MBOX_DATA_REG(slot) + i * 4);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* trigger remote request */
144*4882a593Smuzhiyun writel(BIT(mchan->dst_irq), DST_INT_RAW_REG(mbox->ipc));
145*4882a593Smuzhiyun return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
hi6220_mbox_interrupt(int irq,void * p)148*4882a593Smuzhiyun static irqreturn_t hi6220_mbox_interrupt(int irq, void *p)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct hi6220_mbox *mbox = p;
151*4882a593Smuzhiyun struct hi6220_mbox_chan *mchan;
152*4882a593Smuzhiyun struct mbox_chan *chan;
153*4882a593Smuzhiyun unsigned int state, intr_bit, i;
154*4882a593Smuzhiyun u32 msg[MBOX_MSG_LEN];
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun state = readl(ACK_INT_STAT_REG(mbox->ipc));
157*4882a593Smuzhiyun if (!state) {
158*4882a593Smuzhiyun dev_warn(mbox->dev, "%s: spurious interrupt\n",
159*4882a593Smuzhiyun __func__);
160*4882a593Smuzhiyun return IRQ_HANDLED;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun while (state) {
164*4882a593Smuzhiyun intr_bit = __ffs(state);
165*4882a593Smuzhiyun state &= (state - 1);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun chan = mbox->irq_map_chan[intr_bit];
168*4882a593Smuzhiyun if (!chan) {
169*4882a593Smuzhiyun dev_warn(mbox->dev, "%s: unexpected irq vector %d\n",
170*4882a593Smuzhiyun __func__, intr_bit);
171*4882a593Smuzhiyun continue;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun mchan = chan->con_priv;
175*4882a593Smuzhiyun if (mchan->dir == MBOX_TX)
176*4882a593Smuzhiyun mbox_chan_txdone(chan, 0);
177*4882a593Smuzhiyun else {
178*4882a593Smuzhiyun for (i = 0; i < MBOX_MSG_LEN; i++)
179*4882a593Smuzhiyun msg[i] = readl(mbox->base +
180*4882a593Smuzhiyun MBOX_DATA_REG(mchan->slot) + i * 4);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun mbox_chan_received_data(chan, (void *)msg);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* clear IRQ source */
186*4882a593Smuzhiyun writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc));
187*4882a593Smuzhiyun mbox_set_state(mbox, mchan->slot, MBOX_STATE_IDLE);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return IRQ_HANDLED;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
hi6220_mbox_startup(struct mbox_chan * chan)193*4882a593Smuzhiyun static int hi6220_mbox_startup(struct mbox_chan *chan)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun struct hi6220_mbox_chan *mchan = chan->con_priv;
196*4882a593Smuzhiyun struct hi6220_mbox *mbox = mchan->parent;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun mchan->dir = 0;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun /* enable interrupt */
201*4882a593Smuzhiyun writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc));
202*4882a593Smuzhiyun return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
hi6220_mbox_shutdown(struct mbox_chan * chan)205*4882a593Smuzhiyun static void hi6220_mbox_shutdown(struct mbox_chan *chan)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun struct hi6220_mbox_chan *mchan = chan->con_priv;
208*4882a593Smuzhiyun struct hi6220_mbox *mbox = mchan->parent;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /* disable interrupt */
211*4882a593Smuzhiyun writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc));
212*4882a593Smuzhiyun mbox->irq_map_chan[mchan->ack_irq] = NULL;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun static const struct mbox_chan_ops hi6220_mbox_ops = {
216*4882a593Smuzhiyun .send_data = hi6220_mbox_send_data,
217*4882a593Smuzhiyun .startup = hi6220_mbox_startup,
218*4882a593Smuzhiyun .shutdown = hi6220_mbox_shutdown,
219*4882a593Smuzhiyun .last_tx_done = hi6220_mbox_last_tx_done,
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun
hi6220_mbox_xlate(struct mbox_controller * controller,const struct of_phandle_args * spec)222*4882a593Smuzhiyun static struct mbox_chan *hi6220_mbox_xlate(struct mbox_controller *controller,
223*4882a593Smuzhiyun const struct of_phandle_args *spec)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun struct hi6220_mbox *mbox = dev_get_drvdata(controller->dev);
226*4882a593Smuzhiyun struct hi6220_mbox_chan *mchan;
227*4882a593Smuzhiyun struct mbox_chan *chan;
228*4882a593Smuzhiyun unsigned int i = spec->args[0];
229*4882a593Smuzhiyun unsigned int dst_irq = spec->args[1];
230*4882a593Smuzhiyun unsigned int ack_irq = spec->args[2];
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /* Bounds checking */
233*4882a593Smuzhiyun if (i >= mbox->chan_num || dst_irq >= mbox->chan_num ||
234*4882a593Smuzhiyun ack_irq >= mbox->chan_num) {
235*4882a593Smuzhiyun dev_err(mbox->dev,
236*4882a593Smuzhiyun "Invalid channel idx %d dst_irq %d ack_irq %d\n",
237*4882a593Smuzhiyun i, dst_irq, ack_irq);
238*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /* Is requested channel free? */
242*4882a593Smuzhiyun chan = &mbox->chan[i];
243*4882a593Smuzhiyun if (mbox->irq_map_chan[ack_irq] == (void *)chan) {
244*4882a593Smuzhiyun dev_err(mbox->dev, "Channel in use\n");
245*4882a593Smuzhiyun return ERR_PTR(-EBUSY);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun mchan = chan->con_priv;
249*4882a593Smuzhiyun mchan->dst_irq = dst_irq;
250*4882a593Smuzhiyun mchan->ack_irq = ack_irq;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun mbox->irq_map_chan[ack_irq] = (void *)chan;
253*4882a593Smuzhiyun return chan;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun static const struct of_device_id hi6220_mbox_of_match[] = {
257*4882a593Smuzhiyun { .compatible = "hisilicon,hi6220-mbox", },
258*4882a593Smuzhiyun {},
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hi6220_mbox_of_match);
261*4882a593Smuzhiyun
hi6220_mbox_probe(struct platform_device * pdev)262*4882a593Smuzhiyun static int hi6220_mbox_probe(struct platform_device *pdev)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
265*4882a593Smuzhiyun struct device *dev = &pdev->dev;
266*4882a593Smuzhiyun struct hi6220_mbox *mbox;
267*4882a593Smuzhiyun struct resource *res;
268*4882a593Smuzhiyun int i, err;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
271*4882a593Smuzhiyun if (!mbox)
272*4882a593Smuzhiyun return -ENOMEM;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun mbox->dev = dev;
275*4882a593Smuzhiyun mbox->chan_num = MBOX_CHAN_MAX;
276*4882a593Smuzhiyun mbox->mchan = devm_kcalloc(dev,
277*4882a593Smuzhiyun mbox->chan_num, sizeof(*mbox->mchan), GFP_KERNEL);
278*4882a593Smuzhiyun if (!mbox->mchan)
279*4882a593Smuzhiyun return -ENOMEM;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun mbox->chan = devm_kcalloc(dev,
282*4882a593Smuzhiyun mbox->chan_num, sizeof(*mbox->chan), GFP_KERNEL);
283*4882a593Smuzhiyun if (!mbox->chan)
284*4882a593Smuzhiyun return -ENOMEM;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun mbox->irq = platform_get_irq(pdev, 0);
287*4882a593Smuzhiyun if (mbox->irq < 0)
288*4882a593Smuzhiyun return mbox->irq;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
291*4882a593Smuzhiyun mbox->ipc = devm_ioremap_resource(dev, res);
292*4882a593Smuzhiyun if (IS_ERR(mbox->ipc)) {
293*4882a593Smuzhiyun dev_err(dev, "ioremap ipc failed\n");
294*4882a593Smuzhiyun return PTR_ERR(mbox->ipc);
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
298*4882a593Smuzhiyun mbox->base = devm_ioremap_resource(dev, res);
299*4882a593Smuzhiyun if (IS_ERR(mbox->base)) {
300*4882a593Smuzhiyun dev_err(dev, "ioremap buffer failed\n");
301*4882a593Smuzhiyun return PTR_ERR(mbox->base);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun err = devm_request_irq(dev, mbox->irq, hi6220_mbox_interrupt, 0,
305*4882a593Smuzhiyun dev_name(dev), mbox);
306*4882a593Smuzhiyun if (err) {
307*4882a593Smuzhiyun dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n",
308*4882a593Smuzhiyun err);
309*4882a593Smuzhiyun return -ENODEV;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun mbox->controller.dev = dev;
313*4882a593Smuzhiyun mbox->controller.chans = &mbox->chan[0];
314*4882a593Smuzhiyun mbox->controller.num_chans = mbox->chan_num;
315*4882a593Smuzhiyun mbox->controller.ops = &hi6220_mbox_ops;
316*4882a593Smuzhiyun mbox->controller.of_xlate = hi6220_mbox_xlate;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun for (i = 0; i < mbox->chan_num; i++) {
319*4882a593Smuzhiyun mbox->chan[i].con_priv = &mbox->mchan[i];
320*4882a593Smuzhiyun mbox->irq_map_chan[i] = NULL;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun mbox->mchan[i].parent = mbox;
323*4882a593Smuzhiyun mbox->mchan[i].slot = i;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /* mask and clear all interrupt vectors */
327*4882a593Smuzhiyun writel(0x0, ACK_INT_MSK_REG(mbox->ipc));
328*4882a593Smuzhiyun writel(~0x0, ACK_INT_CLR_REG(mbox->ipc));
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /* use interrupt for tx's ack */
331*4882a593Smuzhiyun if (of_find_property(node, "hi6220,mbox-tx-noirq", NULL))
332*4882a593Smuzhiyun mbox->tx_irq_mode = false;
333*4882a593Smuzhiyun else
334*4882a593Smuzhiyun mbox->tx_irq_mode = true;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun if (mbox->tx_irq_mode)
337*4882a593Smuzhiyun mbox->controller.txdone_irq = true;
338*4882a593Smuzhiyun else {
339*4882a593Smuzhiyun mbox->controller.txdone_poll = true;
340*4882a593Smuzhiyun mbox->controller.txpoll_period = 5;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun err = devm_mbox_controller_register(dev, &mbox->controller);
344*4882a593Smuzhiyun if (err) {
345*4882a593Smuzhiyun dev_err(dev, "Failed to register mailbox %d\n", err);
346*4882a593Smuzhiyun return err;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun platform_set_drvdata(pdev, mbox);
350*4882a593Smuzhiyun dev_info(dev, "Mailbox enabled\n");
351*4882a593Smuzhiyun return 0;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun static struct platform_driver hi6220_mbox_driver = {
355*4882a593Smuzhiyun .driver = {
356*4882a593Smuzhiyun .name = "hi6220-mbox",
357*4882a593Smuzhiyun .of_match_table = hi6220_mbox_of_match,
358*4882a593Smuzhiyun },
359*4882a593Smuzhiyun .probe = hi6220_mbox_probe,
360*4882a593Smuzhiyun };
361*4882a593Smuzhiyun
hi6220_mbox_init(void)362*4882a593Smuzhiyun static int __init hi6220_mbox_init(void)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun return platform_driver_register(&hi6220_mbox_driver);
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun core_initcall(hi6220_mbox_init);
367*4882a593Smuzhiyun
hi6220_mbox_exit(void)368*4882a593Smuzhiyun static void __exit hi6220_mbox_exit(void)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun platform_driver_unregister(&hi6220_mbox_driver);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun module_exit(hi6220_mbox_exit);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
375*4882a593Smuzhiyun MODULE_DESCRIPTION("Hi6220 mailbox driver");
376*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
377