1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2017-2018 Hisilicon Limited.
3*4882a593Smuzhiyun // Copyright (c) 2017-2018 Linaro Limited.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/bitops.h>
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/device.h>
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/iopoll.h>
12*4882a593Smuzhiyun #include <linux/mailbox_controller.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "mailbox.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define MBOX_CHAN_MAX 32
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define MBOX_RX 0x0
22*4882a593Smuzhiyun #define MBOX_TX 0x1
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40))
25*4882a593Smuzhiyun #define MBOX_SRC_REG 0x00
26*4882a593Smuzhiyun #define MBOX_DST_REG 0x04
27*4882a593Smuzhiyun #define MBOX_DCLR_REG 0x08
28*4882a593Smuzhiyun #define MBOX_DSTAT_REG 0x0c
29*4882a593Smuzhiyun #define MBOX_MODE_REG 0x10
30*4882a593Smuzhiyun #define MBOX_IMASK_REG 0x14
31*4882a593Smuzhiyun #define MBOX_ICLR_REG 0x18
32*4882a593Smuzhiyun #define MBOX_SEND_REG 0x1c
33*4882a593Smuzhiyun #define MBOX_DATA_REG 0x20
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define MBOX_IPC_LOCK_REG 0xa00
36*4882a593Smuzhiyun #define MBOX_IPC_UNLOCK 0x1acce551
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define MBOX_AUTOMATIC_ACK 1
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define MBOX_STATE_IDLE BIT(4)
41*4882a593Smuzhiyun #define MBOX_STATE_READY BIT(5)
42*4882a593Smuzhiyun #define MBOX_STATE_ACK BIT(7)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define MBOX_MSG_LEN 8
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /**
47*4882a593Smuzhiyun * Hi3660 mailbox channel information
48*4882a593Smuzhiyun *
49*4882a593Smuzhiyun * A channel can be used for TX or RX, it can trigger remote
50*4882a593Smuzhiyun * processor interrupt to notify remote processor and can receive
51*4882a593Smuzhiyun * interrupt if has incoming message.
52*4882a593Smuzhiyun *
53*4882a593Smuzhiyun * @dst_irq: Interrupt vector for remote processor
54*4882a593Smuzhiyun * @ack_irq: Interrupt vector for local processor
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun struct hi3660_chan_info {
57*4882a593Smuzhiyun unsigned int dst_irq;
58*4882a593Smuzhiyun unsigned int ack_irq;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /**
62*4882a593Smuzhiyun * Hi3660 mailbox controller data
63*4882a593Smuzhiyun *
64*4882a593Smuzhiyun * Mailbox controller includes 32 channels and can allocate
65*4882a593Smuzhiyun * channel for message transferring.
66*4882a593Smuzhiyun *
67*4882a593Smuzhiyun * @dev: Device to which it is attached
68*4882a593Smuzhiyun * @base: Base address of the register mapping region
69*4882a593Smuzhiyun * @chan: Representation of channels in mailbox controller
70*4882a593Smuzhiyun * @mchan: Representation of channel info
71*4882a593Smuzhiyun * @controller: Representation of a communication channel controller
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun struct hi3660_mbox {
74*4882a593Smuzhiyun struct device *dev;
75*4882a593Smuzhiyun void __iomem *base;
76*4882a593Smuzhiyun struct mbox_chan chan[MBOX_CHAN_MAX];
77*4882a593Smuzhiyun struct hi3660_chan_info mchan[MBOX_CHAN_MAX];
78*4882a593Smuzhiyun struct mbox_controller controller;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
to_hi3660_mbox(struct mbox_controller * mbox)81*4882a593Smuzhiyun static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun return container_of(mbox, struct hi3660_mbox, controller);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
hi3660_mbox_check_state(struct mbox_chan * chan)86*4882a593Smuzhiyun static int hi3660_mbox_check_state(struct mbox_chan *chan)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun unsigned long ch = (unsigned long)chan->con_priv;
89*4882a593Smuzhiyun struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
90*4882a593Smuzhiyun struct hi3660_chan_info *mchan = &mbox->mchan[ch];
91*4882a593Smuzhiyun void __iomem *base = MBOX_BASE(mbox, ch);
92*4882a593Smuzhiyun unsigned long val;
93*4882a593Smuzhiyun unsigned int ret;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Mailbox is ready to use */
96*4882a593Smuzhiyun if (readl(base + MBOX_MODE_REG) & MBOX_STATE_READY)
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Wait for acknowledge from remote */
100*4882a593Smuzhiyun ret = readx_poll_timeout_atomic(readl, base + MBOX_MODE_REG,
101*4882a593Smuzhiyun val, (val & MBOX_STATE_ACK), 1000, 300000);
102*4882a593Smuzhiyun if (ret) {
103*4882a593Smuzhiyun dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__);
104*4882a593Smuzhiyun return ret;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* clear ack state, mailbox will get back to ready state */
108*4882a593Smuzhiyun writel(BIT(mchan->ack_irq), base + MBOX_ICLR_REG);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return 0;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
hi3660_mbox_unlock(struct mbox_chan * chan)113*4882a593Smuzhiyun static int hi3660_mbox_unlock(struct mbox_chan *chan)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
116*4882a593Smuzhiyun unsigned int val, retry = 3;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun do {
119*4882a593Smuzhiyun writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun val = readl(mbox->base + MBOX_IPC_LOCK_REG);
122*4882a593Smuzhiyun if (!val)
123*4882a593Smuzhiyun break;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun udelay(10);
126*4882a593Smuzhiyun } while (retry--);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (val)
129*4882a593Smuzhiyun dev_err(mbox->dev, "%s: failed to unlock mailbox\n", __func__);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return (!val) ? 0 : -ETIMEDOUT;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
hi3660_mbox_acquire_channel(struct mbox_chan * chan)134*4882a593Smuzhiyun static int hi3660_mbox_acquire_channel(struct mbox_chan *chan)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun unsigned long ch = (unsigned long)chan->con_priv;
137*4882a593Smuzhiyun struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
138*4882a593Smuzhiyun struct hi3660_chan_info *mchan = &mbox->mchan[ch];
139*4882a593Smuzhiyun void __iomem *base = MBOX_BASE(mbox, ch);
140*4882a593Smuzhiyun unsigned int val, retry;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun for (retry = 10; retry; retry--) {
143*4882a593Smuzhiyun /* Check if channel is in idle state */
144*4882a593Smuzhiyun if (readl(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) {
145*4882a593Smuzhiyun writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* Check ack bit has been set successfully */
148*4882a593Smuzhiyun val = readl(base + MBOX_SRC_REG);
149*4882a593Smuzhiyun if (val & BIT(mchan->ack_irq))
150*4882a593Smuzhiyun break;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (!retry)
155*4882a593Smuzhiyun dev_err(mbox->dev, "%s: failed to acquire channel\n", __func__);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun return retry ? 0 : -ETIMEDOUT;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
hi3660_mbox_startup(struct mbox_chan * chan)160*4882a593Smuzhiyun static int hi3660_mbox_startup(struct mbox_chan *chan)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun int ret;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun ret = hi3660_mbox_unlock(chan);
165*4882a593Smuzhiyun if (ret)
166*4882a593Smuzhiyun return ret;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun ret = hi3660_mbox_acquire_channel(chan);
169*4882a593Smuzhiyun if (ret)
170*4882a593Smuzhiyun return ret;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun return 0;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
hi3660_mbox_send_data(struct mbox_chan * chan,void * msg)175*4882a593Smuzhiyun static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun unsigned long ch = (unsigned long)chan->con_priv;
178*4882a593Smuzhiyun struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
179*4882a593Smuzhiyun struct hi3660_chan_info *mchan = &mbox->mchan[ch];
180*4882a593Smuzhiyun void __iomem *base = MBOX_BASE(mbox, ch);
181*4882a593Smuzhiyun u32 *buf = msg;
182*4882a593Smuzhiyun unsigned int i;
183*4882a593Smuzhiyun int ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun ret = hi3660_mbox_check_state(chan);
186*4882a593Smuzhiyun if (ret)
187*4882a593Smuzhiyun return ret;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* Clear mask for destination interrupt */
190*4882a593Smuzhiyun writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* Config destination for interrupt vector */
193*4882a593Smuzhiyun writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* Automatic acknowledge mode */
196*4882a593Smuzhiyun writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* Fill message data */
199*4882a593Smuzhiyun for (i = 0; i < MBOX_MSG_LEN; i++)
200*4882a593Smuzhiyun writel_relaxed(buf[i], base + MBOX_DATA_REG + i * 4);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /* Trigger data transferring */
203*4882a593Smuzhiyun writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG);
204*4882a593Smuzhiyun return 0;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static const struct mbox_chan_ops hi3660_mbox_ops = {
208*4882a593Smuzhiyun .startup = hi3660_mbox_startup,
209*4882a593Smuzhiyun .send_data = hi3660_mbox_send_data,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun
hi3660_mbox_xlate(struct mbox_controller * controller,const struct of_phandle_args * spec)212*4882a593Smuzhiyun static struct mbox_chan *hi3660_mbox_xlate(struct mbox_controller *controller,
213*4882a593Smuzhiyun const struct of_phandle_args *spec)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun struct hi3660_mbox *mbox = to_hi3660_mbox(controller);
216*4882a593Smuzhiyun struct hi3660_chan_info *mchan;
217*4882a593Smuzhiyun unsigned int ch = spec->args[0];
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun if (ch >= MBOX_CHAN_MAX) {
220*4882a593Smuzhiyun dev_err(mbox->dev, "Invalid channel idx %d\n", ch);
221*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun mchan = &mbox->mchan[ch];
225*4882a593Smuzhiyun mchan->dst_irq = spec->args[1];
226*4882a593Smuzhiyun mchan->ack_irq = spec->args[2];
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun return &mbox->chan[ch];
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static const struct of_device_id hi3660_mbox_of_match[] = {
232*4882a593Smuzhiyun { .compatible = "hisilicon,hi3660-mbox", },
233*4882a593Smuzhiyun {},
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hi3660_mbox_of_match);
237*4882a593Smuzhiyun
hi3660_mbox_probe(struct platform_device * pdev)238*4882a593Smuzhiyun static int hi3660_mbox_probe(struct platform_device *pdev)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun struct device *dev = &pdev->dev;
241*4882a593Smuzhiyun struct hi3660_mbox *mbox;
242*4882a593Smuzhiyun struct mbox_chan *chan;
243*4882a593Smuzhiyun struct resource *res;
244*4882a593Smuzhiyun unsigned long ch;
245*4882a593Smuzhiyun int err;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
248*4882a593Smuzhiyun if (!mbox)
249*4882a593Smuzhiyun return -ENOMEM;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
252*4882a593Smuzhiyun mbox->base = devm_ioremap_resource(dev, res);
253*4882a593Smuzhiyun if (IS_ERR(mbox->base))
254*4882a593Smuzhiyun return PTR_ERR(mbox->base);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun mbox->dev = dev;
257*4882a593Smuzhiyun mbox->controller.dev = dev;
258*4882a593Smuzhiyun mbox->controller.chans = mbox->chan;
259*4882a593Smuzhiyun mbox->controller.num_chans = MBOX_CHAN_MAX;
260*4882a593Smuzhiyun mbox->controller.ops = &hi3660_mbox_ops;
261*4882a593Smuzhiyun mbox->controller.of_xlate = hi3660_mbox_xlate;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /* Initialize mailbox channel data */
264*4882a593Smuzhiyun chan = mbox->chan;
265*4882a593Smuzhiyun for (ch = 0; ch < MBOX_CHAN_MAX; ch++)
266*4882a593Smuzhiyun chan[ch].con_priv = (void *)ch;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun err = devm_mbox_controller_register(dev, &mbox->controller);
269*4882a593Smuzhiyun if (err) {
270*4882a593Smuzhiyun dev_err(dev, "Failed to register mailbox %d\n", err);
271*4882a593Smuzhiyun return err;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun platform_set_drvdata(pdev, mbox);
275*4882a593Smuzhiyun dev_info(dev, "Mailbox enabled\n");
276*4882a593Smuzhiyun return 0;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun static struct platform_driver hi3660_mbox_driver = {
280*4882a593Smuzhiyun .probe = hi3660_mbox_probe,
281*4882a593Smuzhiyun .driver = {
282*4882a593Smuzhiyun .name = "hi3660-mbox",
283*4882a593Smuzhiyun .of_match_table = hi3660_mbox_of_match,
284*4882a593Smuzhiyun },
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun
hi3660_mbox_init(void)287*4882a593Smuzhiyun static int __init hi3660_mbox_init(void)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun return platform_driver_register(&hi3660_mbox_driver);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun core_initcall(hi3660_mbox_init);
292*4882a593Smuzhiyun
hi3660_mbox_exit(void)293*4882a593Smuzhiyun static void __exit hi3660_mbox_exit(void)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun platform_driver_unregister(&hi3660_mbox_driver);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun module_exit(hi3660_mbox_exit);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun MODULE_LICENSE("GPL");
300*4882a593Smuzhiyun MODULE_DESCRIPTION("Hisilicon Hi3660 Mailbox Controller");
301*4882a593Smuzhiyun MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
302