1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2010,2015 Broadcom
4*4882a593Smuzhiyun * Copyright (C) 2013-2014 Lubomir Rintel
5*4882a593Smuzhiyun * Copyright (C) 2013 Craig McGeachie
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Parts of the driver are based on:
8*4882a593Smuzhiyun * - arch/arm/mach-bcm2708/vcio.c file written by Gray Girling that was
9*4882a593Smuzhiyun * obtained from branch "rpi-3.6.y" of git://github.com/raspberrypi/
10*4882a593Smuzhiyun * linux.git
11*4882a593Smuzhiyun * - drivers/mailbox/bcm2835-ipc.c by Lubomir Rintel at
12*4882a593Smuzhiyun * https://github.com/hackerspace/rpi-linux/blob/lr-raspberry-pi/drivers/
13*4882a593Smuzhiyun * mailbox/bcm2835-ipc.c
14*4882a593Smuzhiyun * - documentation available on the following web site:
15*4882a593Smuzhiyun * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/device.h>
19*4882a593Smuzhiyun #include <linux/dma-mapping.h>
20*4882a593Smuzhiyun #include <linux/err.h>
21*4882a593Smuzhiyun #include <linux/interrupt.h>
22*4882a593Smuzhiyun #include <linux/irq.h>
23*4882a593Smuzhiyun #include <linux/kernel.h>
24*4882a593Smuzhiyun #include <linux/mailbox_controller.h>
25*4882a593Smuzhiyun #include <linux/module.h>
26*4882a593Smuzhiyun #include <linux/of_address.h>
27*4882a593Smuzhiyun #include <linux/of_irq.h>
28*4882a593Smuzhiyun #include <linux/platform_device.h>
29*4882a593Smuzhiyun #include <linux/spinlock.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Mailboxes */
32*4882a593Smuzhiyun #define ARM_0_MAIL0 0x00
33*4882a593Smuzhiyun #define ARM_0_MAIL1 0x20
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * Mailbox registers. We basically only support mailbox 0 & 1. We
37*4882a593Smuzhiyun * deliver to the VC in mailbox 1, it delivers to us in mailbox 0. See
38*4882a593Smuzhiyun * BCM2835-ARM-Peripherals.pdf section 1.3 for an explanation about
39*4882a593Smuzhiyun * the placement of memory barriers.
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun #define MAIL0_RD (ARM_0_MAIL0 + 0x00)
42*4882a593Smuzhiyun #define MAIL0_POL (ARM_0_MAIL0 + 0x10)
43*4882a593Smuzhiyun #define MAIL0_STA (ARM_0_MAIL0 + 0x18)
44*4882a593Smuzhiyun #define MAIL0_CNF (ARM_0_MAIL0 + 0x1C)
45*4882a593Smuzhiyun #define MAIL1_WRT (ARM_0_MAIL1 + 0x00)
46*4882a593Smuzhiyun #define MAIL1_STA (ARM_0_MAIL1 + 0x18)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Status register: FIFO state. */
49*4882a593Smuzhiyun #define ARM_MS_FULL BIT(31)
50*4882a593Smuzhiyun #define ARM_MS_EMPTY BIT(30)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Configuration register: Enable interrupts. */
53*4882a593Smuzhiyun #define ARM_MC_IHAVEDATAIRQEN BIT(0)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct bcm2835_mbox {
56*4882a593Smuzhiyun void __iomem *regs;
57*4882a593Smuzhiyun spinlock_t lock;
58*4882a593Smuzhiyun struct mbox_controller controller;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
bcm2835_link_mbox(struct mbox_chan * link)61*4882a593Smuzhiyun static struct bcm2835_mbox *bcm2835_link_mbox(struct mbox_chan *link)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun return container_of(link->mbox, struct bcm2835_mbox, controller);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
bcm2835_mbox_irq(int irq,void * dev_id)66*4882a593Smuzhiyun static irqreturn_t bcm2835_mbox_irq(int irq, void *dev_id)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct bcm2835_mbox *mbox = dev_id;
69*4882a593Smuzhiyun struct device *dev = mbox->controller.dev;
70*4882a593Smuzhiyun struct mbox_chan *link = &mbox->controller.chans[0];
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) {
73*4882a593Smuzhiyun u32 msg = readl(mbox->regs + MAIL0_RD);
74*4882a593Smuzhiyun dev_dbg(dev, "Reply 0x%08X\n", msg);
75*4882a593Smuzhiyun mbox_chan_received_data(link, &msg);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun return IRQ_HANDLED;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
bcm2835_send_data(struct mbox_chan * link,void * data)80*4882a593Smuzhiyun static int bcm2835_send_data(struct mbox_chan *link, void *data)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct bcm2835_mbox *mbox = bcm2835_link_mbox(link);
83*4882a593Smuzhiyun u32 msg = *(u32 *)data;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun spin_lock(&mbox->lock);
86*4882a593Smuzhiyun writel(msg, mbox->regs + MAIL1_WRT);
87*4882a593Smuzhiyun dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg);
88*4882a593Smuzhiyun spin_unlock(&mbox->lock);
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
bcm2835_startup(struct mbox_chan * link)92*4882a593Smuzhiyun static int bcm2835_startup(struct mbox_chan *link)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct bcm2835_mbox *mbox = bcm2835_link_mbox(link);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* Enable the interrupt on data reception */
97*4882a593Smuzhiyun writel(ARM_MC_IHAVEDATAIRQEN, mbox->regs + MAIL0_CNF);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
bcm2835_shutdown(struct mbox_chan * link)102*4882a593Smuzhiyun static void bcm2835_shutdown(struct mbox_chan *link)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct bcm2835_mbox *mbox = bcm2835_link_mbox(link);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun writel(0, mbox->regs + MAIL0_CNF);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
bcm2835_last_tx_done(struct mbox_chan * link)109*4882a593Smuzhiyun static bool bcm2835_last_tx_done(struct mbox_chan *link)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct bcm2835_mbox *mbox = bcm2835_link_mbox(link);
112*4882a593Smuzhiyun bool ret;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun spin_lock(&mbox->lock);
115*4882a593Smuzhiyun ret = !(readl(mbox->regs + MAIL1_STA) & ARM_MS_FULL);
116*4882a593Smuzhiyun spin_unlock(&mbox->lock);
117*4882a593Smuzhiyun return ret;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static const struct mbox_chan_ops bcm2835_mbox_chan_ops = {
121*4882a593Smuzhiyun .send_data = bcm2835_send_data,
122*4882a593Smuzhiyun .startup = bcm2835_startup,
123*4882a593Smuzhiyun .shutdown = bcm2835_shutdown,
124*4882a593Smuzhiyun .last_tx_done = bcm2835_last_tx_done
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
bcm2835_mbox_index_xlate(struct mbox_controller * mbox,const struct of_phandle_args * sp)127*4882a593Smuzhiyun static struct mbox_chan *bcm2835_mbox_index_xlate(struct mbox_controller *mbox,
128*4882a593Smuzhiyun const struct of_phandle_args *sp)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun if (sp->args_count != 0)
131*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return &mbox->chans[0];
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
bcm2835_mbox_probe(struct platform_device * pdev)136*4882a593Smuzhiyun static int bcm2835_mbox_probe(struct platform_device *pdev)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct device *dev = &pdev->dev;
139*4882a593Smuzhiyun int ret = 0;
140*4882a593Smuzhiyun struct resource *iomem;
141*4882a593Smuzhiyun struct bcm2835_mbox *mbox;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
144*4882a593Smuzhiyun if (mbox == NULL)
145*4882a593Smuzhiyun return -ENOMEM;
146*4882a593Smuzhiyun spin_lock_init(&mbox->lock);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun ret = devm_request_irq(dev, irq_of_parse_and_map(dev->of_node, 0),
149*4882a593Smuzhiyun bcm2835_mbox_irq, 0, dev_name(dev), mbox);
150*4882a593Smuzhiyun if (ret) {
151*4882a593Smuzhiyun dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n",
152*4882a593Smuzhiyun ret);
153*4882a593Smuzhiyun return -ENODEV;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
157*4882a593Smuzhiyun mbox->regs = devm_ioremap_resource(&pdev->dev, iomem);
158*4882a593Smuzhiyun if (IS_ERR(mbox->regs)) {
159*4882a593Smuzhiyun ret = PTR_ERR(mbox->regs);
160*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to remap mailbox regs: %d\n", ret);
161*4882a593Smuzhiyun return ret;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun mbox->controller.txdone_poll = true;
165*4882a593Smuzhiyun mbox->controller.txpoll_period = 5;
166*4882a593Smuzhiyun mbox->controller.ops = &bcm2835_mbox_chan_ops;
167*4882a593Smuzhiyun mbox->controller.of_xlate = &bcm2835_mbox_index_xlate;
168*4882a593Smuzhiyun mbox->controller.dev = dev;
169*4882a593Smuzhiyun mbox->controller.num_chans = 1;
170*4882a593Smuzhiyun mbox->controller.chans = devm_kzalloc(dev,
171*4882a593Smuzhiyun sizeof(*mbox->controller.chans), GFP_KERNEL);
172*4882a593Smuzhiyun if (!mbox->controller.chans)
173*4882a593Smuzhiyun return -ENOMEM;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun ret = devm_mbox_controller_register(dev, &mbox->controller);
176*4882a593Smuzhiyun if (ret)
177*4882a593Smuzhiyun return ret;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun platform_set_drvdata(pdev, mbox);
180*4882a593Smuzhiyun dev_info(dev, "mailbox enabled\n");
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun return ret;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun static const struct of_device_id bcm2835_mbox_of_match[] = {
186*4882a593Smuzhiyun { .compatible = "brcm,bcm2835-mbox", },
187*4882a593Smuzhiyun {},
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bcm2835_mbox_of_match);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun static struct platform_driver bcm2835_mbox_driver = {
192*4882a593Smuzhiyun .driver = {
193*4882a593Smuzhiyun .name = "bcm2835-mbox",
194*4882a593Smuzhiyun .of_match_table = bcm2835_mbox_of_match,
195*4882a593Smuzhiyun },
196*4882a593Smuzhiyun .probe = bcm2835_mbox_probe,
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun module_platform_driver(bcm2835_mbox_driver);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
201*4882a593Smuzhiyun MODULE_DESCRIPTION("BCM2835 mailbox IPC driver");
202*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
203