1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * TI LP8501 9 channel LED Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/firmware.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/leds.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/mutex.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/platform_data/leds-lp55xx.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include "leds-lp55xx-common.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define LP8501_PROGRAM_LENGTH 32
24*4882a593Smuzhiyun #define LP8501_MAX_LEDS 9
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Registers */
27*4882a593Smuzhiyun #define LP8501_REG_ENABLE 0x00
28*4882a593Smuzhiyun #define LP8501_ENABLE BIT(6)
29*4882a593Smuzhiyun #define LP8501_EXEC_M 0x3F
30*4882a593Smuzhiyun #define LP8501_EXEC_ENG1_M 0x30
31*4882a593Smuzhiyun #define LP8501_EXEC_ENG2_M 0x0C
32*4882a593Smuzhiyun #define LP8501_EXEC_ENG3_M 0x03
33*4882a593Smuzhiyun #define LP8501_RUN_ENG1 0x20
34*4882a593Smuzhiyun #define LP8501_RUN_ENG2 0x08
35*4882a593Smuzhiyun #define LP8501_RUN_ENG3 0x02
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define LP8501_REG_OP_MODE 0x01
38*4882a593Smuzhiyun #define LP8501_MODE_ENG1_M 0x30
39*4882a593Smuzhiyun #define LP8501_MODE_ENG2_M 0x0C
40*4882a593Smuzhiyun #define LP8501_MODE_ENG3_M 0x03
41*4882a593Smuzhiyun #define LP8501_LOAD_ENG1 0x10
42*4882a593Smuzhiyun #define LP8501_LOAD_ENG2 0x04
43*4882a593Smuzhiyun #define LP8501_LOAD_ENG3 0x01
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define LP8501_REG_PWR_CONFIG 0x05
46*4882a593Smuzhiyun #define LP8501_PWR_CONFIG_M 0x03
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define LP8501_REG_LED_PWM_BASE 0x16
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define LP8501_REG_LED_CURRENT_BASE 0x26
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define LP8501_REG_CONFIG 0x36
53*4882a593Smuzhiyun #define LP8501_PWM_PSAVE BIT(7)
54*4882a593Smuzhiyun #define LP8501_AUTO_INC BIT(6)
55*4882a593Smuzhiyun #define LP8501_PWR_SAVE BIT(5)
56*4882a593Smuzhiyun #define LP8501_CP_AUTO 0x18
57*4882a593Smuzhiyun #define LP8501_INT_CLK BIT(0)
58*4882a593Smuzhiyun #define LP8501_DEFAULT_CFG \
59*4882a593Smuzhiyun (LP8501_PWM_PSAVE | LP8501_AUTO_INC | LP8501_PWR_SAVE | LP8501_CP_AUTO)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define LP8501_REG_RESET 0x3D
62*4882a593Smuzhiyun #define LP8501_RESET 0xFF
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define LP8501_REG_PROG_PAGE_SEL 0x4F
65*4882a593Smuzhiyun #define LP8501_PAGE_ENG1 0
66*4882a593Smuzhiyun #define LP8501_PAGE_ENG2 1
67*4882a593Smuzhiyun #define LP8501_PAGE_ENG3 2
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define LP8501_REG_PROG_MEM 0x50
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define LP8501_ENG1_IS_LOADING(mode) \
72*4882a593Smuzhiyun ((mode & LP8501_MODE_ENG1_M) == LP8501_LOAD_ENG1)
73*4882a593Smuzhiyun #define LP8501_ENG2_IS_LOADING(mode) \
74*4882a593Smuzhiyun ((mode & LP8501_MODE_ENG2_M) == LP8501_LOAD_ENG2)
75*4882a593Smuzhiyun #define LP8501_ENG3_IS_LOADING(mode) \
76*4882a593Smuzhiyun ((mode & LP8501_MODE_ENG3_M) == LP8501_LOAD_ENG3)
77*4882a593Smuzhiyun
lp8501_wait_opmode_done(void)78*4882a593Smuzhiyun static inline void lp8501_wait_opmode_done(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun usleep_range(1000, 2000);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
lp8501_set_led_current(struct lp55xx_led * led,u8 led_current)83*4882a593Smuzhiyun static void lp8501_set_led_current(struct lp55xx_led *led, u8 led_current)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun led->led_current = led_current;
86*4882a593Smuzhiyun lp55xx_write(led->chip, LP8501_REG_LED_CURRENT_BASE + led->chan_nr,
87*4882a593Smuzhiyun led_current);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
lp8501_post_init_device(struct lp55xx_chip * chip)90*4882a593Smuzhiyun static int lp8501_post_init_device(struct lp55xx_chip *chip)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun int ret;
93*4882a593Smuzhiyun u8 val = LP8501_DEFAULT_CFG;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun ret = lp55xx_write(chip, LP8501_REG_ENABLE, LP8501_ENABLE);
96*4882a593Smuzhiyun if (ret)
97*4882a593Smuzhiyun return ret;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Chip startup time is 500 us, 1 - 2 ms gives some margin */
100*4882a593Smuzhiyun usleep_range(1000, 2000);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (chip->pdata->clock_mode != LP55XX_CLOCK_EXT)
103*4882a593Smuzhiyun val |= LP8501_INT_CLK;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun ret = lp55xx_write(chip, LP8501_REG_CONFIG, val);
106*4882a593Smuzhiyun if (ret)
107*4882a593Smuzhiyun return ret;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Power selection for each output */
110*4882a593Smuzhiyun return lp55xx_update_bits(chip, LP8501_REG_PWR_CONFIG,
111*4882a593Smuzhiyun LP8501_PWR_CONFIG_M, chip->pdata->pwr_sel);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
lp8501_load_engine(struct lp55xx_chip * chip)114*4882a593Smuzhiyun static void lp8501_load_engine(struct lp55xx_chip *chip)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun enum lp55xx_engine_index idx = chip->engine_idx;
117*4882a593Smuzhiyun static const u8 mask[] = {
118*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP8501_MODE_ENG1_M,
119*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP8501_MODE_ENG2_M,
120*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP8501_MODE_ENG3_M,
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun static const u8 val[] = {
124*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP8501_LOAD_ENG1,
125*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP8501_LOAD_ENG2,
126*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP8501_LOAD_ENG3,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static const u8 page_sel[] = {
130*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP8501_PAGE_ENG1,
131*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP8501_PAGE_ENG2,
132*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP8501_PAGE_ENG3,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun lp55xx_update_bits(chip, LP8501_REG_OP_MODE, mask[idx], val[idx]);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun lp8501_wait_opmode_done();
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun lp55xx_write(chip, LP8501_REG_PROG_PAGE_SEL, page_sel[idx]);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
lp8501_stop_engine(struct lp55xx_chip * chip)142*4882a593Smuzhiyun static void lp8501_stop_engine(struct lp55xx_chip *chip)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun lp55xx_write(chip, LP8501_REG_OP_MODE, 0);
145*4882a593Smuzhiyun lp8501_wait_opmode_done();
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
lp8501_turn_off_channels(struct lp55xx_chip * chip)148*4882a593Smuzhiyun static void lp8501_turn_off_channels(struct lp55xx_chip *chip)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun int i;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun for (i = 0; i < LP8501_MAX_LEDS; i++)
153*4882a593Smuzhiyun lp55xx_write(chip, LP8501_REG_LED_PWM_BASE + i, 0);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
lp8501_run_engine(struct lp55xx_chip * chip,bool start)156*4882a593Smuzhiyun static void lp8501_run_engine(struct lp55xx_chip *chip, bool start)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun int ret;
159*4882a593Smuzhiyun u8 mode;
160*4882a593Smuzhiyun u8 exec;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* stop engine */
163*4882a593Smuzhiyun if (!start) {
164*4882a593Smuzhiyun lp8501_stop_engine(chip);
165*4882a593Smuzhiyun lp8501_turn_off_channels(chip);
166*4882a593Smuzhiyun return;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /*
170*4882a593Smuzhiyun * To run the engine,
171*4882a593Smuzhiyun * operation mode and enable register should updated at the same time
172*4882a593Smuzhiyun */
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun ret = lp55xx_read(chip, LP8501_REG_OP_MODE, &mode);
175*4882a593Smuzhiyun if (ret)
176*4882a593Smuzhiyun return;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ret = lp55xx_read(chip, LP8501_REG_ENABLE, &exec);
179*4882a593Smuzhiyun if (ret)
180*4882a593Smuzhiyun return;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* change operation mode to RUN only when each engine is loading */
183*4882a593Smuzhiyun if (LP8501_ENG1_IS_LOADING(mode)) {
184*4882a593Smuzhiyun mode = (mode & ~LP8501_MODE_ENG1_M) | LP8501_RUN_ENG1;
185*4882a593Smuzhiyun exec = (exec & ~LP8501_EXEC_ENG1_M) | LP8501_RUN_ENG1;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun if (LP8501_ENG2_IS_LOADING(mode)) {
189*4882a593Smuzhiyun mode = (mode & ~LP8501_MODE_ENG2_M) | LP8501_RUN_ENG2;
190*4882a593Smuzhiyun exec = (exec & ~LP8501_EXEC_ENG2_M) | LP8501_RUN_ENG2;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun if (LP8501_ENG3_IS_LOADING(mode)) {
194*4882a593Smuzhiyun mode = (mode & ~LP8501_MODE_ENG3_M) | LP8501_RUN_ENG3;
195*4882a593Smuzhiyun exec = (exec & ~LP8501_EXEC_ENG3_M) | LP8501_RUN_ENG3;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun lp55xx_write(chip, LP8501_REG_OP_MODE, mode);
199*4882a593Smuzhiyun lp8501_wait_opmode_done();
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun lp55xx_update_bits(chip, LP8501_REG_ENABLE, LP8501_EXEC_M, exec);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
lp8501_update_program_memory(struct lp55xx_chip * chip,const u8 * data,size_t size)204*4882a593Smuzhiyun static int lp8501_update_program_memory(struct lp55xx_chip *chip,
205*4882a593Smuzhiyun const u8 *data, size_t size)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun u8 pattern[LP8501_PROGRAM_LENGTH] = {0};
208*4882a593Smuzhiyun unsigned cmd;
209*4882a593Smuzhiyun char c[3];
210*4882a593Smuzhiyun int update_size;
211*4882a593Smuzhiyun int nrchars;
212*4882a593Smuzhiyun int offset = 0;
213*4882a593Smuzhiyun int ret;
214*4882a593Smuzhiyun int i;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun /* clear program memory before updating */
217*4882a593Smuzhiyun for (i = 0; i < LP8501_PROGRAM_LENGTH; i++)
218*4882a593Smuzhiyun lp55xx_write(chip, LP8501_REG_PROG_MEM + i, 0);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun i = 0;
221*4882a593Smuzhiyun while ((offset < size - 1) && (i < LP8501_PROGRAM_LENGTH)) {
222*4882a593Smuzhiyun /* separate sscanfs because length is working only for %s */
223*4882a593Smuzhiyun ret = sscanf(data + offset, "%2s%n ", c, &nrchars);
224*4882a593Smuzhiyun if (ret != 1)
225*4882a593Smuzhiyun goto err;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun ret = sscanf(c, "%2x", &cmd);
228*4882a593Smuzhiyun if (ret != 1)
229*4882a593Smuzhiyun goto err;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun pattern[i] = (u8)cmd;
232*4882a593Smuzhiyun offset += nrchars;
233*4882a593Smuzhiyun i++;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* Each instruction is 16bit long. Check that length is even */
237*4882a593Smuzhiyun if (i % 2)
238*4882a593Smuzhiyun goto err;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun update_size = i;
241*4882a593Smuzhiyun for (i = 0; i < update_size; i++)
242*4882a593Smuzhiyun lp55xx_write(chip, LP8501_REG_PROG_MEM + i, pattern[i]);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun return 0;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun err:
247*4882a593Smuzhiyun dev_err(&chip->cl->dev, "wrong pattern format\n");
248*4882a593Smuzhiyun return -EINVAL;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
lp8501_firmware_loaded(struct lp55xx_chip * chip)251*4882a593Smuzhiyun static void lp8501_firmware_loaded(struct lp55xx_chip *chip)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun const struct firmware *fw = chip->fw;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun if (fw->size > LP8501_PROGRAM_LENGTH) {
256*4882a593Smuzhiyun dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
257*4882a593Smuzhiyun fw->size);
258*4882a593Smuzhiyun return;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /*
262*4882a593Smuzhiyun * Program memory sequence
263*4882a593Smuzhiyun * 1) set engine mode to "LOAD"
264*4882a593Smuzhiyun * 2) write firmware data into program memory
265*4882a593Smuzhiyun */
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun lp8501_load_engine(chip);
268*4882a593Smuzhiyun lp8501_update_program_memory(chip, fw->data, fw->size);
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
lp8501_led_brightness(struct lp55xx_led * led)271*4882a593Smuzhiyun static int lp8501_led_brightness(struct lp55xx_led *led)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
274*4882a593Smuzhiyun int ret;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun mutex_lock(&chip->lock);
277*4882a593Smuzhiyun ret = lp55xx_write(chip, LP8501_REG_LED_PWM_BASE + led->chan_nr,
278*4882a593Smuzhiyun led->brightness);
279*4882a593Smuzhiyun mutex_unlock(&chip->lock);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun return ret;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /* Chip specific configurations */
285*4882a593Smuzhiyun static struct lp55xx_device_config lp8501_cfg = {
286*4882a593Smuzhiyun .reset = {
287*4882a593Smuzhiyun .addr = LP8501_REG_RESET,
288*4882a593Smuzhiyun .val = LP8501_RESET,
289*4882a593Smuzhiyun },
290*4882a593Smuzhiyun .enable = {
291*4882a593Smuzhiyun .addr = LP8501_REG_ENABLE,
292*4882a593Smuzhiyun .val = LP8501_ENABLE,
293*4882a593Smuzhiyun },
294*4882a593Smuzhiyun .max_channel = LP8501_MAX_LEDS,
295*4882a593Smuzhiyun .post_init_device = lp8501_post_init_device,
296*4882a593Smuzhiyun .brightness_fn = lp8501_led_brightness,
297*4882a593Smuzhiyun .set_led_current = lp8501_set_led_current,
298*4882a593Smuzhiyun .firmware_cb = lp8501_firmware_loaded,
299*4882a593Smuzhiyun .run_engine = lp8501_run_engine,
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun
lp8501_probe(struct i2c_client * client,const struct i2c_device_id * id)302*4882a593Smuzhiyun static int lp8501_probe(struct i2c_client *client,
303*4882a593Smuzhiyun const struct i2c_device_id *id)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun int ret;
306*4882a593Smuzhiyun struct lp55xx_chip *chip;
307*4882a593Smuzhiyun struct lp55xx_led *led;
308*4882a593Smuzhiyun struct lp55xx_platform_data *pdata = dev_get_platdata(&client->dev);
309*4882a593Smuzhiyun struct device_node *np = dev_of_node(&client->dev);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
312*4882a593Smuzhiyun if (!chip)
313*4882a593Smuzhiyun return -ENOMEM;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun chip->cfg = &lp8501_cfg;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if (!pdata) {
318*4882a593Smuzhiyun if (np) {
319*4882a593Smuzhiyun pdata = lp55xx_of_populate_pdata(&client->dev, np,
320*4882a593Smuzhiyun chip);
321*4882a593Smuzhiyun if (IS_ERR(pdata))
322*4882a593Smuzhiyun return PTR_ERR(pdata);
323*4882a593Smuzhiyun } else {
324*4882a593Smuzhiyun dev_err(&client->dev, "no platform data\n");
325*4882a593Smuzhiyun return -EINVAL;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun led = devm_kcalloc(&client->dev,
330*4882a593Smuzhiyun pdata->num_channels, sizeof(*led), GFP_KERNEL);
331*4882a593Smuzhiyun if (!led)
332*4882a593Smuzhiyun return -ENOMEM;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun chip->cl = client;
335*4882a593Smuzhiyun chip->pdata = pdata;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun mutex_init(&chip->lock);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun i2c_set_clientdata(client, led);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ret = lp55xx_init_device(chip);
342*4882a593Smuzhiyun if (ret)
343*4882a593Smuzhiyun goto err_init;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun dev_info(&client->dev, "%s Programmable led chip found\n", id->name);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun ret = lp55xx_register_leds(led, chip);
348*4882a593Smuzhiyun if (ret)
349*4882a593Smuzhiyun goto err_out;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun ret = lp55xx_register_sysfs(chip);
352*4882a593Smuzhiyun if (ret) {
353*4882a593Smuzhiyun dev_err(&client->dev, "registering sysfs failed\n");
354*4882a593Smuzhiyun goto err_out;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun return 0;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun err_out:
360*4882a593Smuzhiyun lp55xx_deinit_device(chip);
361*4882a593Smuzhiyun err_init:
362*4882a593Smuzhiyun return ret;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
lp8501_remove(struct i2c_client * client)365*4882a593Smuzhiyun static int lp8501_remove(struct i2c_client *client)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(client);
368*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun lp8501_stop_engine(chip);
371*4882a593Smuzhiyun lp55xx_unregister_sysfs(chip);
372*4882a593Smuzhiyun lp55xx_deinit_device(chip);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun return 0;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun static const struct i2c_device_id lp8501_id[] = {
378*4882a593Smuzhiyun { "lp8501", 0 },
379*4882a593Smuzhiyun { }
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, lp8501_id);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun #ifdef CONFIG_OF
384*4882a593Smuzhiyun static const struct of_device_id of_lp8501_leds_match[] = {
385*4882a593Smuzhiyun { .compatible = "ti,lp8501", },
386*4882a593Smuzhiyun {},
387*4882a593Smuzhiyun };
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_lp8501_leds_match);
390*4882a593Smuzhiyun #endif
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun static struct i2c_driver lp8501_driver = {
393*4882a593Smuzhiyun .driver = {
394*4882a593Smuzhiyun .name = "lp8501",
395*4882a593Smuzhiyun .of_match_table = of_match_ptr(of_lp8501_leds_match),
396*4882a593Smuzhiyun },
397*4882a593Smuzhiyun .probe = lp8501_probe,
398*4882a593Smuzhiyun .remove = lp8501_remove,
399*4882a593Smuzhiyun .id_table = lp8501_id,
400*4882a593Smuzhiyun };
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun module_i2c_driver(lp8501_driver);
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun MODULE_DESCRIPTION("Texas Instruments LP8501 LED driver");
405*4882a593Smuzhiyun MODULE_AUTHOR("Milo Kim");
406*4882a593Smuzhiyun MODULE_LICENSE("GPL");
407