1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * LP5562 LED driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/firmware.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/leds.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/mutex.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/platform_data/leds-lp55xx.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "leds-lp55xx-common.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define LP5562_PROGRAM_LENGTH 32
23*4882a593Smuzhiyun #define LP5562_MAX_LEDS 4
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* ENABLE Register 00h */
26*4882a593Smuzhiyun #define LP5562_REG_ENABLE 0x00
27*4882a593Smuzhiyun #define LP5562_EXEC_ENG1_M 0x30
28*4882a593Smuzhiyun #define LP5562_EXEC_ENG2_M 0x0C
29*4882a593Smuzhiyun #define LP5562_EXEC_ENG3_M 0x03
30*4882a593Smuzhiyun #define LP5562_EXEC_M 0x3F
31*4882a593Smuzhiyun #define LP5562_MASTER_ENABLE 0x40 /* Chip master enable */
32*4882a593Smuzhiyun #define LP5562_LOGARITHMIC_PWM 0x80 /* Logarithmic PWM adjustment */
33*4882a593Smuzhiyun #define LP5562_EXEC_RUN 0x2A
34*4882a593Smuzhiyun #define LP5562_ENABLE_DEFAULT \
35*4882a593Smuzhiyun (LP5562_MASTER_ENABLE | LP5562_LOGARITHMIC_PWM)
36*4882a593Smuzhiyun #define LP5562_ENABLE_RUN_PROGRAM \
37*4882a593Smuzhiyun (LP5562_ENABLE_DEFAULT | LP5562_EXEC_RUN)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* OPMODE Register 01h */
40*4882a593Smuzhiyun #define LP5562_REG_OP_MODE 0x01
41*4882a593Smuzhiyun #define LP5562_MODE_ENG1_M 0x30
42*4882a593Smuzhiyun #define LP5562_MODE_ENG2_M 0x0C
43*4882a593Smuzhiyun #define LP5562_MODE_ENG3_M 0x03
44*4882a593Smuzhiyun #define LP5562_LOAD_ENG1 0x10
45*4882a593Smuzhiyun #define LP5562_LOAD_ENG2 0x04
46*4882a593Smuzhiyun #define LP5562_LOAD_ENG3 0x01
47*4882a593Smuzhiyun #define LP5562_RUN_ENG1 0x20
48*4882a593Smuzhiyun #define LP5562_RUN_ENG2 0x08
49*4882a593Smuzhiyun #define LP5562_RUN_ENG3 0x02
50*4882a593Smuzhiyun #define LP5562_ENG1_IS_LOADING(mode) \
51*4882a593Smuzhiyun ((mode & LP5562_MODE_ENG1_M) == LP5562_LOAD_ENG1)
52*4882a593Smuzhiyun #define LP5562_ENG2_IS_LOADING(mode) \
53*4882a593Smuzhiyun ((mode & LP5562_MODE_ENG2_M) == LP5562_LOAD_ENG2)
54*4882a593Smuzhiyun #define LP5562_ENG3_IS_LOADING(mode) \
55*4882a593Smuzhiyun ((mode & LP5562_MODE_ENG3_M) == LP5562_LOAD_ENG3)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* BRIGHTNESS Registers */
58*4882a593Smuzhiyun #define LP5562_REG_R_PWM 0x04
59*4882a593Smuzhiyun #define LP5562_REG_G_PWM 0x03
60*4882a593Smuzhiyun #define LP5562_REG_B_PWM 0x02
61*4882a593Smuzhiyun #define LP5562_REG_W_PWM 0x0E
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* CURRENT Registers */
64*4882a593Smuzhiyun #define LP5562_REG_R_CURRENT 0x07
65*4882a593Smuzhiyun #define LP5562_REG_G_CURRENT 0x06
66*4882a593Smuzhiyun #define LP5562_REG_B_CURRENT 0x05
67*4882a593Smuzhiyun #define LP5562_REG_W_CURRENT 0x0F
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* CONFIG Register 08h */
70*4882a593Smuzhiyun #define LP5562_REG_CONFIG 0x08
71*4882a593Smuzhiyun #define LP5562_PWM_HF 0x40
72*4882a593Smuzhiyun #define LP5562_PWRSAVE_EN 0x20
73*4882a593Smuzhiyun #define LP5562_CLK_INT 0x01 /* Internal clock */
74*4882a593Smuzhiyun #define LP5562_DEFAULT_CFG (LP5562_PWM_HF | LP5562_PWRSAVE_EN)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* RESET Register 0Dh */
77*4882a593Smuzhiyun #define LP5562_REG_RESET 0x0D
78*4882a593Smuzhiyun #define LP5562_RESET 0xFF
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* PROGRAM ENGINE Registers */
81*4882a593Smuzhiyun #define LP5562_REG_PROG_MEM_ENG1 0x10
82*4882a593Smuzhiyun #define LP5562_REG_PROG_MEM_ENG2 0x30
83*4882a593Smuzhiyun #define LP5562_REG_PROG_MEM_ENG3 0x50
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* LEDMAP Register 70h */
86*4882a593Smuzhiyun #define LP5562_REG_ENG_SEL 0x70
87*4882a593Smuzhiyun #define LP5562_ENG_SEL_PWM 0
88*4882a593Smuzhiyun #define LP5562_ENG_FOR_RGB_M 0x3F
89*4882a593Smuzhiyun #define LP5562_ENG_SEL_RGB 0x1B /* R:ENG1, G:ENG2, B:ENG3 */
90*4882a593Smuzhiyun #define LP5562_ENG_FOR_W_M 0xC0
91*4882a593Smuzhiyun #define LP5562_ENG1_FOR_W 0x40 /* W:ENG1 */
92*4882a593Smuzhiyun #define LP5562_ENG2_FOR_W 0x80 /* W:ENG2 */
93*4882a593Smuzhiyun #define LP5562_ENG3_FOR_W 0xC0 /* W:ENG3 */
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Program Commands */
96*4882a593Smuzhiyun #define LP5562_CMD_DISABLE 0x00
97*4882a593Smuzhiyun #define LP5562_CMD_LOAD 0x15
98*4882a593Smuzhiyun #define LP5562_CMD_RUN 0x2A
99*4882a593Smuzhiyun #define LP5562_CMD_DIRECT 0x3F
100*4882a593Smuzhiyun #define LP5562_PATTERN_OFF 0
101*4882a593Smuzhiyun
lp5562_wait_opmode_done(void)102*4882a593Smuzhiyun static inline void lp5562_wait_opmode_done(void)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun /* operation mode change needs to be longer than 153 us */
105*4882a593Smuzhiyun usleep_range(200, 300);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
lp5562_wait_enable_done(void)108*4882a593Smuzhiyun static inline void lp5562_wait_enable_done(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun /* it takes more 488 us to update ENABLE register */
111*4882a593Smuzhiyun usleep_range(500, 600);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
lp5562_set_led_current(struct lp55xx_led * led,u8 led_current)114*4882a593Smuzhiyun static void lp5562_set_led_current(struct lp55xx_led *led, u8 led_current)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun static const u8 addr[] = {
117*4882a593Smuzhiyun LP5562_REG_R_CURRENT,
118*4882a593Smuzhiyun LP5562_REG_G_CURRENT,
119*4882a593Smuzhiyun LP5562_REG_B_CURRENT,
120*4882a593Smuzhiyun LP5562_REG_W_CURRENT,
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun led->led_current = led_current;
124*4882a593Smuzhiyun lp55xx_write(led->chip, addr[led->chan_nr], led_current);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
lp5562_load_engine(struct lp55xx_chip * chip)127*4882a593Smuzhiyun static void lp5562_load_engine(struct lp55xx_chip *chip)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun enum lp55xx_engine_index idx = chip->engine_idx;
130*4882a593Smuzhiyun static const u8 mask[] = {
131*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP5562_MODE_ENG1_M,
132*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP5562_MODE_ENG2_M,
133*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP5562_MODE_ENG3_M,
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun static const u8 val[] = {
137*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP5562_LOAD_ENG1,
138*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP5562_LOAD_ENG2,
139*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP5562_LOAD_ENG3,
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun lp55xx_update_bits(chip, LP5562_REG_OP_MODE, mask[idx], val[idx]);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun lp5562_wait_opmode_done();
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
lp5562_stop_engine(struct lp55xx_chip * chip)147*4882a593Smuzhiyun static void lp5562_stop_engine(struct lp55xx_chip *chip)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_OP_MODE, LP5562_CMD_DISABLE);
150*4882a593Smuzhiyun lp5562_wait_opmode_done();
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
lp5562_run_engine(struct lp55xx_chip * chip,bool start)153*4882a593Smuzhiyun static void lp5562_run_engine(struct lp55xx_chip *chip, bool start)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun int ret;
156*4882a593Smuzhiyun u8 mode;
157*4882a593Smuzhiyun u8 exec;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* stop engine */
160*4882a593Smuzhiyun if (!start) {
161*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_ENABLE, LP5562_ENABLE_DEFAULT);
162*4882a593Smuzhiyun lp5562_wait_enable_done();
163*4882a593Smuzhiyun lp5562_stop_engine(chip);
164*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_ENG_SEL, LP5562_ENG_SEL_PWM);
165*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_OP_MODE, LP5562_CMD_DIRECT);
166*4882a593Smuzhiyun lp5562_wait_opmode_done();
167*4882a593Smuzhiyun return;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /*
171*4882a593Smuzhiyun * To run the engine,
172*4882a593Smuzhiyun * operation mode and enable register should updated at the same time
173*4882a593Smuzhiyun */
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun ret = lp55xx_read(chip, LP5562_REG_OP_MODE, &mode);
176*4882a593Smuzhiyun if (ret)
177*4882a593Smuzhiyun return;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun ret = lp55xx_read(chip, LP5562_REG_ENABLE, &exec);
180*4882a593Smuzhiyun if (ret)
181*4882a593Smuzhiyun return;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun /* change operation mode to RUN only when each engine is loading */
184*4882a593Smuzhiyun if (LP5562_ENG1_IS_LOADING(mode)) {
185*4882a593Smuzhiyun mode = (mode & ~LP5562_MODE_ENG1_M) | LP5562_RUN_ENG1;
186*4882a593Smuzhiyun exec = (exec & ~LP5562_EXEC_ENG1_M) | LP5562_RUN_ENG1;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun if (LP5562_ENG2_IS_LOADING(mode)) {
190*4882a593Smuzhiyun mode = (mode & ~LP5562_MODE_ENG2_M) | LP5562_RUN_ENG2;
191*4882a593Smuzhiyun exec = (exec & ~LP5562_EXEC_ENG2_M) | LP5562_RUN_ENG2;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun if (LP5562_ENG3_IS_LOADING(mode)) {
195*4882a593Smuzhiyun mode = (mode & ~LP5562_MODE_ENG3_M) | LP5562_RUN_ENG3;
196*4882a593Smuzhiyun exec = (exec & ~LP5562_EXEC_ENG3_M) | LP5562_RUN_ENG3;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_OP_MODE, mode);
200*4882a593Smuzhiyun lp5562_wait_opmode_done();
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun lp55xx_update_bits(chip, LP5562_REG_ENABLE, LP5562_EXEC_M, exec);
203*4882a593Smuzhiyun lp5562_wait_enable_done();
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
lp5562_update_firmware(struct lp55xx_chip * chip,const u8 * data,size_t size)206*4882a593Smuzhiyun static int lp5562_update_firmware(struct lp55xx_chip *chip,
207*4882a593Smuzhiyun const u8 *data, size_t size)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun enum lp55xx_engine_index idx = chip->engine_idx;
210*4882a593Smuzhiyun u8 pattern[LP5562_PROGRAM_LENGTH] = {0};
211*4882a593Smuzhiyun static const u8 addr[] = {
212*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP5562_REG_PROG_MEM_ENG1,
213*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP5562_REG_PROG_MEM_ENG2,
214*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP5562_REG_PROG_MEM_ENG3,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun unsigned cmd;
217*4882a593Smuzhiyun char c[3];
218*4882a593Smuzhiyun int program_size;
219*4882a593Smuzhiyun int nrchars;
220*4882a593Smuzhiyun int offset = 0;
221*4882a593Smuzhiyun int ret;
222*4882a593Smuzhiyun int i;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* clear program memory before updating */
225*4882a593Smuzhiyun for (i = 0; i < LP5562_PROGRAM_LENGTH; i++)
226*4882a593Smuzhiyun lp55xx_write(chip, addr[idx] + i, 0);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun i = 0;
229*4882a593Smuzhiyun while ((offset < size - 1) && (i < LP5562_PROGRAM_LENGTH)) {
230*4882a593Smuzhiyun /* separate sscanfs because length is working only for %s */
231*4882a593Smuzhiyun ret = sscanf(data + offset, "%2s%n ", c, &nrchars);
232*4882a593Smuzhiyun if (ret != 1)
233*4882a593Smuzhiyun goto err;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun ret = sscanf(c, "%2x", &cmd);
236*4882a593Smuzhiyun if (ret != 1)
237*4882a593Smuzhiyun goto err;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun pattern[i] = (u8)cmd;
240*4882a593Smuzhiyun offset += nrchars;
241*4882a593Smuzhiyun i++;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* Each instruction is 16bit long. Check that length is even */
245*4882a593Smuzhiyun if (i % 2)
246*4882a593Smuzhiyun goto err;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun program_size = i;
249*4882a593Smuzhiyun for (i = 0; i < program_size; i++)
250*4882a593Smuzhiyun lp55xx_write(chip, addr[idx] + i, pattern[i]);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun return 0;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun err:
255*4882a593Smuzhiyun dev_err(&chip->cl->dev, "wrong pattern format\n");
256*4882a593Smuzhiyun return -EINVAL;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
lp5562_firmware_loaded(struct lp55xx_chip * chip)259*4882a593Smuzhiyun static void lp5562_firmware_loaded(struct lp55xx_chip *chip)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun const struct firmware *fw = chip->fw;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /*
264*4882a593Smuzhiyun * the firmware is encoded in ascii hex character, with 2 chars
265*4882a593Smuzhiyun * per byte
266*4882a593Smuzhiyun */
267*4882a593Smuzhiyun if (fw->size > (LP5562_PROGRAM_LENGTH * 2)) {
268*4882a593Smuzhiyun dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
269*4882a593Smuzhiyun fw->size);
270*4882a593Smuzhiyun return;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun /*
274*4882a593Smuzhiyun * Program memory sequence
275*4882a593Smuzhiyun * 1) set engine mode to "LOAD"
276*4882a593Smuzhiyun * 2) write firmware data into program memory
277*4882a593Smuzhiyun */
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun lp5562_load_engine(chip);
280*4882a593Smuzhiyun lp5562_update_firmware(chip, fw->data, fw->size);
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
lp5562_post_init_device(struct lp55xx_chip * chip)283*4882a593Smuzhiyun static int lp5562_post_init_device(struct lp55xx_chip *chip)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun int ret;
286*4882a593Smuzhiyun u8 cfg = LP5562_DEFAULT_CFG;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* Set all PWMs to direct control mode */
289*4882a593Smuzhiyun ret = lp55xx_write(chip, LP5562_REG_OP_MODE, LP5562_CMD_DIRECT);
290*4882a593Smuzhiyun if (ret)
291*4882a593Smuzhiyun return ret;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun lp5562_wait_opmode_done();
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun /* Update configuration for the clock setting */
296*4882a593Smuzhiyun if (!lp55xx_is_extclk_used(chip))
297*4882a593Smuzhiyun cfg |= LP5562_CLK_INT;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun ret = lp55xx_write(chip, LP5562_REG_CONFIG, cfg);
300*4882a593Smuzhiyun if (ret)
301*4882a593Smuzhiyun return ret;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /* Initialize all channels PWM to zero -> leds off */
304*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_R_PWM, 0);
305*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_G_PWM, 0);
306*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_B_PWM, 0);
307*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_W_PWM, 0);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /* Set LED map as register PWM by default */
310*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_ENG_SEL, LP5562_ENG_SEL_PWM);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun return 0;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
lp5562_led_brightness(struct lp55xx_led * led)315*4882a593Smuzhiyun static int lp5562_led_brightness(struct lp55xx_led *led)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
318*4882a593Smuzhiyun static const u8 addr[] = {
319*4882a593Smuzhiyun LP5562_REG_R_PWM,
320*4882a593Smuzhiyun LP5562_REG_G_PWM,
321*4882a593Smuzhiyun LP5562_REG_B_PWM,
322*4882a593Smuzhiyun LP5562_REG_W_PWM,
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun int ret;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun mutex_lock(&chip->lock);
327*4882a593Smuzhiyun ret = lp55xx_write(chip, addr[led->chan_nr], led->brightness);
328*4882a593Smuzhiyun mutex_unlock(&chip->lock);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return ret;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
lp5562_write_program_memory(struct lp55xx_chip * chip,u8 base,const u8 * rgb,int size)333*4882a593Smuzhiyun static void lp5562_write_program_memory(struct lp55xx_chip *chip,
334*4882a593Smuzhiyun u8 base, const u8 *rgb, int size)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun int i;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun if (!rgb || size <= 0)
339*4882a593Smuzhiyun return;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun for (i = 0; i < size; i++)
342*4882a593Smuzhiyun lp55xx_write(chip, base + i, *(rgb + i));
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun lp55xx_write(chip, base + i, 0);
345*4882a593Smuzhiyun lp55xx_write(chip, base + i + 1, 0);
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /* check the size of program count */
_is_pc_overflow(struct lp55xx_predef_pattern * ptn)349*4882a593Smuzhiyun static inline bool _is_pc_overflow(struct lp55xx_predef_pattern *ptn)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun return ptn->size_r >= LP5562_PROGRAM_LENGTH ||
352*4882a593Smuzhiyun ptn->size_g >= LP5562_PROGRAM_LENGTH ||
353*4882a593Smuzhiyun ptn->size_b >= LP5562_PROGRAM_LENGTH;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
lp5562_run_predef_led_pattern(struct lp55xx_chip * chip,int mode)356*4882a593Smuzhiyun static int lp5562_run_predef_led_pattern(struct lp55xx_chip *chip, int mode)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun struct lp55xx_predef_pattern *ptn;
359*4882a593Smuzhiyun int i;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun if (mode == LP5562_PATTERN_OFF) {
362*4882a593Smuzhiyun lp5562_run_engine(chip, false);
363*4882a593Smuzhiyun return 0;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun ptn = chip->pdata->patterns + (mode - 1);
367*4882a593Smuzhiyun if (!ptn || _is_pc_overflow(ptn)) {
368*4882a593Smuzhiyun dev_err(&chip->cl->dev, "invalid pattern data\n");
369*4882a593Smuzhiyun return -EINVAL;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun lp5562_stop_engine(chip);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /* Set LED map as RGB */
375*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_ENG_SEL, LP5562_ENG_SEL_RGB);
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /* Load engines */
378*4882a593Smuzhiyun for (i = LP55XX_ENGINE_1; i <= LP55XX_ENGINE_3; i++) {
379*4882a593Smuzhiyun chip->engine_idx = i;
380*4882a593Smuzhiyun lp5562_load_engine(chip);
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun /* Clear program registers */
384*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG1, 0);
385*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG1 + 1, 0);
386*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG2, 0);
387*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG2 + 1, 0);
388*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG3, 0);
389*4882a593Smuzhiyun lp55xx_write(chip, LP5562_REG_PROG_MEM_ENG3 + 1, 0);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun /* Program engines */
392*4882a593Smuzhiyun lp5562_write_program_memory(chip, LP5562_REG_PROG_MEM_ENG1,
393*4882a593Smuzhiyun ptn->r, ptn->size_r);
394*4882a593Smuzhiyun lp5562_write_program_memory(chip, LP5562_REG_PROG_MEM_ENG2,
395*4882a593Smuzhiyun ptn->g, ptn->size_g);
396*4882a593Smuzhiyun lp5562_write_program_memory(chip, LP5562_REG_PROG_MEM_ENG3,
397*4882a593Smuzhiyun ptn->b, ptn->size_b);
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun /* Run engines */
400*4882a593Smuzhiyun lp5562_run_engine(chip, true);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun return 0;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
lp5562_store_pattern(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)405*4882a593Smuzhiyun static ssize_t lp5562_store_pattern(struct device *dev,
406*4882a593Smuzhiyun struct device_attribute *attr,
407*4882a593Smuzhiyun const char *buf, size_t len)
408*4882a593Smuzhiyun {
409*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
410*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
411*4882a593Smuzhiyun struct lp55xx_predef_pattern *ptn = chip->pdata->patterns;
412*4882a593Smuzhiyun int num_patterns = chip->pdata->num_patterns;
413*4882a593Smuzhiyun unsigned long mode;
414*4882a593Smuzhiyun int ret;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun ret = kstrtoul(buf, 0, &mode);
417*4882a593Smuzhiyun if (ret)
418*4882a593Smuzhiyun return ret;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun if (mode > num_patterns || !ptn)
421*4882a593Smuzhiyun return -EINVAL;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun mutex_lock(&chip->lock);
424*4882a593Smuzhiyun ret = lp5562_run_predef_led_pattern(chip, mode);
425*4882a593Smuzhiyun mutex_unlock(&chip->lock);
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun if (ret)
428*4882a593Smuzhiyun return ret;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun return len;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
lp5562_store_engine_mux(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)433*4882a593Smuzhiyun static ssize_t lp5562_store_engine_mux(struct device *dev,
434*4882a593Smuzhiyun struct device_attribute *attr,
435*4882a593Smuzhiyun const char *buf, size_t len)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
438*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
439*4882a593Smuzhiyun u8 mask;
440*4882a593Smuzhiyun u8 val;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun /* LED map
443*4882a593Smuzhiyun * R ... Engine 1 (fixed)
444*4882a593Smuzhiyun * G ... Engine 2 (fixed)
445*4882a593Smuzhiyun * B ... Engine 3 (fixed)
446*4882a593Smuzhiyun * W ... Engine 1 or 2 or 3
447*4882a593Smuzhiyun */
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun if (sysfs_streq(buf, "RGB")) {
450*4882a593Smuzhiyun mask = LP5562_ENG_FOR_RGB_M;
451*4882a593Smuzhiyun val = LP5562_ENG_SEL_RGB;
452*4882a593Smuzhiyun } else if (sysfs_streq(buf, "W")) {
453*4882a593Smuzhiyun enum lp55xx_engine_index idx = chip->engine_idx;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun mask = LP5562_ENG_FOR_W_M;
456*4882a593Smuzhiyun switch (idx) {
457*4882a593Smuzhiyun case LP55XX_ENGINE_1:
458*4882a593Smuzhiyun val = LP5562_ENG1_FOR_W;
459*4882a593Smuzhiyun break;
460*4882a593Smuzhiyun case LP55XX_ENGINE_2:
461*4882a593Smuzhiyun val = LP5562_ENG2_FOR_W;
462*4882a593Smuzhiyun break;
463*4882a593Smuzhiyun case LP55XX_ENGINE_3:
464*4882a593Smuzhiyun val = LP5562_ENG3_FOR_W;
465*4882a593Smuzhiyun break;
466*4882a593Smuzhiyun default:
467*4882a593Smuzhiyun return -EINVAL;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun } else {
471*4882a593Smuzhiyun dev_err(dev, "choose RGB or W\n");
472*4882a593Smuzhiyun return -EINVAL;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun mutex_lock(&chip->lock);
476*4882a593Smuzhiyun lp55xx_update_bits(chip, LP5562_REG_ENG_SEL, mask, val);
477*4882a593Smuzhiyun mutex_unlock(&chip->lock);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun return len;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun static LP55XX_DEV_ATTR_WO(led_pattern, lp5562_store_pattern);
483*4882a593Smuzhiyun static LP55XX_DEV_ATTR_WO(engine_mux, lp5562_store_engine_mux);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun static struct attribute *lp5562_attributes[] = {
486*4882a593Smuzhiyun &dev_attr_led_pattern.attr,
487*4882a593Smuzhiyun &dev_attr_engine_mux.attr,
488*4882a593Smuzhiyun NULL,
489*4882a593Smuzhiyun };
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun static const struct attribute_group lp5562_group = {
492*4882a593Smuzhiyun .attrs = lp5562_attributes,
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun /* Chip specific configurations */
496*4882a593Smuzhiyun static struct lp55xx_device_config lp5562_cfg = {
497*4882a593Smuzhiyun .max_channel = LP5562_MAX_LEDS,
498*4882a593Smuzhiyun .reset = {
499*4882a593Smuzhiyun .addr = LP5562_REG_RESET,
500*4882a593Smuzhiyun .val = LP5562_RESET,
501*4882a593Smuzhiyun },
502*4882a593Smuzhiyun .enable = {
503*4882a593Smuzhiyun .addr = LP5562_REG_ENABLE,
504*4882a593Smuzhiyun .val = LP5562_ENABLE_DEFAULT,
505*4882a593Smuzhiyun },
506*4882a593Smuzhiyun .post_init_device = lp5562_post_init_device,
507*4882a593Smuzhiyun .set_led_current = lp5562_set_led_current,
508*4882a593Smuzhiyun .brightness_fn = lp5562_led_brightness,
509*4882a593Smuzhiyun .run_engine = lp5562_run_engine,
510*4882a593Smuzhiyun .firmware_cb = lp5562_firmware_loaded,
511*4882a593Smuzhiyun .dev_attr_group = &lp5562_group,
512*4882a593Smuzhiyun };
513*4882a593Smuzhiyun
lp5562_probe(struct i2c_client * client,const struct i2c_device_id * id)514*4882a593Smuzhiyun static int lp5562_probe(struct i2c_client *client,
515*4882a593Smuzhiyun const struct i2c_device_id *id)
516*4882a593Smuzhiyun {
517*4882a593Smuzhiyun int ret;
518*4882a593Smuzhiyun struct lp55xx_chip *chip;
519*4882a593Smuzhiyun struct lp55xx_led *led;
520*4882a593Smuzhiyun struct lp55xx_platform_data *pdata = dev_get_platdata(&client->dev);
521*4882a593Smuzhiyun struct device_node *np = dev_of_node(&client->dev);
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
524*4882a593Smuzhiyun if (!chip)
525*4882a593Smuzhiyun return -ENOMEM;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun chip->cfg = &lp5562_cfg;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun if (!pdata) {
530*4882a593Smuzhiyun if (np) {
531*4882a593Smuzhiyun pdata = lp55xx_of_populate_pdata(&client->dev, np,
532*4882a593Smuzhiyun chip);
533*4882a593Smuzhiyun if (IS_ERR(pdata))
534*4882a593Smuzhiyun return PTR_ERR(pdata);
535*4882a593Smuzhiyun } else {
536*4882a593Smuzhiyun dev_err(&client->dev, "no platform data\n");
537*4882a593Smuzhiyun return -EINVAL;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun led = devm_kcalloc(&client->dev,
543*4882a593Smuzhiyun pdata->num_channels, sizeof(*led), GFP_KERNEL);
544*4882a593Smuzhiyun if (!led)
545*4882a593Smuzhiyun return -ENOMEM;
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun chip->cl = client;
548*4882a593Smuzhiyun chip->pdata = pdata;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun mutex_init(&chip->lock);
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun i2c_set_clientdata(client, led);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun ret = lp55xx_init_device(chip);
555*4882a593Smuzhiyun if (ret)
556*4882a593Smuzhiyun goto err_init;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun ret = lp55xx_register_leds(led, chip);
559*4882a593Smuzhiyun if (ret)
560*4882a593Smuzhiyun goto err_out;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun ret = lp55xx_register_sysfs(chip);
563*4882a593Smuzhiyun if (ret) {
564*4882a593Smuzhiyun dev_err(&client->dev, "registering sysfs failed\n");
565*4882a593Smuzhiyun goto err_out;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun return 0;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun err_out:
571*4882a593Smuzhiyun lp55xx_deinit_device(chip);
572*4882a593Smuzhiyun err_init:
573*4882a593Smuzhiyun return ret;
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun
lp5562_remove(struct i2c_client * client)576*4882a593Smuzhiyun static int lp5562_remove(struct i2c_client *client)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(client);
579*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun lp5562_stop_engine(chip);
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun lp55xx_unregister_sysfs(chip);
584*4882a593Smuzhiyun lp55xx_deinit_device(chip);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun return 0;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun static const struct i2c_device_id lp5562_id[] = {
590*4882a593Smuzhiyun { "lp5562", 0 },
591*4882a593Smuzhiyun { }
592*4882a593Smuzhiyun };
593*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, lp5562_id);
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun #ifdef CONFIG_OF
596*4882a593Smuzhiyun static const struct of_device_id of_lp5562_leds_match[] = {
597*4882a593Smuzhiyun { .compatible = "ti,lp5562", },
598*4882a593Smuzhiyun {},
599*4882a593Smuzhiyun };
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_lp5562_leds_match);
602*4882a593Smuzhiyun #endif
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun static struct i2c_driver lp5562_driver = {
605*4882a593Smuzhiyun .driver = {
606*4882a593Smuzhiyun .name = "lp5562",
607*4882a593Smuzhiyun .of_match_table = of_match_ptr(of_lp5562_leds_match),
608*4882a593Smuzhiyun },
609*4882a593Smuzhiyun .probe = lp5562_probe,
610*4882a593Smuzhiyun .remove = lp5562_remove,
611*4882a593Smuzhiyun .id_table = lp5562_id,
612*4882a593Smuzhiyun };
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun module_i2c_driver(lp5562_driver);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun MODULE_DESCRIPTION("Texas Instruments LP5562 LED Driver");
617*4882a593Smuzhiyun MODULE_AUTHOR("Milo Kim");
618*4882a593Smuzhiyun MODULE_LICENSE("GPL");
619