1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * LP5521 LED chip driver.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 Nokia Corporation
6*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Contact: Samu Onkalo <samu.p.onkalo@nokia.com>
9*4882a593Smuzhiyun * Milo(Woogyom) Kim <milo.kim@ti.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/firmware.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/leds.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/mutex.h>
18*4882a593Smuzhiyun #include <linux/platform_data/leds-lp55xx.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include "leds-lp55xx-common.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define LP5521_PROGRAM_LENGTH 32
25*4882a593Smuzhiyun #define LP5521_MAX_LEDS 3
26*4882a593Smuzhiyun #define LP5521_CMD_DIRECT 0x3F
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Registers */
29*4882a593Smuzhiyun #define LP5521_REG_ENABLE 0x00
30*4882a593Smuzhiyun #define LP5521_REG_OP_MODE 0x01
31*4882a593Smuzhiyun #define LP5521_REG_R_PWM 0x02
32*4882a593Smuzhiyun #define LP5521_REG_G_PWM 0x03
33*4882a593Smuzhiyun #define LP5521_REG_B_PWM 0x04
34*4882a593Smuzhiyun #define LP5521_REG_R_CURRENT 0x05
35*4882a593Smuzhiyun #define LP5521_REG_G_CURRENT 0x06
36*4882a593Smuzhiyun #define LP5521_REG_B_CURRENT 0x07
37*4882a593Smuzhiyun #define LP5521_REG_CONFIG 0x08
38*4882a593Smuzhiyun #define LP5521_REG_STATUS 0x0C
39*4882a593Smuzhiyun #define LP5521_REG_RESET 0x0D
40*4882a593Smuzhiyun #define LP5521_REG_R_PROG_MEM 0x10
41*4882a593Smuzhiyun #define LP5521_REG_G_PROG_MEM 0x30
42*4882a593Smuzhiyun #define LP5521_REG_B_PROG_MEM 0x50
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Base register to set LED current */
45*4882a593Smuzhiyun #define LP5521_REG_LED_CURRENT_BASE LP5521_REG_R_CURRENT
46*4882a593Smuzhiyun /* Base register to set the brightness */
47*4882a593Smuzhiyun #define LP5521_REG_LED_PWM_BASE LP5521_REG_R_PWM
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Bits in ENABLE register */
50*4882a593Smuzhiyun #define LP5521_MASTER_ENABLE 0x40 /* Chip master enable */
51*4882a593Smuzhiyun #define LP5521_LOGARITHMIC_PWM 0x80 /* Logarithmic PWM adjustment */
52*4882a593Smuzhiyun #define LP5521_EXEC_RUN 0x2A
53*4882a593Smuzhiyun #define LP5521_ENABLE_DEFAULT \
54*4882a593Smuzhiyun (LP5521_MASTER_ENABLE | LP5521_LOGARITHMIC_PWM)
55*4882a593Smuzhiyun #define LP5521_ENABLE_RUN_PROGRAM \
56*4882a593Smuzhiyun (LP5521_ENABLE_DEFAULT | LP5521_EXEC_RUN)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* CONFIG register */
59*4882a593Smuzhiyun #define LP5521_PWM_HF 0x40 /* PWM: 0 = 256Hz, 1 = 558Hz */
60*4882a593Smuzhiyun #define LP5521_PWRSAVE_EN 0x20 /* 1 = Power save mode */
61*4882a593Smuzhiyun #define LP5521_CP_MODE_OFF 0 /* Charge pump (CP) off */
62*4882a593Smuzhiyun #define LP5521_CP_MODE_BYPASS 8 /* CP forced to bypass mode */
63*4882a593Smuzhiyun #define LP5521_CP_MODE_1X5 0x10 /* CP forced to 1.5x mode */
64*4882a593Smuzhiyun #define LP5521_CP_MODE_AUTO 0x18 /* Automatic mode selection */
65*4882a593Smuzhiyun #define LP5521_R_TO_BATT 0x04 /* R out: 0 = CP, 1 = Vbat */
66*4882a593Smuzhiyun #define LP5521_CLK_INT 0x01 /* Internal clock */
67*4882a593Smuzhiyun #define LP5521_DEFAULT_CFG \
68*4882a593Smuzhiyun (LP5521_PWM_HF | LP5521_PWRSAVE_EN | LP5521_CP_MODE_AUTO)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Status */
71*4882a593Smuzhiyun #define LP5521_EXT_CLK_USED 0x08
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* default R channel current register value */
74*4882a593Smuzhiyun #define LP5521_REG_R_CURR_DEFAULT 0xAF
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* Reset register value */
77*4882a593Smuzhiyun #define LP5521_RESET 0xFF
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Program Memory Operations */
80*4882a593Smuzhiyun #define LP5521_MODE_R_M 0x30 /* Operation Mode Register */
81*4882a593Smuzhiyun #define LP5521_MODE_G_M 0x0C
82*4882a593Smuzhiyun #define LP5521_MODE_B_M 0x03
83*4882a593Smuzhiyun #define LP5521_LOAD_R 0x10
84*4882a593Smuzhiyun #define LP5521_LOAD_G 0x04
85*4882a593Smuzhiyun #define LP5521_LOAD_B 0x01
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define LP5521_R_IS_LOADING(mode) \
88*4882a593Smuzhiyun ((mode & LP5521_MODE_R_M) == LP5521_LOAD_R)
89*4882a593Smuzhiyun #define LP5521_G_IS_LOADING(mode) \
90*4882a593Smuzhiyun ((mode & LP5521_MODE_G_M) == LP5521_LOAD_G)
91*4882a593Smuzhiyun #define LP5521_B_IS_LOADING(mode) \
92*4882a593Smuzhiyun ((mode & LP5521_MODE_B_M) == LP5521_LOAD_B)
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #define LP5521_EXEC_R_M 0x30 /* Enable Register */
95*4882a593Smuzhiyun #define LP5521_EXEC_G_M 0x0C
96*4882a593Smuzhiyun #define LP5521_EXEC_B_M 0x03
97*4882a593Smuzhiyun #define LP5521_EXEC_M 0x3F
98*4882a593Smuzhiyun #define LP5521_RUN_R 0x20
99*4882a593Smuzhiyun #define LP5521_RUN_G 0x08
100*4882a593Smuzhiyun #define LP5521_RUN_B 0x02
101*4882a593Smuzhiyun
lp5521_wait_opmode_done(void)102*4882a593Smuzhiyun static inline void lp5521_wait_opmode_done(void)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun /* operation mode change needs to be longer than 153 us */
105*4882a593Smuzhiyun usleep_range(200, 300);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
lp5521_wait_enable_done(void)108*4882a593Smuzhiyun static inline void lp5521_wait_enable_done(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun /* it takes more 488 us to update ENABLE register */
111*4882a593Smuzhiyun usleep_range(500, 600);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
lp5521_set_led_current(struct lp55xx_led * led,u8 led_current)114*4882a593Smuzhiyun static void lp5521_set_led_current(struct lp55xx_led *led, u8 led_current)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun led->led_current = led_current;
117*4882a593Smuzhiyun lp55xx_write(led->chip, LP5521_REG_LED_CURRENT_BASE + led->chan_nr,
118*4882a593Smuzhiyun led_current);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
lp5521_load_engine(struct lp55xx_chip * chip)121*4882a593Smuzhiyun static void lp5521_load_engine(struct lp55xx_chip *chip)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun enum lp55xx_engine_index idx = chip->engine_idx;
124*4882a593Smuzhiyun static const u8 mask[] = {
125*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP5521_MODE_R_M,
126*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP5521_MODE_G_M,
127*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP5521_MODE_B_M,
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static const u8 val[] = {
131*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP5521_LOAD_R,
132*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP5521_LOAD_G,
133*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP5521_LOAD_B,
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun lp55xx_update_bits(chip, LP5521_REG_OP_MODE, mask[idx], val[idx]);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun lp5521_wait_opmode_done();
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
lp5521_stop_all_engines(struct lp55xx_chip * chip)141*4882a593Smuzhiyun static void lp5521_stop_all_engines(struct lp55xx_chip *chip)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun lp55xx_write(chip, LP5521_REG_OP_MODE, 0);
144*4882a593Smuzhiyun lp5521_wait_opmode_done();
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
lp5521_stop_engine(struct lp55xx_chip * chip)147*4882a593Smuzhiyun static void lp5521_stop_engine(struct lp55xx_chip *chip)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun enum lp55xx_engine_index idx = chip->engine_idx;
150*4882a593Smuzhiyun static const u8 mask[] = {
151*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP5521_MODE_R_M,
152*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP5521_MODE_G_M,
153*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP5521_MODE_B_M,
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun lp55xx_update_bits(chip, LP5521_REG_OP_MODE, mask[idx], 0);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun lp5521_wait_opmode_done();
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
lp5521_run_engine(struct lp55xx_chip * chip,bool start)161*4882a593Smuzhiyun static void lp5521_run_engine(struct lp55xx_chip *chip, bool start)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun int ret;
164*4882a593Smuzhiyun u8 mode;
165*4882a593Smuzhiyun u8 exec;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* stop engine */
168*4882a593Smuzhiyun if (!start) {
169*4882a593Smuzhiyun lp5521_stop_engine(chip);
170*4882a593Smuzhiyun lp55xx_write(chip, LP5521_REG_OP_MODE, LP5521_CMD_DIRECT);
171*4882a593Smuzhiyun lp5521_wait_opmode_done();
172*4882a593Smuzhiyun return;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /*
176*4882a593Smuzhiyun * To run the engine,
177*4882a593Smuzhiyun * operation mode and enable register should updated at the same time
178*4882a593Smuzhiyun */
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun ret = lp55xx_read(chip, LP5521_REG_OP_MODE, &mode);
181*4882a593Smuzhiyun if (ret)
182*4882a593Smuzhiyun return;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun ret = lp55xx_read(chip, LP5521_REG_ENABLE, &exec);
185*4882a593Smuzhiyun if (ret)
186*4882a593Smuzhiyun return;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /* change operation mode to RUN only when each engine is loading */
189*4882a593Smuzhiyun if (LP5521_R_IS_LOADING(mode)) {
190*4882a593Smuzhiyun mode = (mode & ~LP5521_MODE_R_M) | LP5521_RUN_R;
191*4882a593Smuzhiyun exec = (exec & ~LP5521_EXEC_R_M) | LP5521_RUN_R;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun if (LP5521_G_IS_LOADING(mode)) {
195*4882a593Smuzhiyun mode = (mode & ~LP5521_MODE_G_M) | LP5521_RUN_G;
196*4882a593Smuzhiyun exec = (exec & ~LP5521_EXEC_G_M) | LP5521_RUN_G;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun if (LP5521_B_IS_LOADING(mode)) {
200*4882a593Smuzhiyun mode = (mode & ~LP5521_MODE_B_M) | LP5521_RUN_B;
201*4882a593Smuzhiyun exec = (exec & ~LP5521_EXEC_B_M) | LP5521_RUN_B;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun lp55xx_write(chip, LP5521_REG_OP_MODE, mode);
205*4882a593Smuzhiyun lp5521_wait_opmode_done();
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun lp55xx_update_bits(chip, LP5521_REG_ENABLE, LP5521_EXEC_M, exec);
208*4882a593Smuzhiyun lp5521_wait_enable_done();
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
lp5521_update_program_memory(struct lp55xx_chip * chip,const u8 * data,size_t size)211*4882a593Smuzhiyun static int lp5521_update_program_memory(struct lp55xx_chip *chip,
212*4882a593Smuzhiyun const u8 *data, size_t size)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun enum lp55xx_engine_index idx = chip->engine_idx;
215*4882a593Smuzhiyun u8 pattern[LP5521_PROGRAM_LENGTH] = {0};
216*4882a593Smuzhiyun static const u8 addr[] = {
217*4882a593Smuzhiyun [LP55XX_ENGINE_1] = LP5521_REG_R_PROG_MEM,
218*4882a593Smuzhiyun [LP55XX_ENGINE_2] = LP5521_REG_G_PROG_MEM,
219*4882a593Smuzhiyun [LP55XX_ENGINE_3] = LP5521_REG_B_PROG_MEM,
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun unsigned cmd;
222*4882a593Smuzhiyun char c[3];
223*4882a593Smuzhiyun int nrchars;
224*4882a593Smuzhiyun int ret;
225*4882a593Smuzhiyun int offset = 0;
226*4882a593Smuzhiyun int i = 0;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun while ((offset < size - 1) && (i < LP5521_PROGRAM_LENGTH)) {
229*4882a593Smuzhiyun /* separate sscanfs because length is working only for %s */
230*4882a593Smuzhiyun ret = sscanf(data + offset, "%2s%n ", c, &nrchars);
231*4882a593Smuzhiyun if (ret != 1)
232*4882a593Smuzhiyun goto err;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun ret = sscanf(c, "%2x", &cmd);
235*4882a593Smuzhiyun if (ret != 1)
236*4882a593Smuzhiyun goto err;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun pattern[i] = (u8)cmd;
239*4882a593Smuzhiyun offset += nrchars;
240*4882a593Smuzhiyun i++;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /* Each instruction is 16bit long. Check that length is even */
244*4882a593Smuzhiyun if (i % 2)
245*4882a593Smuzhiyun goto err;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun for (i = 0; i < LP5521_PROGRAM_LENGTH; i++) {
248*4882a593Smuzhiyun ret = lp55xx_write(chip, addr[idx] + i, pattern[i]);
249*4882a593Smuzhiyun if (ret)
250*4882a593Smuzhiyun return -EINVAL;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun return size;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun err:
256*4882a593Smuzhiyun dev_err(&chip->cl->dev, "wrong pattern format\n");
257*4882a593Smuzhiyun return -EINVAL;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
lp5521_firmware_loaded(struct lp55xx_chip * chip)260*4882a593Smuzhiyun static void lp5521_firmware_loaded(struct lp55xx_chip *chip)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun const struct firmware *fw = chip->fw;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun if (fw->size > LP5521_PROGRAM_LENGTH) {
265*4882a593Smuzhiyun dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
266*4882a593Smuzhiyun fw->size);
267*4882a593Smuzhiyun return;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /*
271*4882a593Smuzhiyun * Program memory sequence
272*4882a593Smuzhiyun * 1) set engine mode to "LOAD"
273*4882a593Smuzhiyun * 2) write firmware data into program memory
274*4882a593Smuzhiyun */
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun lp5521_load_engine(chip);
277*4882a593Smuzhiyun lp5521_update_program_memory(chip, fw->data, fw->size);
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
lp5521_post_init_device(struct lp55xx_chip * chip)280*4882a593Smuzhiyun static int lp5521_post_init_device(struct lp55xx_chip *chip)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun int ret;
283*4882a593Smuzhiyun u8 val;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /*
286*4882a593Smuzhiyun * Make sure that the chip is reset by reading back the r channel
287*4882a593Smuzhiyun * current reg. This is dummy read is required on some platforms -
288*4882a593Smuzhiyun * otherwise further access to the R G B channels in the
289*4882a593Smuzhiyun * LP5521_REG_ENABLE register will not have any effect - strange!
290*4882a593Smuzhiyun */
291*4882a593Smuzhiyun ret = lp55xx_read(chip, LP5521_REG_R_CURRENT, &val);
292*4882a593Smuzhiyun if (ret) {
293*4882a593Smuzhiyun dev_err(&chip->cl->dev, "error in resetting chip\n");
294*4882a593Smuzhiyun return ret;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun if (val != LP5521_REG_R_CURR_DEFAULT) {
297*4882a593Smuzhiyun dev_err(&chip->cl->dev,
298*4882a593Smuzhiyun "unexpected data in register (expected 0x%x got 0x%x)\n",
299*4882a593Smuzhiyun LP5521_REG_R_CURR_DEFAULT, val);
300*4882a593Smuzhiyun ret = -EINVAL;
301*4882a593Smuzhiyun return ret;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun usleep_range(10000, 20000);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* Set all PWMs to direct control mode */
306*4882a593Smuzhiyun ret = lp55xx_write(chip, LP5521_REG_OP_MODE, LP5521_CMD_DIRECT);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* Update configuration for the clock setting */
309*4882a593Smuzhiyun val = LP5521_DEFAULT_CFG;
310*4882a593Smuzhiyun if (!lp55xx_is_extclk_used(chip))
311*4882a593Smuzhiyun val |= LP5521_CLK_INT;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun ret = lp55xx_write(chip, LP5521_REG_CONFIG, val);
314*4882a593Smuzhiyun if (ret)
315*4882a593Smuzhiyun return ret;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun /* Initialize all channels PWM to zero -> leds off */
318*4882a593Smuzhiyun lp55xx_write(chip, LP5521_REG_R_PWM, 0);
319*4882a593Smuzhiyun lp55xx_write(chip, LP5521_REG_G_PWM, 0);
320*4882a593Smuzhiyun lp55xx_write(chip, LP5521_REG_B_PWM, 0);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* Set engines are set to run state when OP_MODE enables engines */
323*4882a593Smuzhiyun ret = lp55xx_write(chip, LP5521_REG_ENABLE, LP5521_ENABLE_RUN_PROGRAM);
324*4882a593Smuzhiyun if (ret)
325*4882a593Smuzhiyun return ret;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun lp5521_wait_enable_done();
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun return 0;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
lp5521_run_selftest(struct lp55xx_chip * chip,char * buf)332*4882a593Smuzhiyun static int lp5521_run_selftest(struct lp55xx_chip *chip, char *buf)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun struct lp55xx_platform_data *pdata = chip->pdata;
335*4882a593Smuzhiyun int ret;
336*4882a593Smuzhiyun u8 status;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun ret = lp55xx_read(chip, LP5521_REG_STATUS, &status);
339*4882a593Smuzhiyun if (ret < 0)
340*4882a593Smuzhiyun return ret;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun if (pdata->clock_mode != LP55XX_CLOCK_EXT)
343*4882a593Smuzhiyun return 0;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /* Check that ext clock is really in use if requested */
346*4882a593Smuzhiyun if ((status & LP5521_EXT_CLK_USED) == 0)
347*4882a593Smuzhiyun return -EIO;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun return 0;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
lp5521_multicolor_brightness(struct lp55xx_led * led)352*4882a593Smuzhiyun static int lp5521_multicolor_brightness(struct lp55xx_led *led)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
355*4882a593Smuzhiyun int ret;
356*4882a593Smuzhiyun int i;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun mutex_lock(&chip->lock);
359*4882a593Smuzhiyun for (i = 0; i < led->mc_cdev.num_colors; i++) {
360*4882a593Smuzhiyun ret = lp55xx_write(chip,
361*4882a593Smuzhiyun LP5521_REG_LED_PWM_BASE +
362*4882a593Smuzhiyun led->mc_cdev.subled_info[i].channel,
363*4882a593Smuzhiyun led->mc_cdev.subled_info[i].brightness);
364*4882a593Smuzhiyun if (ret)
365*4882a593Smuzhiyun break;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun mutex_unlock(&chip->lock);
368*4882a593Smuzhiyun return ret;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
lp5521_led_brightness(struct lp55xx_led * led)371*4882a593Smuzhiyun static int lp5521_led_brightness(struct lp55xx_led *led)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
374*4882a593Smuzhiyun int ret;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun mutex_lock(&chip->lock);
377*4882a593Smuzhiyun ret = lp55xx_write(chip, LP5521_REG_LED_PWM_BASE + led->chan_nr,
378*4882a593Smuzhiyun led->brightness);
379*4882a593Smuzhiyun mutex_unlock(&chip->lock);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun return ret;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
show_engine_mode(struct device * dev,struct device_attribute * attr,char * buf,int nr)384*4882a593Smuzhiyun static ssize_t show_engine_mode(struct device *dev,
385*4882a593Smuzhiyun struct device_attribute *attr,
386*4882a593Smuzhiyun char *buf, int nr)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
389*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
390*4882a593Smuzhiyun enum lp55xx_engine_mode mode = chip->engines[nr - 1].mode;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun switch (mode) {
393*4882a593Smuzhiyun case LP55XX_ENGINE_RUN:
394*4882a593Smuzhiyun return sprintf(buf, "run\n");
395*4882a593Smuzhiyun case LP55XX_ENGINE_LOAD:
396*4882a593Smuzhiyun return sprintf(buf, "load\n");
397*4882a593Smuzhiyun case LP55XX_ENGINE_DISABLED:
398*4882a593Smuzhiyun default:
399*4882a593Smuzhiyun return sprintf(buf, "disabled\n");
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun show_mode(1)
403*4882a593Smuzhiyun show_mode(2)
404*4882a593Smuzhiyun show_mode(3)
405*4882a593Smuzhiyun
store_engine_mode(struct device * dev,struct device_attribute * attr,const char * buf,size_t len,int nr)406*4882a593Smuzhiyun static ssize_t store_engine_mode(struct device *dev,
407*4882a593Smuzhiyun struct device_attribute *attr,
408*4882a593Smuzhiyun const char *buf, size_t len, int nr)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
411*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
412*4882a593Smuzhiyun struct lp55xx_engine *engine = &chip->engines[nr - 1];
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun mutex_lock(&chip->lock);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun chip->engine_idx = nr;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (!strncmp(buf, "run", 3)) {
419*4882a593Smuzhiyun lp5521_run_engine(chip, true);
420*4882a593Smuzhiyun engine->mode = LP55XX_ENGINE_RUN;
421*4882a593Smuzhiyun } else if (!strncmp(buf, "load", 4)) {
422*4882a593Smuzhiyun lp5521_stop_engine(chip);
423*4882a593Smuzhiyun lp5521_load_engine(chip);
424*4882a593Smuzhiyun engine->mode = LP55XX_ENGINE_LOAD;
425*4882a593Smuzhiyun } else if (!strncmp(buf, "disabled", 8)) {
426*4882a593Smuzhiyun lp5521_stop_engine(chip);
427*4882a593Smuzhiyun engine->mode = LP55XX_ENGINE_DISABLED;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun mutex_unlock(&chip->lock);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun return len;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun store_mode(1)
435*4882a593Smuzhiyun store_mode(2)
436*4882a593Smuzhiyun store_mode(3)
437*4882a593Smuzhiyun
store_engine_load(struct device * dev,struct device_attribute * attr,const char * buf,size_t len,int nr)438*4882a593Smuzhiyun static ssize_t store_engine_load(struct device *dev,
439*4882a593Smuzhiyun struct device_attribute *attr,
440*4882a593Smuzhiyun const char *buf, size_t len, int nr)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
443*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
444*4882a593Smuzhiyun int ret;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun mutex_lock(&chip->lock);
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun chip->engine_idx = nr;
449*4882a593Smuzhiyun lp5521_load_engine(chip);
450*4882a593Smuzhiyun ret = lp5521_update_program_memory(chip, buf, len);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun mutex_unlock(&chip->lock);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun return ret;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun store_load(1)
457*4882a593Smuzhiyun store_load(2)
458*4882a593Smuzhiyun store_load(3)
459*4882a593Smuzhiyun
lp5521_selftest(struct device * dev,struct device_attribute * attr,char * buf)460*4882a593Smuzhiyun static ssize_t lp5521_selftest(struct device *dev,
461*4882a593Smuzhiyun struct device_attribute *attr,
462*4882a593Smuzhiyun char *buf)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(to_i2c_client(dev));
465*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
466*4882a593Smuzhiyun int ret;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun mutex_lock(&chip->lock);
469*4882a593Smuzhiyun ret = lp5521_run_selftest(chip, buf);
470*4882a593Smuzhiyun mutex_unlock(&chip->lock);
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%s\n", ret ? "FAIL" : "OK");
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun /* device attributes */
476*4882a593Smuzhiyun static LP55XX_DEV_ATTR_RW(engine1_mode, show_engine1_mode, store_engine1_mode);
477*4882a593Smuzhiyun static LP55XX_DEV_ATTR_RW(engine2_mode, show_engine2_mode, store_engine2_mode);
478*4882a593Smuzhiyun static LP55XX_DEV_ATTR_RW(engine3_mode, show_engine3_mode, store_engine3_mode);
479*4882a593Smuzhiyun static LP55XX_DEV_ATTR_WO(engine1_load, store_engine1_load);
480*4882a593Smuzhiyun static LP55XX_DEV_ATTR_WO(engine2_load, store_engine2_load);
481*4882a593Smuzhiyun static LP55XX_DEV_ATTR_WO(engine3_load, store_engine3_load);
482*4882a593Smuzhiyun static LP55XX_DEV_ATTR_RO(selftest, lp5521_selftest);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun static struct attribute *lp5521_attributes[] = {
485*4882a593Smuzhiyun &dev_attr_engine1_mode.attr,
486*4882a593Smuzhiyun &dev_attr_engine2_mode.attr,
487*4882a593Smuzhiyun &dev_attr_engine3_mode.attr,
488*4882a593Smuzhiyun &dev_attr_engine1_load.attr,
489*4882a593Smuzhiyun &dev_attr_engine2_load.attr,
490*4882a593Smuzhiyun &dev_attr_engine3_load.attr,
491*4882a593Smuzhiyun &dev_attr_selftest.attr,
492*4882a593Smuzhiyun NULL
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun static const struct attribute_group lp5521_group = {
496*4882a593Smuzhiyun .attrs = lp5521_attributes,
497*4882a593Smuzhiyun };
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun /* Chip specific configurations */
500*4882a593Smuzhiyun static struct lp55xx_device_config lp5521_cfg = {
501*4882a593Smuzhiyun .reset = {
502*4882a593Smuzhiyun .addr = LP5521_REG_RESET,
503*4882a593Smuzhiyun .val = LP5521_RESET,
504*4882a593Smuzhiyun },
505*4882a593Smuzhiyun .enable = {
506*4882a593Smuzhiyun .addr = LP5521_REG_ENABLE,
507*4882a593Smuzhiyun .val = LP5521_ENABLE_DEFAULT,
508*4882a593Smuzhiyun },
509*4882a593Smuzhiyun .max_channel = LP5521_MAX_LEDS,
510*4882a593Smuzhiyun .post_init_device = lp5521_post_init_device,
511*4882a593Smuzhiyun .brightness_fn = lp5521_led_brightness,
512*4882a593Smuzhiyun .multicolor_brightness_fn = lp5521_multicolor_brightness,
513*4882a593Smuzhiyun .set_led_current = lp5521_set_led_current,
514*4882a593Smuzhiyun .firmware_cb = lp5521_firmware_loaded,
515*4882a593Smuzhiyun .run_engine = lp5521_run_engine,
516*4882a593Smuzhiyun .dev_attr_group = &lp5521_group,
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun
lp5521_probe(struct i2c_client * client,const struct i2c_device_id * id)519*4882a593Smuzhiyun static int lp5521_probe(struct i2c_client *client,
520*4882a593Smuzhiyun const struct i2c_device_id *id)
521*4882a593Smuzhiyun {
522*4882a593Smuzhiyun int ret;
523*4882a593Smuzhiyun struct lp55xx_chip *chip;
524*4882a593Smuzhiyun struct lp55xx_led *led;
525*4882a593Smuzhiyun struct lp55xx_platform_data *pdata = dev_get_platdata(&client->dev);
526*4882a593Smuzhiyun struct device_node *np = dev_of_node(&client->dev);
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
529*4882a593Smuzhiyun if (!chip)
530*4882a593Smuzhiyun return -ENOMEM;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun chip->cfg = &lp5521_cfg;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun if (!pdata) {
535*4882a593Smuzhiyun if (np) {
536*4882a593Smuzhiyun pdata = lp55xx_of_populate_pdata(&client->dev, np,
537*4882a593Smuzhiyun chip);
538*4882a593Smuzhiyun if (IS_ERR(pdata))
539*4882a593Smuzhiyun return PTR_ERR(pdata);
540*4882a593Smuzhiyun } else {
541*4882a593Smuzhiyun dev_err(&client->dev, "no platform data\n");
542*4882a593Smuzhiyun return -EINVAL;
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun led = devm_kcalloc(&client->dev,
547*4882a593Smuzhiyun pdata->num_channels, sizeof(*led), GFP_KERNEL);
548*4882a593Smuzhiyun if (!led)
549*4882a593Smuzhiyun return -ENOMEM;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun chip->cl = client;
552*4882a593Smuzhiyun chip->pdata = pdata;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun mutex_init(&chip->lock);
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun i2c_set_clientdata(client, led);
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun ret = lp55xx_init_device(chip);
559*4882a593Smuzhiyun if (ret)
560*4882a593Smuzhiyun goto err_init;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun dev_info(&client->dev, "%s programmable led chip found\n", id->name);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun ret = lp55xx_register_leds(led, chip);
565*4882a593Smuzhiyun if (ret)
566*4882a593Smuzhiyun goto err_out;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun ret = lp55xx_register_sysfs(chip);
569*4882a593Smuzhiyun if (ret) {
570*4882a593Smuzhiyun dev_err(&client->dev, "registering sysfs failed\n");
571*4882a593Smuzhiyun goto err_out;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun return 0;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun err_out:
577*4882a593Smuzhiyun lp55xx_deinit_device(chip);
578*4882a593Smuzhiyun err_init:
579*4882a593Smuzhiyun return ret;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
lp5521_remove(struct i2c_client * client)582*4882a593Smuzhiyun static int lp5521_remove(struct i2c_client *client)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun struct lp55xx_led *led = i2c_get_clientdata(client);
585*4882a593Smuzhiyun struct lp55xx_chip *chip = led->chip;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun lp5521_stop_all_engines(chip);
588*4882a593Smuzhiyun lp55xx_unregister_sysfs(chip);
589*4882a593Smuzhiyun lp55xx_deinit_device(chip);
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun return 0;
592*4882a593Smuzhiyun }
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun static const struct i2c_device_id lp5521_id[] = {
595*4882a593Smuzhiyun { "lp5521", 0 }, /* Three channel chip */
596*4882a593Smuzhiyun { }
597*4882a593Smuzhiyun };
598*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, lp5521_id);
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun #ifdef CONFIG_OF
601*4882a593Smuzhiyun static const struct of_device_id of_lp5521_leds_match[] = {
602*4882a593Smuzhiyun { .compatible = "national,lp5521", },
603*4882a593Smuzhiyun {},
604*4882a593Smuzhiyun };
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_lp5521_leds_match);
607*4882a593Smuzhiyun #endif
608*4882a593Smuzhiyun static struct i2c_driver lp5521_driver = {
609*4882a593Smuzhiyun .driver = {
610*4882a593Smuzhiyun .name = "lp5521",
611*4882a593Smuzhiyun .of_match_table = of_match_ptr(of_lp5521_leds_match),
612*4882a593Smuzhiyun },
613*4882a593Smuzhiyun .probe = lp5521_probe,
614*4882a593Smuzhiyun .remove = lp5521_remove,
615*4882a593Smuzhiyun .id_table = lp5521_id,
616*4882a593Smuzhiyun };
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun module_i2c_driver(lp5521_driver);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun MODULE_AUTHOR("Mathias Nyman, Yuri Zaporozhets, Samu Onkalo");
621*4882a593Smuzhiyun MODULE_AUTHOR("Milo Kim <milo.kim@ti.com>");
622*4882a593Smuzhiyun MODULE_DESCRIPTION("LP5521 LED engine");
623*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
624