1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // TI LP50XX LED chip family driver
3*4882a593Smuzhiyun // Copyright (C) 2018-20 Texas Instruments Incorporated - https://www.ti.com/
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
6*4882a593Smuzhiyun #include <linux/i2c.h>
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/leds.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/mutex.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_gpio.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <uapi/linux/uleds.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/led-class-multicolor.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "leds.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define LP50XX_DEV_CFG0 0x00
23*4882a593Smuzhiyun #define LP50XX_DEV_CFG1 0x01
24*4882a593Smuzhiyun #define LP50XX_LED_CFG0 0x02
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* LP5009 and LP5012 registers */
27*4882a593Smuzhiyun #define LP5012_BNK_BRT 0x03
28*4882a593Smuzhiyun #define LP5012_BNKA_CLR 0x04
29*4882a593Smuzhiyun #define LP5012_BNKB_CLR 0x05
30*4882a593Smuzhiyun #define LP5012_BNKC_CLR 0x06
31*4882a593Smuzhiyun #define LP5012_LED0_BRT 0x07
32*4882a593Smuzhiyun #define LP5012_OUT0_CLR 0x0b
33*4882a593Smuzhiyun #define LP5012_RESET 0x17
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* LP5018 and LP5024 registers */
36*4882a593Smuzhiyun #define LP5024_BNK_BRT 0x03
37*4882a593Smuzhiyun #define LP5024_BNKA_CLR 0x04
38*4882a593Smuzhiyun #define LP5024_BNKB_CLR 0x05
39*4882a593Smuzhiyun #define LP5024_BNKC_CLR 0x06
40*4882a593Smuzhiyun #define LP5024_LED0_BRT 0x07
41*4882a593Smuzhiyun #define LP5024_OUT0_CLR 0x0f
42*4882a593Smuzhiyun #define LP5024_RESET 0x27
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* LP5030 and LP5036 registers */
45*4882a593Smuzhiyun #define LP5036_LED_CFG1 0x03
46*4882a593Smuzhiyun #define LP5036_BNK_BRT 0x04
47*4882a593Smuzhiyun #define LP5036_BNKA_CLR 0x05
48*4882a593Smuzhiyun #define LP5036_BNKB_CLR 0x06
49*4882a593Smuzhiyun #define LP5036_BNKC_CLR 0x07
50*4882a593Smuzhiyun #define LP5036_LED0_BRT 0x08
51*4882a593Smuzhiyun #define LP5036_OUT0_CLR 0x14
52*4882a593Smuzhiyun #define LP5036_RESET 0x38
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define LP50XX_SW_RESET 0xff
55*4882a593Smuzhiyun #define LP50XX_CHIP_EN BIT(6)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* There are 3 LED outputs per bank */
58*4882a593Smuzhiyun #define LP50XX_LEDS_PER_MODULE 3
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define LP5009_MAX_LED_MODULES 2
61*4882a593Smuzhiyun #define LP5012_MAX_LED_MODULES 4
62*4882a593Smuzhiyun #define LP5018_MAX_LED_MODULES 6
63*4882a593Smuzhiyun #define LP5024_MAX_LED_MODULES 8
64*4882a593Smuzhiyun #define LP5030_MAX_LED_MODULES 10
65*4882a593Smuzhiyun #define LP5036_MAX_LED_MODULES 12
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const struct reg_default lp5012_reg_defs[] = {
68*4882a593Smuzhiyun {LP50XX_DEV_CFG0, 0x0},
69*4882a593Smuzhiyun {LP50XX_DEV_CFG1, 0x3c},
70*4882a593Smuzhiyun {LP50XX_LED_CFG0, 0x0},
71*4882a593Smuzhiyun {LP5012_BNK_BRT, 0xff},
72*4882a593Smuzhiyun {LP5012_BNKA_CLR, 0x0f},
73*4882a593Smuzhiyun {LP5012_BNKB_CLR, 0x0f},
74*4882a593Smuzhiyun {LP5012_BNKC_CLR, 0x0f},
75*4882a593Smuzhiyun {LP5012_LED0_BRT, 0x0f},
76*4882a593Smuzhiyun /* LEDX_BRT registers are all 0xff for defaults */
77*4882a593Smuzhiyun {0x08, 0xff}, {0x09, 0xff}, {0x0a, 0xff},
78*4882a593Smuzhiyun {LP5012_OUT0_CLR, 0x0f},
79*4882a593Smuzhiyun /* OUTX_CLR registers are all 0x0 for defaults */
80*4882a593Smuzhiyun {0x0c, 0x00}, {0x0d, 0x00}, {0x0e, 0x00}, {0x0f, 0x00}, {0x10, 0x00},
81*4882a593Smuzhiyun {0x11, 0x00}, {0x12, 0x00}, {0x13, 0x00}, {0x14, 0x00}, {0x15, 0x00},
82*4882a593Smuzhiyun {0x16, 0x00},
83*4882a593Smuzhiyun {LP5012_RESET, 0x00}
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static const struct reg_default lp5024_reg_defs[] = {
87*4882a593Smuzhiyun {LP50XX_DEV_CFG0, 0x0},
88*4882a593Smuzhiyun {LP50XX_DEV_CFG1, 0x3c},
89*4882a593Smuzhiyun {LP50XX_LED_CFG0, 0x0},
90*4882a593Smuzhiyun {LP5024_BNK_BRT, 0xff},
91*4882a593Smuzhiyun {LP5024_BNKA_CLR, 0x0f},
92*4882a593Smuzhiyun {LP5024_BNKB_CLR, 0x0f},
93*4882a593Smuzhiyun {LP5024_BNKC_CLR, 0x0f},
94*4882a593Smuzhiyun {LP5024_LED0_BRT, 0x0f},
95*4882a593Smuzhiyun /* LEDX_BRT registers are all 0xff for defaults */
96*4882a593Smuzhiyun {0x08, 0xff}, {0x09, 0xff}, {0x0a, 0xff}, {0x0b, 0xff}, {0x0c, 0xff},
97*4882a593Smuzhiyun {0x0d, 0xff}, {0x0e, 0xff},
98*4882a593Smuzhiyun {LP5024_OUT0_CLR, 0x0f},
99*4882a593Smuzhiyun /* OUTX_CLR registers are all 0x0 for defaults */
100*4882a593Smuzhiyun {0x10, 0x00}, {0x11, 0x00}, {0x12, 0x00}, {0x13, 0x00}, {0x14, 0x00},
101*4882a593Smuzhiyun {0x15, 0x00}, {0x16, 0x00}, {0x17, 0x00}, {0x18, 0x00}, {0x19, 0x00},
102*4882a593Smuzhiyun {0x1a, 0x00}, {0x1b, 0x00}, {0x1c, 0x00}, {0x1d, 0x00}, {0x1e, 0x00},
103*4882a593Smuzhiyun {0x1f, 0x00}, {0x20, 0x00}, {0x21, 0x00}, {0x22, 0x00}, {0x23, 0x00},
104*4882a593Smuzhiyun {0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00},
105*4882a593Smuzhiyun {LP5024_RESET, 0x00}
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct reg_default lp5036_reg_defs[] = {
109*4882a593Smuzhiyun {LP50XX_DEV_CFG0, 0x0},
110*4882a593Smuzhiyun {LP50XX_DEV_CFG1, 0x3c},
111*4882a593Smuzhiyun {LP50XX_LED_CFG0, 0x0},
112*4882a593Smuzhiyun {LP5036_LED_CFG1, 0x0},
113*4882a593Smuzhiyun {LP5036_BNK_BRT, 0xff},
114*4882a593Smuzhiyun {LP5036_BNKA_CLR, 0x0f},
115*4882a593Smuzhiyun {LP5036_BNKB_CLR, 0x0f},
116*4882a593Smuzhiyun {LP5036_BNKC_CLR, 0x0f},
117*4882a593Smuzhiyun {LP5036_LED0_BRT, 0x0f},
118*4882a593Smuzhiyun /* LEDX_BRT registers are all 0xff for defaults */
119*4882a593Smuzhiyun {0x08, 0xff}, {0x09, 0xff}, {0x0a, 0xff}, {0x0b, 0xff}, {0x0c, 0xff},
120*4882a593Smuzhiyun {0x0d, 0xff}, {0x0e, 0xff}, {0x0f, 0xff}, {0x10, 0xff}, {0x11, 0xff},
121*4882a593Smuzhiyun {0x12, 0xff}, {0x13, 0xff},
122*4882a593Smuzhiyun {LP5036_OUT0_CLR, 0x0f},
123*4882a593Smuzhiyun /* OUTX_CLR registers are all 0x0 for defaults */
124*4882a593Smuzhiyun {0x15, 0x00}, {0x16, 0x00}, {0x17, 0x00}, {0x18, 0x00}, {0x19, 0x00},
125*4882a593Smuzhiyun {0x1a, 0x00}, {0x1b, 0x00}, {0x1c, 0x00}, {0x1d, 0x00}, {0x1e, 0x00},
126*4882a593Smuzhiyun {0x1f, 0x00}, {0x20, 0x00}, {0x21, 0x00}, {0x22, 0x00}, {0x23, 0x00},
127*4882a593Smuzhiyun {0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00}, {0x27, 0x00}, {0x28, 0x00},
128*4882a593Smuzhiyun {0x29, 0x00}, {0x2a, 0x00}, {0x2b, 0x00}, {0x2c, 0x00}, {0x2d, 0x00},
129*4882a593Smuzhiyun {0x2e, 0x00}, {0x2f, 0x00}, {0x30, 0x00}, {0x31, 0x00}, {0x32, 0x00},
130*4882a593Smuzhiyun {0x33, 0x00}, {0x34, 0x00}, {0x35, 0x00}, {0x36, 0x00}, {0x37, 0x00},
131*4882a593Smuzhiyun {LP5036_RESET, 0x00}
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun static const struct regmap_config lp5012_regmap_config = {
135*4882a593Smuzhiyun .reg_bits = 8,
136*4882a593Smuzhiyun .val_bits = 8,
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun .max_register = LP5012_RESET,
139*4882a593Smuzhiyun .reg_defaults = lp5012_reg_defs,
140*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(lp5012_reg_defs),
141*4882a593Smuzhiyun .cache_type = REGCACHE_FLAT,
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun static const struct regmap_config lp5024_regmap_config = {
145*4882a593Smuzhiyun .reg_bits = 8,
146*4882a593Smuzhiyun .val_bits = 8,
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun .max_register = LP5024_RESET,
149*4882a593Smuzhiyun .reg_defaults = lp5024_reg_defs,
150*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(lp5024_reg_defs),
151*4882a593Smuzhiyun .cache_type = REGCACHE_FLAT,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun static const struct regmap_config lp5036_regmap_config = {
155*4882a593Smuzhiyun .reg_bits = 8,
156*4882a593Smuzhiyun .val_bits = 8,
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun .max_register = LP5036_RESET,
159*4882a593Smuzhiyun .reg_defaults = lp5036_reg_defs,
160*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(lp5036_reg_defs),
161*4882a593Smuzhiyun .cache_type = REGCACHE_FLAT,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun enum lp50xx_model {
165*4882a593Smuzhiyun LP5009,
166*4882a593Smuzhiyun LP5012,
167*4882a593Smuzhiyun LP5018,
168*4882a593Smuzhiyun LP5024,
169*4882a593Smuzhiyun LP5030,
170*4882a593Smuzhiyun LP5036,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /**
174*4882a593Smuzhiyun * struct lp50xx_chip_info -
175*4882a593Smuzhiyun * @lp50xx_regmap_config: regmap register configuration
176*4882a593Smuzhiyun * @model_id: LED device model
177*4882a593Smuzhiyun * @max_modules: total number of supported LED modules
178*4882a593Smuzhiyun * @num_leds: number of LED outputs available on the device
179*4882a593Smuzhiyun * @led_brightness0_reg: first brightness register of the device
180*4882a593Smuzhiyun * @mix_out0_reg: first color mix register of the device
181*4882a593Smuzhiyun * @bank_brt_reg: bank brightness register
182*4882a593Smuzhiyun * @bank_mix_reg: color mix register
183*4882a593Smuzhiyun * @reset_reg: device reset register
184*4882a593Smuzhiyun */
185*4882a593Smuzhiyun struct lp50xx_chip_info {
186*4882a593Smuzhiyun const struct regmap_config *lp50xx_regmap_config;
187*4882a593Smuzhiyun int model_id;
188*4882a593Smuzhiyun u8 max_modules;
189*4882a593Smuzhiyun u8 num_leds;
190*4882a593Smuzhiyun u8 led_brightness0_reg;
191*4882a593Smuzhiyun u8 mix_out0_reg;
192*4882a593Smuzhiyun u8 bank_brt_reg;
193*4882a593Smuzhiyun u8 bank_mix_reg;
194*4882a593Smuzhiyun u8 reset_reg;
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static const struct lp50xx_chip_info lp50xx_chip_info_tbl[] = {
198*4882a593Smuzhiyun [LP5009] = {
199*4882a593Smuzhiyun .model_id = LP5009,
200*4882a593Smuzhiyun .max_modules = LP5009_MAX_LED_MODULES,
201*4882a593Smuzhiyun .num_leds = LP5009_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE,
202*4882a593Smuzhiyun .led_brightness0_reg = LP5012_LED0_BRT,
203*4882a593Smuzhiyun .mix_out0_reg = LP5012_OUT0_CLR,
204*4882a593Smuzhiyun .bank_brt_reg = LP5012_BNK_BRT,
205*4882a593Smuzhiyun .bank_mix_reg = LP5012_BNKA_CLR,
206*4882a593Smuzhiyun .reset_reg = LP5012_RESET,
207*4882a593Smuzhiyun .lp50xx_regmap_config = &lp5012_regmap_config,
208*4882a593Smuzhiyun },
209*4882a593Smuzhiyun [LP5012] = {
210*4882a593Smuzhiyun .model_id = LP5012,
211*4882a593Smuzhiyun .max_modules = LP5012_MAX_LED_MODULES,
212*4882a593Smuzhiyun .num_leds = LP5012_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE,
213*4882a593Smuzhiyun .led_brightness0_reg = LP5012_LED0_BRT,
214*4882a593Smuzhiyun .mix_out0_reg = LP5012_OUT0_CLR,
215*4882a593Smuzhiyun .bank_brt_reg = LP5012_BNK_BRT,
216*4882a593Smuzhiyun .bank_mix_reg = LP5012_BNKA_CLR,
217*4882a593Smuzhiyun .reset_reg = LP5012_RESET,
218*4882a593Smuzhiyun .lp50xx_regmap_config = &lp5012_regmap_config,
219*4882a593Smuzhiyun },
220*4882a593Smuzhiyun [LP5018] = {
221*4882a593Smuzhiyun .model_id = LP5018,
222*4882a593Smuzhiyun .max_modules = LP5018_MAX_LED_MODULES,
223*4882a593Smuzhiyun .num_leds = LP5018_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE,
224*4882a593Smuzhiyun .led_brightness0_reg = LP5024_LED0_BRT,
225*4882a593Smuzhiyun .mix_out0_reg = LP5024_OUT0_CLR,
226*4882a593Smuzhiyun .bank_brt_reg = LP5024_BNK_BRT,
227*4882a593Smuzhiyun .bank_mix_reg = LP5024_BNKA_CLR,
228*4882a593Smuzhiyun .reset_reg = LP5024_RESET,
229*4882a593Smuzhiyun .lp50xx_regmap_config = &lp5024_regmap_config,
230*4882a593Smuzhiyun },
231*4882a593Smuzhiyun [LP5024] = {
232*4882a593Smuzhiyun .model_id = LP5024,
233*4882a593Smuzhiyun .max_modules = LP5024_MAX_LED_MODULES,
234*4882a593Smuzhiyun .num_leds = LP5024_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE,
235*4882a593Smuzhiyun .led_brightness0_reg = LP5024_LED0_BRT,
236*4882a593Smuzhiyun .mix_out0_reg = LP5024_OUT0_CLR,
237*4882a593Smuzhiyun .bank_brt_reg = LP5024_BNK_BRT,
238*4882a593Smuzhiyun .bank_mix_reg = LP5024_BNKA_CLR,
239*4882a593Smuzhiyun .reset_reg = LP5024_RESET,
240*4882a593Smuzhiyun .lp50xx_regmap_config = &lp5024_regmap_config,
241*4882a593Smuzhiyun },
242*4882a593Smuzhiyun [LP5030] = {
243*4882a593Smuzhiyun .model_id = LP5030,
244*4882a593Smuzhiyun .max_modules = LP5030_MAX_LED_MODULES,
245*4882a593Smuzhiyun .num_leds = LP5030_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE,
246*4882a593Smuzhiyun .led_brightness0_reg = LP5036_LED0_BRT,
247*4882a593Smuzhiyun .mix_out0_reg = LP5036_OUT0_CLR,
248*4882a593Smuzhiyun .bank_brt_reg = LP5036_BNK_BRT,
249*4882a593Smuzhiyun .bank_mix_reg = LP5036_BNKA_CLR,
250*4882a593Smuzhiyun .reset_reg = LP5036_RESET,
251*4882a593Smuzhiyun .lp50xx_regmap_config = &lp5036_regmap_config,
252*4882a593Smuzhiyun },
253*4882a593Smuzhiyun [LP5036] = {
254*4882a593Smuzhiyun .model_id = LP5036,
255*4882a593Smuzhiyun .max_modules = LP5036_MAX_LED_MODULES,
256*4882a593Smuzhiyun .num_leds = LP5036_MAX_LED_MODULES * LP50XX_LEDS_PER_MODULE,
257*4882a593Smuzhiyun .led_brightness0_reg = LP5036_LED0_BRT,
258*4882a593Smuzhiyun .mix_out0_reg = LP5036_OUT0_CLR,
259*4882a593Smuzhiyun .bank_brt_reg = LP5036_BNK_BRT,
260*4882a593Smuzhiyun .bank_mix_reg = LP5036_BNKA_CLR,
261*4882a593Smuzhiyun .reset_reg = LP5036_RESET,
262*4882a593Smuzhiyun .lp50xx_regmap_config = &lp5036_regmap_config,
263*4882a593Smuzhiyun },
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun struct lp50xx_led {
267*4882a593Smuzhiyun struct led_classdev_mc mc_cdev;
268*4882a593Smuzhiyun struct lp50xx *priv;
269*4882a593Smuzhiyun unsigned long bank_modules;
270*4882a593Smuzhiyun int led_intensity[LP50XX_LEDS_PER_MODULE];
271*4882a593Smuzhiyun u8 ctrl_bank_enabled;
272*4882a593Smuzhiyun int led_number;
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /**
276*4882a593Smuzhiyun * struct lp50xx -
277*4882a593Smuzhiyun * @enable_gpio: hardware enable gpio
278*4882a593Smuzhiyun * @regulator: LED supply regulator pointer
279*4882a593Smuzhiyun * @client: pointer to the I2C client
280*4882a593Smuzhiyun * @regmap: device register map
281*4882a593Smuzhiyun * @dev: pointer to the devices device struct
282*4882a593Smuzhiyun * @lock: lock for reading/writing the device
283*4882a593Smuzhiyun * @chip_info: chip specific information (ie num_leds)
284*4882a593Smuzhiyun * @num_of_banked_leds: holds the number of banked LEDs
285*4882a593Smuzhiyun * @leds: array of LED strings
286*4882a593Smuzhiyun */
287*4882a593Smuzhiyun struct lp50xx {
288*4882a593Smuzhiyun struct gpio_desc *enable_gpio;
289*4882a593Smuzhiyun struct regulator *regulator;
290*4882a593Smuzhiyun struct i2c_client *client;
291*4882a593Smuzhiyun struct regmap *regmap;
292*4882a593Smuzhiyun struct device *dev;
293*4882a593Smuzhiyun struct mutex lock;
294*4882a593Smuzhiyun const struct lp50xx_chip_info *chip_info;
295*4882a593Smuzhiyun int num_of_banked_leds;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /* This needs to be at the end of the struct */
298*4882a593Smuzhiyun struct lp50xx_led leds[];
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun
mcled_cdev_to_led(struct led_classdev_mc * mc_cdev)301*4882a593Smuzhiyun static struct lp50xx_led *mcled_cdev_to_led(struct led_classdev_mc *mc_cdev)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun return container_of(mc_cdev, struct lp50xx_led, mc_cdev);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
lp50xx_brightness_set(struct led_classdev * cdev,enum led_brightness brightness)306*4882a593Smuzhiyun static int lp50xx_brightness_set(struct led_classdev *cdev,
307*4882a593Smuzhiyun enum led_brightness brightness)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun struct led_classdev_mc *mc_dev = lcdev_to_mccdev(cdev);
310*4882a593Smuzhiyun struct lp50xx_led *led = mcled_cdev_to_led(mc_dev);
311*4882a593Smuzhiyun const struct lp50xx_chip_info *led_chip = led->priv->chip_info;
312*4882a593Smuzhiyun u8 led_offset, reg_val;
313*4882a593Smuzhiyun int ret = 0;
314*4882a593Smuzhiyun int i;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun mutex_lock(&led->priv->lock);
317*4882a593Smuzhiyun if (led->ctrl_bank_enabled)
318*4882a593Smuzhiyun reg_val = led_chip->bank_brt_reg;
319*4882a593Smuzhiyun else
320*4882a593Smuzhiyun reg_val = led_chip->led_brightness0_reg +
321*4882a593Smuzhiyun led->led_number;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun ret = regmap_write(led->priv->regmap, reg_val, brightness);
324*4882a593Smuzhiyun if (ret) {
325*4882a593Smuzhiyun dev_err(&led->priv->client->dev,
326*4882a593Smuzhiyun "Cannot write brightness value %d\n", ret);
327*4882a593Smuzhiyun goto out;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun for (i = 0; i < led->mc_cdev.num_colors; i++) {
331*4882a593Smuzhiyun if (led->ctrl_bank_enabled) {
332*4882a593Smuzhiyun reg_val = led_chip->bank_mix_reg + i;
333*4882a593Smuzhiyun } else {
334*4882a593Smuzhiyun led_offset = (led->led_number * 3) + i;
335*4882a593Smuzhiyun reg_val = led_chip->mix_out0_reg + led_offset;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun ret = regmap_write(led->priv->regmap, reg_val,
339*4882a593Smuzhiyun mc_dev->subled_info[i].intensity);
340*4882a593Smuzhiyun if (ret) {
341*4882a593Smuzhiyun dev_err(&led->priv->client->dev,
342*4882a593Smuzhiyun "Cannot write intensity value %d\n", ret);
343*4882a593Smuzhiyun goto out;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun out:
347*4882a593Smuzhiyun mutex_unlock(&led->priv->lock);
348*4882a593Smuzhiyun return ret;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
lp50xx_set_banks(struct lp50xx * priv,u32 led_banks[])351*4882a593Smuzhiyun static int lp50xx_set_banks(struct lp50xx *priv, u32 led_banks[])
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun u8 led_config_lo, led_config_hi;
354*4882a593Smuzhiyun u32 bank_enable_mask = 0;
355*4882a593Smuzhiyun int ret;
356*4882a593Smuzhiyun int i;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun for (i = 0; i < priv->chip_info->max_modules; i++) {
359*4882a593Smuzhiyun if (led_banks[i])
360*4882a593Smuzhiyun bank_enable_mask |= (1 << led_banks[i]);
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun led_config_lo = (u8)(bank_enable_mask & 0xff);
364*4882a593Smuzhiyun led_config_hi = (u8)(bank_enable_mask >> 8) & 0xff;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun ret = regmap_write(priv->regmap, LP50XX_LED_CFG0, led_config_lo);
367*4882a593Smuzhiyun if (ret)
368*4882a593Smuzhiyun return ret;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (priv->chip_info->model_id >= LP5030)
371*4882a593Smuzhiyun ret = regmap_write(priv->regmap, LP5036_LED_CFG1, led_config_hi);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun return ret;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
lp50xx_reset(struct lp50xx * priv)376*4882a593Smuzhiyun static int lp50xx_reset(struct lp50xx *priv)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun return regmap_write(priv->regmap, priv->chip_info->reset_reg, LP50XX_SW_RESET);
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
lp50xx_enable_disable(struct lp50xx * priv,int enable_disable)381*4882a593Smuzhiyun static int lp50xx_enable_disable(struct lp50xx *priv, int enable_disable)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun int ret;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun if (priv->enable_gpio) {
386*4882a593Smuzhiyun ret = gpiod_direction_output(priv->enable_gpio, enable_disable);
387*4882a593Smuzhiyun if (ret)
388*4882a593Smuzhiyun return ret;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun if (enable_disable)
392*4882a593Smuzhiyun return regmap_write(priv->regmap, LP50XX_DEV_CFG0, LP50XX_CHIP_EN);
393*4882a593Smuzhiyun else
394*4882a593Smuzhiyun return regmap_write(priv->regmap, LP50XX_DEV_CFG0, 0);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
lp50xx_probe_leds(struct fwnode_handle * child,struct lp50xx * priv,struct lp50xx_led * led,int num_leds)398*4882a593Smuzhiyun static int lp50xx_probe_leds(struct fwnode_handle *child, struct lp50xx *priv,
399*4882a593Smuzhiyun struct lp50xx_led *led, int num_leds)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun u32 led_banks[LP5036_MAX_LED_MODULES] = {0};
402*4882a593Smuzhiyun int led_number;
403*4882a593Smuzhiyun int ret;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun if (num_leds > 1) {
406*4882a593Smuzhiyun if (num_leds > priv->chip_info->max_modules) {
407*4882a593Smuzhiyun dev_err(&priv->client->dev, "reg property is invalid\n");
408*4882a593Smuzhiyun return -EINVAL;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun priv->num_of_banked_leds = num_leds;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun ret = fwnode_property_read_u32_array(child, "reg", led_banks, num_leds);
414*4882a593Smuzhiyun if (ret) {
415*4882a593Smuzhiyun dev_err(&priv->client->dev, "reg property is missing\n");
416*4882a593Smuzhiyun return ret;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun ret = lp50xx_set_banks(priv, led_banks);
420*4882a593Smuzhiyun if (ret) {
421*4882a593Smuzhiyun dev_err(&priv->client->dev, "Cannot setup banked LEDs\n");
422*4882a593Smuzhiyun return ret;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun led->ctrl_bank_enabled = 1;
426*4882a593Smuzhiyun } else {
427*4882a593Smuzhiyun ret = fwnode_property_read_u32(child, "reg", &led_number);
428*4882a593Smuzhiyun if (ret) {
429*4882a593Smuzhiyun dev_err(&priv->client->dev, "led reg property missing\n");
430*4882a593Smuzhiyun return ret;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (led_number > priv->chip_info->num_leds) {
434*4882a593Smuzhiyun dev_err(&priv->client->dev, "led-sources property is invalid\n");
435*4882a593Smuzhiyun return -EINVAL;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun led->led_number = led_number;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun return 0;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
lp50xx_probe_dt(struct lp50xx * priv)444*4882a593Smuzhiyun static int lp50xx_probe_dt(struct lp50xx *priv)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun struct fwnode_handle *child = NULL;
447*4882a593Smuzhiyun struct fwnode_handle *led_node = NULL;
448*4882a593Smuzhiyun struct led_init_data init_data = {};
449*4882a593Smuzhiyun struct led_classdev *led_cdev;
450*4882a593Smuzhiyun struct mc_subled *mc_led_info;
451*4882a593Smuzhiyun struct lp50xx_led *led;
452*4882a593Smuzhiyun int ret = -EINVAL;
453*4882a593Smuzhiyun int num_colors;
454*4882a593Smuzhiyun u32 color_id;
455*4882a593Smuzhiyun int i = 0;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun priv->enable_gpio = devm_gpiod_get_optional(priv->dev, "enable", GPIOD_OUT_LOW);
458*4882a593Smuzhiyun if (IS_ERR(priv->enable_gpio)) {
459*4882a593Smuzhiyun ret = PTR_ERR(priv->enable_gpio);
460*4882a593Smuzhiyun dev_err(&priv->client->dev, "Failed to get enable gpio: %d\n",
461*4882a593Smuzhiyun ret);
462*4882a593Smuzhiyun return ret;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun priv->regulator = devm_regulator_get(priv->dev, "vled");
466*4882a593Smuzhiyun if (IS_ERR(priv->regulator))
467*4882a593Smuzhiyun priv->regulator = NULL;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun device_for_each_child_node(priv->dev, child) {
470*4882a593Smuzhiyun led = &priv->leds[i];
471*4882a593Smuzhiyun ret = fwnode_property_count_u32(child, "reg");
472*4882a593Smuzhiyun if (ret < 0) {
473*4882a593Smuzhiyun dev_err(&priv->client->dev, "reg property is invalid\n");
474*4882a593Smuzhiyun goto child_out;
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun ret = lp50xx_probe_leds(child, priv, led, ret);
478*4882a593Smuzhiyun if (ret)
479*4882a593Smuzhiyun goto child_out;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun init_data.fwnode = child;
482*4882a593Smuzhiyun num_colors = 0;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun /*
485*4882a593Smuzhiyun * There are only 3 LEDs per module otherwise they should be
486*4882a593Smuzhiyun * banked which also is presented as 3 LEDs.
487*4882a593Smuzhiyun */
488*4882a593Smuzhiyun mc_led_info = devm_kcalloc(priv->dev, LP50XX_LEDS_PER_MODULE,
489*4882a593Smuzhiyun sizeof(*mc_led_info), GFP_KERNEL);
490*4882a593Smuzhiyun if (!mc_led_info) {
491*4882a593Smuzhiyun ret = -ENOMEM;
492*4882a593Smuzhiyun goto child_out;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun fwnode_for_each_child_node(child, led_node) {
496*4882a593Smuzhiyun ret = fwnode_property_read_u32(led_node, "color",
497*4882a593Smuzhiyun &color_id);
498*4882a593Smuzhiyun if (ret) {
499*4882a593Smuzhiyun fwnode_handle_put(led_node);
500*4882a593Smuzhiyun dev_err(priv->dev, "Cannot read color\n");
501*4882a593Smuzhiyun goto child_out;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun mc_led_info[num_colors].color_index = color_id;
505*4882a593Smuzhiyun num_colors++;
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun led->priv = priv;
509*4882a593Smuzhiyun led->mc_cdev.num_colors = num_colors;
510*4882a593Smuzhiyun led->mc_cdev.subled_info = mc_led_info;
511*4882a593Smuzhiyun led_cdev = &led->mc_cdev.led_cdev;
512*4882a593Smuzhiyun led_cdev->brightness_set_blocking = lp50xx_brightness_set;
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun ret = devm_led_classdev_multicolor_register_ext(&priv->client->dev,
515*4882a593Smuzhiyun &led->mc_cdev,
516*4882a593Smuzhiyun &init_data);
517*4882a593Smuzhiyun if (ret) {
518*4882a593Smuzhiyun dev_err(&priv->client->dev, "led register err: %d\n",
519*4882a593Smuzhiyun ret);
520*4882a593Smuzhiyun goto child_out;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun i++;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun return 0;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun child_out:
528*4882a593Smuzhiyun fwnode_handle_put(child);
529*4882a593Smuzhiyun return ret;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun
lp50xx_probe(struct i2c_client * client,const struct i2c_device_id * id)532*4882a593Smuzhiyun static int lp50xx_probe(struct i2c_client *client,
533*4882a593Smuzhiyun const struct i2c_device_id *id)
534*4882a593Smuzhiyun {
535*4882a593Smuzhiyun struct lp50xx *led;
536*4882a593Smuzhiyun int count;
537*4882a593Smuzhiyun int ret;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun count = device_get_child_node_count(&client->dev);
540*4882a593Smuzhiyun if (!count) {
541*4882a593Smuzhiyun dev_err(&client->dev, "LEDs are not defined in device tree!");
542*4882a593Smuzhiyun return -ENODEV;
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun led = devm_kzalloc(&client->dev, struct_size(led, leds, count),
546*4882a593Smuzhiyun GFP_KERNEL);
547*4882a593Smuzhiyun if (!led)
548*4882a593Smuzhiyun return -ENOMEM;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun mutex_init(&led->lock);
551*4882a593Smuzhiyun led->client = client;
552*4882a593Smuzhiyun led->dev = &client->dev;
553*4882a593Smuzhiyun led->chip_info = &lp50xx_chip_info_tbl[id->driver_data];
554*4882a593Smuzhiyun i2c_set_clientdata(client, led);
555*4882a593Smuzhiyun led->regmap = devm_regmap_init_i2c(client,
556*4882a593Smuzhiyun led->chip_info->lp50xx_regmap_config);
557*4882a593Smuzhiyun if (IS_ERR(led->regmap)) {
558*4882a593Smuzhiyun ret = PTR_ERR(led->regmap);
559*4882a593Smuzhiyun dev_err(&client->dev, "Failed to allocate register map: %d\n",
560*4882a593Smuzhiyun ret);
561*4882a593Smuzhiyun return ret;
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun ret = lp50xx_reset(led);
565*4882a593Smuzhiyun if (ret)
566*4882a593Smuzhiyun return ret;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun ret = lp50xx_enable_disable(led, 1);
569*4882a593Smuzhiyun if (ret)
570*4882a593Smuzhiyun return ret;
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun return lp50xx_probe_dt(led);
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun
lp50xx_remove(struct i2c_client * client)575*4882a593Smuzhiyun static int lp50xx_remove(struct i2c_client *client)
576*4882a593Smuzhiyun {
577*4882a593Smuzhiyun struct lp50xx *led = i2c_get_clientdata(client);
578*4882a593Smuzhiyun int ret;
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun ret = lp50xx_enable_disable(led, 0);
581*4882a593Smuzhiyun if (ret) {
582*4882a593Smuzhiyun dev_err(&led->client->dev, "Failed to disable chip\n");
583*4882a593Smuzhiyun return ret;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun if (led->regulator) {
587*4882a593Smuzhiyun ret = regulator_disable(led->regulator);
588*4882a593Smuzhiyun if (ret)
589*4882a593Smuzhiyun dev_err(&led->client->dev,
590*4882a593Smuzhiyun "Failed to disable regulator\n");
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun mutex_destroy(&led->lock);
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun return 0;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun static const struct i2c_device_id lp50xx_id[] = {
599*4882a593Smuzhiyun { "lp5009", LP5009 },
600*4882a593Smuzhiyun { "lp5012", LP5012 },
601*4882a593Smuzhiyun { "lp5018", LP5018 },
602*4882a593Smuzhiyun { "lp5024", LP5024 },
603*4882a593Smuzhiyun { "lp5030", LP5030 },
604*4882a593Smuzhiyun { "lp5036", LP5036 },
605*4882a593Smuzhiyun { }
606*4882a593Smuzhiyun };
607*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, lp50xx_id);
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun static const struct of_device_id of_lp50xx_leds_match[] = {
610*4882a593Smuzhiyun { .compatible = "ti,lp5009", .data = (void *)LP5009 },
611*4882a593Smuzhiyun { .compatible = "ti,lp5012", .data = (void *)LP5012 },
612*4882a593Smuzhiyun { .compatible = "ti,lp5018", .data = (void *)LP5018 },
613*4882a593Smuzhiyun { .compatible = "ti,lp5024", .data = (void *)LP5024 },
614*4882a593Smuzhiyun { .compatible = "ti,lp5030", .data = (void *)LP5030 },
615*4882a593Smuzhiyun { .compatible = "ti,lp5036", .data = (void *)LP5036 },
616*4882a593Smuzhiyun {},
617*4882a593Smuzhiyun };
618*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_lp50xx_leds_match);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun static struct i2c_driver lp50xx_driver = {
621*4882a593Smuzhiyun .driver = {
622*4882a593Smuzhiyun .name = "lp50xx",
623*4882a593Smuzhiyun .of_match_table = of_lp50xx_leds_match,
624*4882a593Smuzhiyun },
625*4882a593Smuzhiyun .probe = lp50xx_probe,
626*4882a593Smuzhiyun .remove = lp50xx_remove,
627*4882a593Smuzhiyun .id_table = lp50xx_id,
628*4882a593Smuzhiyun };
629*4882a593Smuzhiyun module_i2c_driver(lp50xx_driver);
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun MODULE_DESCRIPTION("Texas Instruments LP50XX LED driver");
632*4882a593Smuzhiyun MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
633*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
634