1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Winbond W6692 specific defines 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author Karsten Keil <keil@isdn4linux.de> 6*4882a593Smuzhiyun * based on the w6692 I4L driver from Petr Novak <petr.novak@i.cz> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Specifications of W6692 registers */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define W_D_RFIFO 0x00 /* R */ 14*4882a593Smuzhiyun #define W_D_XFIFO 0x04 /* W */ 15*4882a593Smuzhiyun #define W_D_CMDR 0x08 /* W */ 16*4882a593Smuzhiyun #define W_D_MODE 0x0c /* R/W */ 17*4882a593Smuzhiyun #define W_D_TIMR 0x10 /* R/W */ 18*4882a593Smuzhiyun #define W_ISTA 0x14 /* R_clr */ 19*4882a593Smuzhiyun #define W_IMASK 0x18 /* R/W */ 20*4882a593Smuzhiyun #define W_D_EXIR 0x1c /* R_clr */ 21*4882a593Smuzhiyun #define W_D_EXIM 0x20 /* R/W */ 22*4882a593Smuzhiyun #define W_D_STAR 0x24 /* R */ 23*4882a593Smuzhiyun #define W_D_RSTA 0x28 /* R */ 24*4882a593Smuzhiyun #define W_D_SAM 0x2c /* R/W */ 25*4882a593Smuzhiyun #define W_D_SAP1 0x30 /* R/W */ 26*4882a593Smuzhiyun #define W_D_SAP2 0x34 /* R/W */ 27*4882a593Smuzhiyun #define W_D_TAM 0x38 /* R/W */ 28*4882a593Smuzhiyun #define W_D_TEI1 0x3c /* R/W */ 29*4882a593Smuzhiyun #define W_D_TEI2 0x40 /* R/W */ 30*4882a593Smuzhiyun #define W_D_RBCH 0x44 /* R */ 31*4882a593Smuzhiyun #define W_D_RBCL 0x48 /* R */ 32*4882a593Smuzhiyun #define W_TIMR2 0x4c /* W */ 33*4882a593Smuzhiyun #define W_L1_RC 0x50 /* R/W */ 34*4882a593Smuzhiyun #define W_D_CTL 0x54 /* R/W */ 35*4882a593Smuzhiyun #define W_CIR 0x58 /* R */ 36*4882a593Smuzhiyun #define W_CIX 0x5c /* W */ 37*4882a593Smuzhiyun #define W_SQR 0x60 /* R */ 38*4882a593Smuzhiyun #define W_SQX 0x64 /* W */ 39*4882a593Smuzhiyun #define W_PCTL 0x68 /* R/W */ 40*4882a593Smuzhiyun #define W_MOR 0x6c /* R */ 41*4882a593Smuzhiyun #define W_MOX 0x70 /* R/W */ 42*4882a593Smuzhiyun #define W_MOSR 0x74 /* R_clr */ 43*4882a593Smuzhiyun #define W_MOCR 0x78 /* R/W */ 44*4882a593Smuzhiyun #define W_GCR 0x7c /* R/W */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define W_B_RFIFO 0x80 /* R */ 47*4882a593Smuzhiyun #define W_B_XFIFO 0x84 /* W */ 48*4882a593Smuzhiyun #define W_B_CMDR 0x88 /* W */ 49*4882a593Smuzhiyun #define W_B_MODE 0x8c /* R/W */ 50*4882a593Smuzhiyun #define W_B_EXIR 0x90 /* R_clr */ 51*4882a593Smuzhiyun #define W_B_EXIM 0x94 /* R/W */ 52*4882a593Smuzhiyun #define W_B_STAR 0x98 /* R */ 53*4882a593Smuzhiyun #define W_B_ADM1 0x9c /* R/W */ 54*4882a593Smuzhiyun #define W_B_ADM2 0xa0 /* R/W */ 55*4882a593Smuzhiyun #define W_B_ADR1 0xa4 /* R/W */ 56*4882a593Smuzhiyun #define W_B_ADR2 0xa8 /* R/W */ 57*4882a593Smuzhiyun #define W_B_RBCL 0xac /* R */ 58*4882a593Smuzhiyun #define W_B_RBCH 0xb0 /* R */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define W_XADDR 0xf4 /* R/W */ 61*4882a593Smuzhiyun #define W_XDATA 0xf8 /* R/W */ 62*4882a593Smuzhiyun #define W_EPCTL 0xfc /* W */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* W6692 register bits */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define W_D_CMDR_XRST 0x01 67*4882a593Smuzhiyun #define W_D_CMDR_XME 0x02 68*4882a593Smuzhiyun #define W_D_CMDR_XMS 0x08 69*4882a593Smuzhiyun #define W_D_CMDR_STT 0x10 70*4882a593Smuzhiyun #define W_D_CMDR_RRST 0x40 71*4882a593Smuzhiyun #define W_D_CMDR_RACK 0x80 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define W_D_MODE_RLP 0x01 74*4882a593Smuzhiyun #define W_D_MODE_DLP 0x02 75*4882a593Smuzhiyun #define W_D_MODE_MFD 0x04 76*4882a593Smuzhiyun #define W_D_MODE_TEE 0x08 77*4882a593Smuzhiyun #define W_D_MODE_TMS 0x10 78*4882a593Smuzhiyun #define W_D_MODE_RACT 0x40 79*4882a593Smuzhiyun #define W_D_MODE_MMS 0x80 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define W_INT_B2_EXI 0x01 82*4882a593Smuzhiyun #define W_INT_B1_EXI 0x02 83*4882a593Smuzhiyun #define W_INT_D_EXI 0x04 84*4882a593Smuzhiyun #define W_INT_XINT0 0x08 85*4882a593Smuzhiyun #define W_INT_XINT1 0x10 86*4882a593Smuzhiyun #define W_INT_D_XFR 0x20 87*4882a593Smuzhiyun #define W_INT_D_RME 0x40 88*4882a593Smuzhiyun #define W_INT_D_RMR 0x80 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define W_D_EXI_WEXP 0x01 91*4882a593Smuzhiyun #define W_D_EXI_TEXP 0x02 92*4882a593Smuzhiyun #define W_D_EXI_ISC 0x04 93*4882a593Smuzhiyun #define W_D_EXI_MOC 0x08 94*4882a593Smuzhiyun #define W_D_EXI_TIN2 0x10 95*4882a593Smuzhiyun #define W_D_EXI_XCOL 0x20 96*4882a593Smuzhiyun #define W_D_EXI_XDUN 0x40 97*4882a593Smuzhiyun #define W_D_EXI_RDOV 0x80 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define W_D_STAR_DRDY 0x10 100*4882a593Smuzhiyun #define W_D_STAR_XBZ 0x20 101*4882a593Smuzhiyun #define W_D_STAR_XDOW 0x80 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define W_D_RSTA_RMB 0x10 104*4882a593Smuzhiyun #define W_D_RSTA_CRCE 0x20 105*4882a593Smuzhiyun #define W_D_RSTA_RDOV 0x40 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define W_D_CTL_SRST 0x20 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define W_CIR_SCC 0x80 110*4882a593Smuzhiyun #define W_CIR_ICC 0x40 111*4882a593Smuzhiyun #define W_CIR_COD_MASK 0x0f 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define W_PCTL_PCX 0x01 114*4882a593Smuzhiyun #define W_PCTL_XMODE 0x02 115*4882a593Smuzhiyun #define W_PCTL_OE0 0x04 116*4882a593Smuzhiyun #define W_PCTL_OE1 0x08 117*4882a593Smuzhiyun #define W_PCTL_OE2 0x10 118*4882a593Smuzhiyun #define W_PCTL_OE3 0x20 119*4882a593Smuzhiyun #define W_PCTL_OE4 0x40 120*4882a593Smuzhiyun #define W_PCTL_OE5 0x80 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define W_B_CMDR_XRST 0x01 123*4882a593Smuzhiyun #define W_B_CMDR_XME 0x02 124*4882a593Smuzhiyun #define W_B_CMDR_XMS 0x04 125*4882a593Smuzhiyun #define W_B_CMDR_RACT 0x20 126*4882a593Smuzhiyun #define W_B_CMDR_RRST 0x40 127*4882a593Smuzhiyun #define W_B_CMDR_RACK 0x80 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define W_B_MODE_FTS0 0x01 130*4882a593Smuzhiyun #define W_B_MODE_FTS1 0x02 131*4882a593Smuzhiyun #define W_B_MODE_SW56 0x04 132*4882a593Smuzhiyun #define W_B_MODE_BSW0 0x08 133*4882a593Smuzhiyun #define W_B_MODE_BSW1 0x10 134*4882a593Smuzhiyun #define W_B_MODE_EPCM 0x20 135*4882a593Smuzhiyun #define W_B_MODE_ITF 0x40 136*4882a593Smuzhiyun #define W_B_MODE_MMS 0x80 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define W_B_EXI_XDUN 0x01 139*4882a593Smuzhiyun #define W_B_EXI_XFR 0x02 140*4882a593Smuzhiyun #define W_B_EXI_RDOV 0x10 141*4882a593Smuzhiyun #define W_B_EXI_RME 0x20 142*4882a593Smuzhiyun #define W_B_EXI_RMR 0x40 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define W_B_STAR_XBZ 0x01 145*4882a593Smuzhiyun #define W_B_STAR_XDOW 0x04 146*4882a593Smuzhiyun #define W_B_STAR_RMB 0x10 147*4882a593Smuzhiyun #define W_B_STAR_CRCE 0x20 148*4882a593Smuzhiyun #define W_B_STAR_RDOV 0x40 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define W_B_RBCH_LOV 0x20 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* W6692 Layer1 commands */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define W_L1CMD_ECK 0x00 155*4882a593Smuzhiyun #define W_L1CMD_RST 0x01 156*4882a593Smuzhiyun #define W_L1CMD_SCP 0x04 157*4882a593Smuzhiyun #define W_L1CMD_SSP 0x02 158*4882a593Smuzhiyun #define W_L1CMD_AR8 0x08 159*4882a593Smuzhiyun #define W_L1CMD_AR10 0x09 160*4882a593Smuzhiyun #define W_L1CMD_EAL 0x0a 161*4882a593Smuzhiyun #define W_L1CMD_DRC 0x0f 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* W6692 Layer1 indications */ 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define W_L1IND_CE 0x07 166*4882a593Smuzhiyun #define W_L1IND_DRD 0x00 167*4882a593Smuzhiyun #define W_L1IND_LD 0x04 168*4882a593Smuzhiyun #define W_L1IND_ARD 0x08 169*4882a593Smuzhiyun #define W_L1IND_TI 0x0a 170*4882a593Smuzhiyun #define W_L1IND_ATI 0x0b 171*4882a593Smuzhiyun #define W_L1IND_AI8 0x0c 172*4882a593Smuzhiyun #define W_L1IND_AI10 0x0d 173*4882a593Smuzhiyun #define W_L1IND_CD 0x0f 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* FIFO thresholds */ 176*4882a593Smuzhiyun #define W_D_FIFO_THRESH 64 177*4882a593Smuzhiyun #define W_B_FIFO_THRESH 64 178