xref: /OK3568_Linux_fs/kernel/drivers/isdn/hardware/mISDN/w6692.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * w6692.c     mISDN driver for Winbond w6692 based cards
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author      Karsten Keil <kkeil@suse.de>
6*4882a593Smuzhiyun  *             based on the w6692 I4L driver from Petr Novak <petr.novak@i.cz>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright 2009  by Karsten Keil <keil@isdn4linux.de>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/pci.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/mISDNhw.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include "w6692.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define W6692_REV	"2.0"
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define DBUSY_TIMER_VALUE	80
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun enum {
24*4882a593Smuzhiyun 	W6692_ASUS,
25*4882a593Smuzhiyun 	W6692_WINBOND,
26*4882a593Smuzhiyun 	W6692_USR
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* private data in the PCI devices list */
30*4882a593Smuzhiyun struct w6692map {
31*4882a593Smuzhiyun 	u_int	subtype;
32*4882a593Smuzhiyun 	char	*name;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun static const struct w6692map  w6692_map[] =
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun 	{W6692_ASUS, "Dynalink/AsusCom IS64PH"},
38*4882a593Smuzhiyun 	{W6692_WINBOND, "Winbond W6692"},
39*4882a593Smuzhiyun 	{W6692_USR, "USR W6692"}
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define PCI_DEVICE_ID_USR_6692	0x3409
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun struct w6692_ch {
45*4882a593Smuzhiyun 	struct bchannel		bch;
46*4882a593Smuzhiyun 	u32			addr;
47*4882a593Smuzhiyun 	struct timer_list	timer;
48*4882a593Smuzhiyun 	u8			b_mode;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun struct w6692_hw {
52*4882a593Smuzhiyun 	struct list_head	list;
53*4882a593Smuzhiyun 	struct pci_dev		*pdev;
54*4882a593Smuzhiyun 	char			name[MISDN_MAX_IDLEN];
55*4882a593Smuzhiyun 	u32			irq;
56*4882a593Smuzhiyun 	u32			irqcnt;
57*4882a593Smuzhiyun 	u32			addr;
58*4882a593Smuzhiyun 	u32			fmask;	/* feature mask - bit set per card nr */
59*4882a593Smuzhiyun 	int			subtype;
60*4882a593Smuzhiyun 	spinlock_t		lock;	/* hw lock */
61*4882a593Smuzhiyun 	u8			imask;
62*4882a593Smuzhiyun 	u8			pctl;
63*4882a593Smuzhiyun 	u8			xaddr;
64*4882a593Smuzhiyun 	u8			xdata;
65*4882a593Smuzhiyun 	u8			state;
66*4882a593Smuzhiyun 	struct w6692_ch		bc[2];
67*4882a593Smuzhiyun 	struct dchannel		dch;
68*4882a593Smuzhiyun 	char			log[64];
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun static LIST_HEAD(Cards);
72*4882a593Smuzhiyun static DEFINE_RWLOCK(card_lock); /* protect Cards */
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun static int w6692_cnt;
75*4882a593Smuzhiyun static int debug;
76*4882a593Smuzhiyun static u32 led;
77*4882a593Smuzhiyun static u32 pots;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun static void
_set_debug(struct w6692_hw * card)80*4882a593Smuzhiyun _set_debug(struct w6692_hw *card)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun 	card->dch.debug = debug;
83*4882a593Smuzhiyun 	card->bc[0].bch.debug = debug;
84*4882a593Smuzhiyun 	card->bc[1].bch.debug = debug;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun static int
set_debug(const char * val,const struct kernel_param * kp)88*4882a593Smuzhiyun set_debug(const char *val, const struct kernel_param *kp)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	int ret;
91*4882a593Smuzhiyun 	struct w6692_hw *card;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	ret = param_set_uint(val, kp);
94*4882a593Smuzhiyun 	if (!ret) {
95*4882a593Smuzhiyun 		read_lock(&card_lock);
96*4882a593Smuzhiyun 		list_for_each_entry(card, &Cards, list)
97*4882a593Smuzhiyun 			_set_debug(card);
98*4882a593Smuzhiyun 		read_unlock(&card_lock);
99*4882a593Smuzhiyun 	}
100*4882a593Smuzhiyun 	return ret;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun MODULE_AUTHOR("Karsten Keil");
104*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
105*4882a593Smuzhiyun MODULE_VERSION(W6692_REV);
106*4882a593Smuzhiyun module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
107*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "W6692 debug mask");
108*4882a593Smuzhiyun module_param(led, uint, S_IRUGO | S_IWUSR);
109*4882a593Smuzhiyun MODULE_PARM_DESC(led, "W6692 LED support bitmask (one bit per card)");
110*4882a593Smuzhiyun module_param(pots, uint, S_IRUGO | S_IWUSR);
111*4882a593Smuzhiyun MODULE_PARM_DESC(pots, "W6692 POTS support bitmask (one bit per card)");
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static inline u8
ReadW6692(struct w6692_hw * card,u8 offset)114*4882a593Smuzhiyun ReadW6692(struct w6692_hw *card, u8 offset)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	return inb(card->addr + offset);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun static inline void
WriteW6692(struct w6692_hw * card,u8 offset,u8 value)120*4882a593Smuzhiyun WriteW6692(struct w6692_hw *card, u8 offset, u8 value)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	outb(value, card->addr + offset);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun static inline u8
ReadW6692B(struct w6692_ch * bc,u8 offset)126*4882a593Smuzhiyun ReadW6692B(struct w6692_ch *bc, u8 offset)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	return inb(bc->addr + offset);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun static inline void
WriteW6692B(struct w6692_ch * bc,u8 offset,u8 value)132*4882a593Smuzhiyun WriteW6692B(struct w6692_ch *bc, u8 offset, u8 value)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	outb(value, bc->addr + offset);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static void
enable_hwirq(struct w6692_hw * card)138*4882a593Smuzhiyun enable_hwirq(struct w6692_hw *card)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	WriteW6692(card, W_IMASK, card->imask);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static void
disable_hwirq(struct w6692_hw * card)144*4882a593Smuzhiyun disable_hwirq(struct w6692_hw *card)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	WriteW6692(card, W_IMASK, 0xff);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun static const char *W6692Ver[] = {"V00", "V01", "V10", "V11"};
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun static void
W6692Version(struct w6692_hw * card)152*4882a593Smuzhiyun W6692Version(struct w6692_hw *card)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	int val;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	val = ReadW6692(card, W_D_RBCH);
157*4882a593Smuzhiyun 	pr_notice("%s: Winbond W6692 version: %s\n", card->name,
158*4882a593Smuzhiyun 		  W6692Ver[(val >> 6) & 3]);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun static void
w6692_led_handler(struct w6692_hw * card,int on)162*4882a593Smuzhiyun w6692_led_handler(struct w6692_hw *card, int on)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	if ((!(card->fmask & led)) || card->subtype == W6692_USR)
165*4882a593Smuzhiyun 		return;
166*4882a593Smuzhiyun 	if (on) {
167*4882a593Smuzhiyun 		card->xdata &= 0xfb;	/*  LED ON */
168*4882a593Smuzhiyun 		WriteW6692(card, W_XDATA, card->xdata);
169*4882a593Smuzhiyun 	} else {
170*4882a593Smuzhiyun 		card->xdata |= 0x04;	/*  LED OFF */
171*4882a593Smuzhiyun 		WriteW6692(card, W_XDATA, card->xdata);
172*4882a593Smuzhiyun 	}
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun static void
ph_command(struct w6692_hw * card,u8 cmd)176*4882a593Smuzhiyun ph_command(struct w6692_hw *card, u8 cmd)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	pr_debug("%s: ph_command %x\n", card->name, cmd);
179*4882a593Smuzhiyun 	WriteW6692(card, W_CIX, cmd);
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static void
W6692_new_ph(struct w6692_hw * card)183*4882a593Smuzhiyun W6692_new_ph(struct w6692_hw *card)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	if (card->state == W_L1CMD_RST)
186*4882a593Smuzhiyun 		ph_command(card, W_L1CMD_DRC);
187*4882a593Smuzhiyun 	schedule_event(&card->dch, FLG_PHCHANGE);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static void
W6692_ph_bh(struct dchannel * dch)191*4882a593Smuzhiyun W6692_ph_bh(struct dchannel *dch)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	struct w6692_hw *card = dch->hw;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	switch (card->state) {
196*4882a593Smuzhiyun 	case W_L1CMD_RST:
197*4882a593Smuzhiyun 		dch->state = 0;
198*4882a593Smuzhiyun 		l1_event(dch->l1, HW_RESET_IND);
199*4882a593Smuzhiyun 		break;
200*4882a593Smuzhiyun 	case W_L1IND_CD:
201*4882a593Smuzhiyun 		dch->state = 3;
202*4882a593Smuzhiyun 		l1_event(dch->l1, HW_DEACT_CNF);
203*4882a593Smuzhiyun 		break;
204*4882a593Smuzhiyun 	case W_L1IND_DRD:
205*4882a593Smuzhiyun 		dch->state = 3;
206*4882a593Smuzhiyun 		l1_event(dch->l1, HW_DEACT_IND);
207*4882a593Smuzhiyun 		break;
208*4882a593Smuzhiyun 	case W_L1IND_CE:
209*4882a593Smuzhiyun 		dch->state = 4;
210*4882a593Smuzhiyun 		l1_event(dch->l1, HW_POWERUP_IND);
211*4882a593Smuzhiyun 		break;
212*4882a593Smuzhiyun 	case W_L1IND_LD:
213*4882a593Smuzhiyun 		if (dch->state <= 5) {
214*4882a593Smuzhiyun 			dch->state = 5;
215*4882a593Smuzhiyun 			l1_event(dch->l1, ANYSIGNAL);
216*4882a593Smuzhiyun 		} else {
217*4882a593Smuzhiyun 			dch->state = 8;
218*4882a593Smuzhiyun 			l1_event(dch->l1, LOSTFRAMING);
219*4882a593Smuzhiyun 		}
220*4882a593Smuzhiyun 		break;
221*4882a593Smuzhiyun 	case W_L1IND_ARD:
222*4882a593Smuzhiyun 		dch->state = 6;
223*4882a593Smuzhiyun 		l1_event(dch->l1, INFO2);
224*4882a593Smuzhiyun 		break;
225*4882a593Smuzhiyun 	case W_L1IND_AI8:
226*4882a593Smuzhiyun 		dch->state = 7;
227*4882a593Smuzhiyun 		l1_event(dch->l1, INFO4_P8);
228*4882a593Smuzhiyun 		break;
229*4882a593Smuzhiyun 	case W_L1IND_AI10:
230*4882a593Smuzhiyun 		dch->state = 7;
231*4882a593Smuzhiyun 		l1_event(dch->l1, INFO4_P10);
232*4882a593Smuzhiyun 		break;
233*4882a593Smuzhiyun 	default:
234*4882a593Smuzhiyun 		pr_debug("%s: TE unknown state %02x dch state %02x\n",
235*4882a593Smuzhiyun 			 card->name, card->state, dch->state);
236*4882a593Smuzhiyun 		break;
237*4882a593Smuzhiyun 	}
238*4882a593Smuzhiyun 	pr_debug("%s: TE newstate %02x\n", card->name, dch->state);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun static void
W6692_empty_Dfifo(struct w6692_hw * card,int count)242*4882a593Smuzhiyun W6692_empty_Dfifo(struct w6692_hw *card, int count)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun 	struct dchannel *dch = &card->dch;
245*4882a593Smuzhiyun 	u8 *ptr;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	pr_debug("%s: empty_Dfifo %d\n", card->name, count);
248*4882a593Smuzhiyun 	if (!dch->rx_skb) {
249*4882a593Smuzhiyun 		dch->rx_skb = mI_alloc_skb(card->dch.maxlen, GFP_ATOMIC);
250*4882a593Smuzhiyun 		if (!dch->rx_skb) {
251*4882a593Smuzhiyun 			pr_info("%s: D receive out of memory\n", card->name);
252*4882a593Smuzhiyun 			WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
253*4882a593Smuzhiyun 			return;
254*4882a593Smuzhiyun 		}
255*4882a593Smuzhiyun 	}
256*4882a593Smuzhiyun 	if ((dch->rx_skb->len + count) >= dch->maxlen) {
257*4882a593Smuzhiyun 		pr_debug("%s: empty_Dfifo overrun %d\n", card->name,
258*4882a593Smuzhiyun 			 dch->rx_skb->len + count);
259*4882a593Smuzhiyun 		WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
260*4882a593Smuzhiyun 		return;
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 	ptr = skb_put(dch->rx_skb, count);
263*4882a593Smuzhiyun 	insb(card->addr + W_D_RFIFO, ptr, count);
264*4882a593Smuzhiyun 	WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK);
265*4882a593Smuzhiyun 	if (debug & DEBUG_HW_DFIFO) {
266*4882a593Smuzhiyun 		snprintf(card->log, 63, "D-recv %s %d ",
267*4882a593Smuzhiyun 			 card->name, count);
268*4882a593Smuzhiyun 		print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
269*4882a593Smuzhiyun 	}
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun static void
W6692_fill_Dfifo(struct w6692_hw * card)273*4882a593Smuzhiyun W6692_fill_Dfifo(struct w6692_hw *card)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	struct dchannel *dch = &card->dch;
276*4882a593Smuzhiyun 	int count;
277*4882a593Smuzhiyun 	u8 *ptr;
278*4882a593Smuzhiyun 	u8 cmd = W_D_CMDR_XMS;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	pr_debug("%s: fill_Dfifo\n", card->name);
281*4882a593Smuzhiyun 	if (!dch->tx_skb)
282*4882a593Smuzhiyun 		return;
283*4882a593Smuzhiyun 	count = dch->tx_skb->len - dch->tx_idx;
284*4882a593Smuzhiyun 	if (count <= 0)
285*4882a593Smuzhiyun 		return;
286*4882a593Smuzhiyun 	if (count > W_D_FIFO_THRESH)
287*4882a593Smuzhiyun 		count = W_D_FIFO_THRESH;
288*4882a593Smuzhiyun 	else
289*4882a593Smuzhiyun 		cmd |= W_D_CMDR_XME;
290*4882a593Smuzhiyun 	ptr = dch->tx_skb->data + dch->tx_idx;
291*4882a593Smuzhiyun 	dch->tx_idx += count;
292*4882a593Smuzhiyun 	outsb(card->addr + W_D_XFIFO, ptr, count);
293*4882a593Smuzhiyun 	WriteW6692(card, W_D_CMDR, cmd);
294*4882a593Smuzhiyun 	if (test_and_set_bit(FLG_BUSY_TIMER, &dch->Flags)) {
295*4882a593Smuzhiyun 		pr_debug("%s: fill_Dfifo dbusytimer running\n", card->name);
296*4882a593Smuzhiyun 		del_timer(&dch->timer);
297*4882a593Smuzhiyun 	}
298*4882a593Smuzhiyun 	dch->timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ) / 1000);
299*4882a593Smuzhiyun 	add_timer(&dch->timer);
300*4882a593Smuzhiyun 	if (debug & DEBUG_HW_DFIFO) {
301*4882a593Smuzhiyun 		snprintf(card->log, 63, "D-send %s %d ",
302*4882a593Smuzhiyun 			 card->name, count);
303*4882a593Smuzhiyun 		print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
304*4882a593Smuzhiyun 	}
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun static void
d_retransmit(struct w6692_hw * card)308*4882a593Smuzhiyun d_retransmit(struct w6692_hw *card)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	struct dchannel *dch = &card->dch;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
313*4882a593Smuzhiyun 		del_timer(&dch->timer);
314*4882a593Smuzhiyun #ifdef FIXME
315*4882a593Smuzhiyun 	if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
316*4882a593Smuzhiyun 		dchannel_sched_event(dch, D_CLEARBUSY);
317*4882a593Smuzhiyun #endif
318*4882a593Smuzhiyun 	if (test_bit(FLG_TX_BUSY, &dch->Flags)) {
319*4882a593Smuzhiyun 		/* Restart frame */
320*4882a593Smuzhiyun 		dch->tx_idx = 0;
321*4882a593Smuzhiyun 		W6692_fill_Dfifo(card);
322*4882a593Smuzhiyun 	} else if (dch->tx_skb) { /* should not happen */
323*4882a593Smuzhiyun 		pr_info("%s: %s without TX_BUSY\n", card->name, __func__);
324*4882a593Smuzhiyun 		test_and_set_bit(FLG_TX_BUSY, &dch->Flags);
325*4882a593Smuzhiyun 		dch->tx_idx = 0;
326*4882a593Smuzhiyun 		W6692_fill_Dfifo(card);
327*4882a593Smuzhiyun 	} else {
328*4882a593Smuzhiyun 		pr_info("%s: XDU no TX_BUSY\n", card->name);
329*4882a593Smuzhiyun 		if (get_next_dframe(dch))
330*4882a593Smuzhiyun 			W6692_fill_Dfifo(card);
331*4882a593Smuzhiyun 	}
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun static void
handle_rxD(struct w6692_hw * card)335*4882a593Smuzhiyun handle_rxD(struct w6692_hw *card) {
336*4882a593Smuzhiyun 	u8	stat;
337*4882a593Smuzhiyun 	int	count;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	stat = ReadW6692(card, W_D_RSTA);
340*4882a593Smuzhiyun 	if (stat & (W_D_RSTA_RDOV | W_D_RSTA_CRCE | W_D_RSTA_RMB)) {
341*4882a593Smuzhiyun 		if (stat & W_D_RSTA_RDOV) {
342*4882a593Smuzhiyun 			pr_debug("%s: D-channel RDOV\n", card->name);
343*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
344*4882a593Smuzhiyun 			card->dch.err_rx++;
345*4882a593Smuzhiyun #endif
346*4882a593Smuzhiyun 		}
347*4882a593Smuzhiyun 		if (stat & W_D_RSTA_CRCE) {
348*4882a593Smuzhiyun 			pr_debug("%s: D-channel CRC error\n", card->name);
349*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
350*4882a593Smuzhiyun 			card->dch.err_crc++;
351*4882a593Smuzhiyun #endif
352*4882a593Smuzhiyun 		}
353*4882a593Smuzhiyun 		if (stat & W_D_RSTA_RMB) {
354*4882a593Smuzhiyun 			pr_debug("%s: D-channel ABORT\n", card->name);
355*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
356*4882a593Smuzhiyun 			card->dch.err_rx++;
357*4882a593Smuzhiyun #endif
358*4882a593Smuzhiyun 		}
359*4882a593Smuzhiyun 		dev_kfree_skb(card->dch.rx_skb);
360*4882a593Smuzhiyun 		card->dch.rx_skb = NULL;
361*4882a593Smuzhiyun 		WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK | W_D_CMDR_RRST);
362*4882a593Smuzhiyun 	} else {
363*4882a593Smuzhiyun 		count = ReadW6692(card, W_D_RBCL) & (W_D_FIFO_THRESH - 1);
364*4882a593Smuzhiyun 		if (count == 0)
365*4882a593Smuzhiyun 			count = W_D_FIFO_THRESH;
366*4882a593Smuzhiyun 		W6692_empty_Dfifo(card, count);
367*4882a593Smuzhiyun 		recv_Dchannel(&card->dch);
368*4882a593Smuzhiyun 	}
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun static void
handle_txD(struct w6692_hw * card)372*4882a593Smuzhiyun handle_txD(struct w6692_hw *card) {
373*4882a593Smuzhiyun 	if (test_and_clear_bit(FLG_BUSY_TIMER, &card->dch.Flags))
374*4882a593Smuzhiyun 		del_timer(&card->dch.timer);
375*4882a593Smuzhiyun 	if (card->dch.tx_skb && card->dch.tx_idx < card->dch.tx_skb->len) {
376*4882a593Smuzhiyun 		W6692_fill_Dfifo(card);
377*4882a593Smuzhiyun 	} else {
378*4882a593Smuzhiyun 		dev_kfree_skb(card->dch.tx_skb);
379*4882a593Smuzhiyun 		if (get_next_dframe(&card->dch))
380*4882a593Smuzhiyun 			W6692_fill_Dfifo(card);
381*4882a593Smuzhiyun 	}
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun static void
handle_statusD(struct w6692_hw * card)385*4882a593Smuzhiyun handle_statusD(struct w6692_hw *card)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun 	struct dchannel *dch = &card->dch;
388*4882a593Smuzhiyun 	u8 exval, v1, cir;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	exval = ReadW6692(card, W_D_EXIR);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	pr_debug("%s: D_EXIR %02x\n", card->name, exval);
393*4882a593Smuzhiyun 	if (exval & (W_D_EXI_XDUN | W_D_EXI_XCOL)) {
394*4882a593Smuzhiyun 		/* Transmit underrun/collision */
395*4882a593Smuzhiyun 		pr_debug("%s: D-channel underrun/collision\n", card->name);
396*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
397*4882a593Smuzhiyun 		dch->err_tx++;
398*4882a593Smuzhiyun #endif
399*4882a593Smuzhiyun 		d_retransmit(card);
400*4882a593Smuzhiyun 	}
401*4882a593Smuzhiyun 	if (exval & W_D_EXI_RDOV) {	/* RDOV */
402*4882a593Smuzhiyun 		pr_debug("%s: D-channel RDOV\n", card->name);
403*4882a593Smuzhiyun 		WriteW6692(card, W_D_CMDR, W_D_CMDR_RRST);
404*4882a593Smuzhiyun 	}
405*4882a593Smuzhiyun 	if (exval & W_D_EXI_TIN2)	/* TIN2 - never */
406*4882a593Smuzhiyun 		pr_debug("%s: spurious TIN2 interrupt\n", card->name);
407*4882a593Smuzhiyun 	if (exval & W_D_EXI_MOC) {	/* MOC - not supported */
408*4882a593Smuzhiyun 		v1 = ReadW6692(card, W_MOSR);
409*4882a593Smuzhiyun 		pr_debug("%s: spurious MOC interrupt MOSR %02x\n",
410*4882a593Smuzhiyun 			 card->name, v1);
411*4882a593Smuzhiyun 	}
412*4882a593Smuzhiyun 	if (exval & W_D_EXI_ISC) {	/* ISC - Level1 change */
413*4882a593Smuzhiyun 		cir = ReadW6692(card, W_CIR);
414*4882a593Smuzhiyun 		pr_debug("%s: ISC CIR %02X\n", card->name, cir);
415*4882a593Smuzhiyun 		if (cir & W_CIR_ICC) {
416*4882a593Smuzhiyun 			v1 = cir & W_CIR_COD_MASK;
417*4882a593Smuzhiyun 			pr_debug("%s: ph_state_change %x -> %x\n", card->name,
418*4882a593Smuzhiyun 				 dch->state, v1);
419*4882a593Smuzhiyun 			card->state = v1;
420*4882a593Smuzhiyun 			if (card->fmask & led) {
421*4882a593Smuzhiyun 				switch (v1) {
422*4882a593Smuzhiyun 				case W_L1IND_AI8:
423*4882a593Smuzhiyun 				case W_L1IND_AI10:
424*4882a593Smuzhiyun 					w6692_led_handler(card, 1);
425*4882a593Smuzhiyun 					break;
426*4882a593Smuzhiyun 				default:
427*4882a593Smuzhiyun 					w6692_led_handler(card, 0);
428*4882a593Smuzhiyun 					break;
429*4882a593Smuzhiyun 				}
430*4882a593Smuzhiyun 			}
431*4882a593Smuzhiyun 			W6692_new_ph(card);
432*4882a593Smuzhiyun 		}
433*4882a593Smuzhiyun 		if (cir & W_CIR_SCC) {
434*4882a593Smuzhiyun 			v1 = ReadW6692(card, W_SQR);
435*4882a593Smuzhiyun 			pr_debug("%s: SCC SQR %02X\n", card->name, v1);
436*4882a593Smuzhiyun 		}
437*4882a593Smuzhiyun 	}
438*4882a593Smuzhiyun 	if (exval & W_D_EXI_WEXP)
439*4882a593Smuzhiyun 		pr_debug("%s: spurious WEXP interrupt!\n", card->name);
440*4882a593Smuzhiyun 	if (exval & W_D_EXI_TEXP)
441*4882a593Smuzhiyun 		pr_debug("%s: spurious TEXP interrupt!\n", card->name);
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun static void
W6692_empty_Bfifo(struct w6692_ch * wch,int count)445*4882a593Smuzhiyun W6692_empty_Bfifo(struct w6692_ch *wch, int count)
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun 	struct w6692_hw *card = wch->bch.hw;
448*4882a593Smuzhiyun 	u8 *ptr;
449*4882a593Smuzhiyun 	int maxlen;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	pr_debug("%s: empty_Bfifo %d\n", card->name, count);
452*4882a593Smuzhiyun 	if (unlikely(wch->bch.state == ISDN_P_NONE)) {
453*4882a593Smuzhiyun 		pr_debug("%s: empty_Bfifo ISDN_P_NONE\n", card->name);
454*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
455*4882a593Smuzhiyun 		if (wch->bch.rx_skb)
456*4882a593Smuzhiyun 			skb_trim(wch->bch.rx_skb, 0);
457*4882a593Smuzhiyun 		return;
458*4882a593Smuzhiyun 	}
459*4882a593Smuzhiyun 	if (test_bit(FLG_RX_OFF, &wch->bch.Flags)) {
460*4882a593Smuzhiyun 		wch->bch.dropcnt += count;
461*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
462*4882a593Smuzhiyun 		return;
463*4882a593Smuzhiyun 	}
464*4882a593Smuzhiyun 	maxlen = bchannel_get_rxbuf(&wch->bch, count);
465*4882a593Smuzhiyun 	if (maxlen < 0) {
466*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
467*4882a593Smuzhiyun 		if (wch->bch.rx_skb)
468*4882a593Smuzhiyun 			skb_trim(wch->bch.rx_skb, 0);
469*4882a593Smuzhiyun 		pr_warn("%s.B%d: No bufferspace for %d bytes\n",
470*4882a593Smuzhiyun 			card->name, wch->bch.nr, count);
471*4882a593Smuzhiyun 		return;
472*4882a593Smuzhiyun 	}
473*4882a593Smuzhiyun 	ptr = skb_put(wch->bch.rx_skb, count);
474*4882a593Smuzhiyun 	insb(wch->addr + W_B_RFIFO, ptr, count);
475*4882a593Smuzhiyun 	WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
476*4882a593Smuzhiyun 	if (debug & DEBUG_HW_DFIFO) {
477*4882a593Smuzhiyun 		snprintf(card->log, 63, "B%1d-recv %s %d ",
478*4882a593Smuzhiyun 			 wch->bch.nr, card->name, count);
479*4882a593Smuzhiyun 		print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
480*4882a593Smuzhiyun 	}
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun static void
W6692_fill_Bfifo(struct w6692_ch * wch)484*4882a593Smuzhiyun W6692_fill_Bfifo(struct w6692_ch *wch)
485*4882a593Smuzhiyun {
486*4882a593Smuzhiyun 	struct w6692_hw *card = wch->bch.hw;
487*4882a593Smuzhiyun 	int count, fillempty = 0;
488*4882a593Smuzhiyun 	u8 *ptr, cmd = W_B_CMDR_RACT | W_B_CMDR_XMS;
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	pr_debug("%s: fill Bfifo\n", card->name);
491*4882a593Smuzhiyun 	if (!wch->bch.tx_skb) {
492*4882a593Smuzhiyun 		if (!test_bit(FLG_TX_EMPTY, &wch->bch.Flags))
493*4882a593Smuzhiyun 			return;
494*4882a593Smuzhiyun 		ptr = wch->bch.fill;
495*4882a593Smuzhiyun 		count = W_B_FIFO_THRESH;
496*4882a593Smuzhiyun 		fillempty = 1;
497*4882a593Smuzhiyun 	} else {
498*4882a593Smuzhiyun 		count = wch->bch.tx_skb->len - wch->bch.tx_idx;
499*4882a593Smuzhiyun 		if (count <= 0)
500*4882a593Smuzhiyun 			return;
501*4882a593Smuzhiyun 		ptr = wch->bch.tx_skb->data + wch->bch.tx_idx;
502*4882a593Smuzhiyun 	}
503*4882a593Smuzhiyun 	if (count > W_B_FIFO_THRESH)
504*4882a593Smuzhiyun 		count = W_B_FIFO_THRESH;
505*4882a593Smuzhiyun 	else if (test_bit(FLG_HDLC, &wch->bch.Flags))
506*4882a593Smuzhiyun 		cmd |= W_B_CMDR_XME;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	pr_debug("%s: fill Bfifo%d/%d\n", card->name,
509*4882a593Smuzhiyun 		 count, wch->bch.tx_idx);
510*4882a593Smuzhiyun 	wch->bch.tx_idx += count;
511*4882a593Smuzhiyun 	if (fillempty) {
512*4882a593Smuzhiyun 		while (count > 0) {
513*4882a593Smuzhiyun 			outsb(wch->addr + W_B_XFIFO, ptr, MISDN_BCH_FILL_SIZE);
514*4882a593Smuzhiyun 			count -= MISDN_BCH_FILL_SIZE;
515*4882a593Smuzhiyun 		}
516*4882a593Smuzhiyun 	} else {
517*4882a593Smuzhiyun 		outsb(wch->addr + W_B_XFIFO, ptr, count);
518*4882a593Smuzhiyun 	}
519*4882a593Smuzhiyun 	WriteW6692B(wch, W_B_CMDR, cmd);
520*4882a593Smuzhiyun 	if ((debug & DEBUG_HW_BFIFO) && !fillempty) {
521*4882a593Smuzhiyun 		snprintf(card->log, 63, "B%1d-send %s %d ",
522*4882a593Smuzhiyun 			 wch->bch.nr, card->name, count);
523*4882a593Smuzhiyun 		print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count);
524*4882a593Smuzhiyun 	}
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun #if 0
528*4882a593Smuzhiyun static int
529*4882a593Smuzhiyun setvolume(struct w6692_ch *wch, int mic, struct sk_buff *skb)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun 	struct w6692_hw *card = wch->bch.hw;
532*4882a593Smuzhiyun 	u16 *vol = (u16 *)skb->data;
533*4882a593Smuzhiyun 	u8 val;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	if ((!(card->fmask & pots)) ||
536*4882a593Smuzhiyun 	    !test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
537*4882a593Smuzhiyun 		return -ENODEV;
538*4882a593Smuzhiyun 	if (skb->len < 2)
539*4882a593Smuzhiyun 		return -EINVAL;
540*4882a593Smuzhiyun 	if (*vol > 7)
541*4882a593Smuzhiyun 		return -EINVAL;
542*4882a593Smuzhiyun 	val = *vol & 7;
543*4882a593Smuzhiyun 	val = 7 - val;
544*4882a593Smuzhiyun 	if (mic) {
545*4882a593Smuzhiyun 		val <<= 3;
546*4882a593Smuzhiyun 		card->xaddr &= 0xc7;
547*4882a593Smuzhiyun 	} else {
548*4882a593Smuzhiyun 		card->xaddr &= 0xf8;
549*4882a593Smuzhiyun 	}
550*4882a593Smuzhiyun 	card->xaddr |= val;
551*4882a593Smuzhiyun 	WriteW6692(card, W_XADDR, card->xaddr);
552*4882a593Smuzhiyun 	return 0;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun static int
556*4882a593Smuzhiyun enable_pots(struct w6692_ch *wch)
557*4882a593Smuzhiyun {
558*4882a593Smuzhiyun 	struct w6692_hw *card = wch->bch.hw;
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	if ((!(card->fmask & pots)) ||
561*4882a593Smuzhiyun 	    !test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
562*4882a593Smuzhiyun 		return -ENODEV;
563*4882a593Smuzhiyun 	wch->b_mode |= W_B_MODE_EPCM | W_B_MODE_BSW0;
564*4882a593Smuzhiyun 	WriteW6692B(wch, W_B_MODE, wch->b_mode);
565*4882a593Smuzhiyun 	WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
566*4882a593Smuzhiyun 	card->pctl |= ((wch->bch.nr & 2) ? W_PCTL_PCX : 0);
567*4882a593Smuzhiyun 	WriteW6692(card, W_PCTL, card->pctl);
568*4882a593Smuzhiyun 	return 0;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun #endif
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun static int
disable_pots(struct w6692_ch * wch)573*4882a593Smuzhiyun disable_pots(struct w6692_ch *wch)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun 	struct w6692_hw *card = wch->bch.hw;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	if (!(card->fmask & pots))
578*4882a593Smuzhiyun 		return -ENODEV;
579*4882a593Smuzhiyun 	wch->b_mode &= ~(W_B_MODE_EPCM | W_B_MODE_BSW0);
580*4882a593Smuzhiyun 	WriteW6692B(wch, W_B_MODE, wch->b_mode);
581*4882a593Smuzhiyun 	WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
582*4882a593Smuzhiyun 		    W_B_CMDR_XRST);
583*4882a593Smuzhiyun 	return 0;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun static int
w6692_mode(struct w6692_ch * wch,u32 pr)587*4882a593Smuzhiyun w6692_mode(struct w6692_ch *wch, u32 pr)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun 	struct w6692_hw	*card;
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	card = wch->bch.hw;
592*4882a593Smuzhiyun 	pr_debug("%s: B%d protocol %x-->%x\n", card->name,
593*4882a593Smuzhiyun 		 wch->bch.nr, wch->bch.state, pr);
594*4882a593Smuzhiyun 	switch (pr) {
595*4882a593Smuzhiyun 	case ISDN_P_NONE:
596*4882a593Smuzhiyun 		if ((card->fmask & pots) && (wch->b_mode & W_B_MODE_EPCM))
597*4882a593Smuzhiyun 			disable_pots(wch);
598*4882a593Smuzhiyun 		wch->b_mode = 0;
599*4882a593Smuzhiyun 		mISDN_clear_bchannel(&wch->bch);
600*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_MODE, wch->b_mode);
601*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
602*4882a593Smuzhiyun 		test_and_clear_bit(FLG_HDLC, &wch->bch.Flags);
603*4882a593Smuzhiyun 		test_and_clear_bit(FLG_TRANSPARENT, &wch->bch.Flags);
604*4882a593Smuzhiyun 		break;
605*4882a593Smuzhiyun 	case ISDN_P_B_RAW:
606*4882a593Smuzhiyun 		wch->b_mode = W_B_MODE_MMS;
607*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_MODE, wch->b_mode);
608*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_EXIM, 0);
609*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
610*4882a593Smuzhiyun 			    W_B_CMDR_XRST);
611*4882a593Smuzhiyun 		test_and_set_bit(FLG_TRANSPARENT, &wch->bch.Flags);
612*4882a593Smuzhiyun 		break;
613*4882a593Smuzhiyun 	case ISDN_P_B_HDLC:
614*4882a593Smuzhiyun 		wch->b_mode = W_B_MODE_ITF;
615*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_MODE, wch->b_mode);
616*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_ADM1, 0xff);
617*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_ADM2, 0xff);
618*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_EXIM, 0);
619*4882a593Smuzhiyun 		WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT |
620*4882a593Smuzhiyun 			    W_B_CMDR_XRST);
621*4882a593Smuzhiyun 		test_and_set_bit(FLG_HDLC, &wch->bch.Flags);
622*4882a593Smuzhiyun 		break;
623*4882a593Smuzhiyun 	default:
624*4882a593Smuzhiyun 		pr_info("%s: protocol %x not known\n", card->name, pr);
625*4882a593Smuzhiyun 		return -ENOPROTOOPT;
626*4882a593Smuzhiyun 	}
627*4882a593Smuzhiyun 	wch->bch.state = pr;
628*4882a593Smuzhiyun 	return 0;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun static void
send_next(struct w6692_ch * wch)632*4882a593Smuzhiyun send_next(struct w6692_ch *wch)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun 	if (wch->bch.tx_skb && wch->bch.tx_idx < wch->bch.tx_skb->len) {
635*4882a593Smuzhiyun 		W6692_fill_Bfifo(wch);
636*4882a593Smuzhiyun 	} else {
637*4882a593Smuzhiyun 		dev_kfree_skb(wch->bch.tx_skb);
638*4882a593Smuzhiyun 		if (get_next_bframe(&wch->bch)) {
639*4882a593Smuzhiyun 			W6692_fill_Bfifo(wch);
640*4882a593Smuzhiyun 			test_and_clear_bit(FLG_TX_EMPTY, &wch->bch.Flags);
641*4882a593Smuzhiyun 		} else if (test_bit(FLG_TX_EMPTY, &wch->bch.Flags)) {
642*4882a593Smuzhiyun 			W6692_fill_Bfifo(wch);
643*4882a593Smuzhiyun 		}
644*4882a593Smuzhiyun 	}
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun static void
W6692B_interrupt(struct w6692_hw * card,int ch)648*4882a593Smuzhiyun W6692B_interrupt(struct w6692_hw *card, int ch)
649*4882a593Smuzhiyun {
650*4882a593Smuzhiyun 	struct w6692_ch	*wch = &card->bc[ch];
651*4882a593Smuzhiyun 	int		count;
652*4882a593Smuzhiyun 	u8		stat, star = 0;
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	stat = ReadW6692B(wch, W_B_EXIR);
655*4882a593Smuzhiyun 	pr_debug("%s: B%d EXIR %02x\n", card->name, wch->bch.nr, stat);
656*4882a593Smuzhiyun 	if (stat & W_B_EXI_RME) {
657*4882a593Smuzhiyun 		star = ReadW6692B(wch, W_B_STAR);
658*4882a593Smuzhiyun 		if (star & (W_B_STAR_RDOV | W_B_STAR_CRCE | W_B_STAR_RMB)) {
659*4882a593Smuzhiyun 			if ((star & W_B_STAR_RDOV) &&
660*4882a593Smuzhiyun 			    test_bit(FLG_ACTIVE, &wch->bch.Flags)) {
661*4882a593Smuzhiyun 				pr_debug("%s: B%d RDOV proto=%x\n", card->name,
662*4882a593Smuzhiyun 					 wch->bch.nr, wch->bch.state);
663*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
664*4882a593Smuzhiyun 				wch->bch.err_rdo++;
665*4882a593Smuzhiyun #endif
666*4882a593Smuzhiyun 			}
667*4882a593Smuzhiyun 			if (test_bit(FLG_HDLC, &wch->bch.Flags)) {
668*4882a593Smuzhiyun 				if (star & W_B_STAR_CRCE) {
669*4882a593Smuzhiyun 					pr_debug("%s: B%d CRC error\n",
670*4882a593Smuzhiyun 						 card->name, wch->bch.nr);
671*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
672*4882a593Smuzhiyun 					wch->bch.err_crc++;
673*4882a593Smuzhiyun #endif
674*4882a593Smuzhiyun 				}
675*4882a593Smuzhiyun 				if (star & W_B_STAR_RMB) {
676*4882a593Smuzhiyun 					pr_debug("%s: B%d message abort\n",
677*4882a593Smuzhiyun 						 card->name, wch->bch.nr);
678*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
679*4882a593Smuzhiyun 					wch->bch.err_inv++;
680*4882a593Smuzhiyun #endif
681*4882a593Smuzhiyun 				}
682*4882a593Smuzhiyun 			}
683*4882a593Smuzhiyun 			WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
684*4882a593Smuzhiyun 				    W_B_CMDR_RRST | W_B_CMDR_RACT);
685*4882a593Smuzhiyun 			if (wch->bch.rx_skb)
686*4882a593Smuzhiyun 				skb_trim(wch->bch.rx_skb, 0);
687*4882a593Smuzhiyun 		} else {
688*4882a593Smuzhiyun 			count = ReadW6692B(wch, W_B_RBCL) &
689*4882a593Smuzhiyun 				(W_B_FIFO_THRESH - 1);
690*4882a593Smuzhiyun 			if (count == 0)
691*4882a593Smuzhiyun 				count = W_B_FIFO_THRESH;
692*4882a593Smuzhiyun 			W6692_empty_Bfifo(wch, count);
693*4882a593Smuzhiyun 			recv_Bchannel(&wch->bch, 0, false);
694*4882a593Smuzhiyun 		}
695*4882a593Smuzhiyun 	}
696*4882a593Smuzhiyun 	if (stat & W_B_EXI_RMR) {
697*4882a593Smuzhiyun 		if (!(stat & W_B_EXI_RME))
698*4882a593Smuzhiyun 			star = ReadW6692B(wch, W_B_STAR);
699*4882a593Smuzhiyun 		if (star & W_B_STAR_RDOV) {
700*4882a593Smuzhiyun 			pr_debug("%s: B%d RDOV proto=%x\n", card->name,
701*4882a593Smuzhiyun 				 wch->bch.nr, wch->bch.state);
702*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
703*4882a593Smuzhiyun 			wch->bch.err_rdo++;
704*4882a593Smuzhiyun #endif
705*4882a593Smuzhiyun 			WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
706*4882a593Smuzhiyun 				    W_B_CMDR_RRST | W_B_CMDR_RACT);
707*4882a593Smuzhiyun 		} else {
708*4882a593Smuzhiyun 			W6692_empty_Bfifo(wch, W_B_FIFO_THRESH);
709*4882a593Smuzhiyun 			if (test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
710*4882a593Smuzhiyun 				recv_Bchannel(&wch->bch, 0, false);
711*4882a593Smuzhiyun 		}
712*4882a593Smuzhiyun 	}
713*4882a593Smuzhiyun 	if (stat & W_B_EXI_RDOV) {
714*4882a593Smuzhiyun 		/* only if it is not handled yet */
715*4882a593Smuzhiyun 		if (!(star & W_B_STAR_RDOV)) {
716*4882a593Smuzhiyun 			pr_debug("%s: B%d RDOV IRQ proto=%x\n", card->name,
717*4882a593Smuzhiyun 				 wch->bch.nr, wch->bch.state);
718*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
719*4882a593Smuzhiyun 			wch->bch.err_rdo++;
720*4882a593Smuzhiyun #endif
721*4882a593Smuzhiyun 			WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK |
722*4882a593Smuzhiyun 				    W_B_CMDR_RRST | W_B_CMDR_RACT);
723*4882a593Smuzhiyun 		}
724*4882a593Smuzhiyun 	}
725*4882a593Smuzhiyun 	if (stat & W_B_EXI_XFR) {
726*4882a593Smuzhiyun 		if (!(stat & (W_B_EXI_RME | W_B_EXI_RMR))) {
727*4882a593Smuzhiyun 			star = ReadW6692B(wch, W_B_STAR);
728*4882a593Smuzhiyun 			pr_debug("%s: B%d star %02x\n", card->name,
729*4882a593Smuzhiyun 				 wch->bch.nr, star);
730*4882a593Smuzhiyun 		}
731*4882a593Smuzhiyun 		if (star & W_B_STAR_XDOW) {
732*4882a593Smuzhiyun 			pr_warn("%s: B%d XDOW proto=%x\n", card->name,
733*4882a593Smuzhiyun 				wch->bch.nr, wch->bch.state);
734*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
735*4882a593Smuzhiyun 			wch->bch.err_xdu++;
736*4882a593Smuzhiyun #endif
737*4882a593Smuzhiyun 			WriteW6692B(wch, W_B_CMDR, W_B_CMDR_XRST |
738*4882a593Smuzhiyun 				    W_B_CMDR_RACT);
739*4882a593Smuzhiyun 			/* resend */
740*4882a593Smuzhiyun 			if (wch->bch.tx_skb) {
741*4882a593Smuzhiyun 				if (!test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
742*4882a593Smuzhiyun 					wch->bch.tx_idx = 0;
743*4882a593Smuzhiyun 			}
744*4882a593Smuzhiyun 		}
745*4882a593Smuzhiyun 		send_next(wch);
746*4882a593Smuzhiyun 		if (star & W_B_STAR_XDOW)
747*4882a593Smuzhiyun 			return; /* handle XDOW only once */
748*4882a593Smuzhiyun 	}
749*4882a593Smuzhiyun 	if (stat & W_B_EXI_XDUN) {
750*4882a593Smuzhiyun 		pr_warn("%s: B%d XDUN proto=%x\n", card->name,
751*4882a593Smuzhiyun 			wch->bch.nr, wch->bch.state);
752*4882a593Smuzhiyun #ifdef ERROR_STATISTIC
753*4882a593Smuzhiyun 		wch->bch.err_xdu++;
754*4882a593Smuzhiyun #endif
755*4882a593Smuzhiyun 		/* resend - no XRST needed */
756*4882a593Smuzhiyun 		if (wch->bch.tx_skb) {
757*4882a593Smuzhiyun 			if (!test_bit(FLG_TRANSPARENT, &wch->bch.Flags))
758*4882a593Smuzhiyun 				wch->bch.tx_idx = 0;
759*4882a593Smuzhiyun 		} else if (test_bit(FLG_FILLEMPTY, &wch->bch.Flags)) {
760*4882a593Smuzhiyun 			test_and_set_bit(FLG_TX_EMPTY, &wch->bch.Flags);
761*4882a593Smuzhiyun 		}
762*4882a593Smuzhiyun 		send_next(wch);
763*4882a593Smuzhiyun 	}
764*4882a593Smuzhiyun }
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun static irqreturn_t
w6692_irq(int intno,void * dev_id)767*4882a593Smuzhiyun w6692_irq(int intno, void *dev_id)
768*4882a593Smuzhiyun {
769*4882a593Smuzhiyun 	struct w6692_hw	*card = dev_id;
770*4882a593Smuzhiyun 	u8		ista;
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun 	spin_lock(&card->lock);
773*4882a593Smuzhiyun 	ista = ReadW6692(card, W_ISTA);
774*4882a593Smuzhiyun 	if ((ista | card->imask) == card->imask) {
775*4882a593Smuzhiyun 		/* possible a shared  IRQ reqest */
776*4882a593Smuzhiyun 		spin_unlock(&card->lock);
777*4882a593Smuzhiyun 		return IRQ_NONE;
778*4882a593Smuzhiyun 	}
779*4882a593Smuzhiyun 	card->irqcnt++;
780*4882a593Smuzhiyun 	pr_debug("%s: ista %02x\n", card->name, ista);
781*4882a593Smuzhiyun 	ista &= ~card->imask;
782*4882a593Smuzhiyun 	if (ista & W_INT_B1_EXI)
783*4882a593Smuzhiyun 		W6692B_interrupt(card, 0);
784*4882a593Smuzhiyun 	if (ista & W_INT_B2_EXI)
785*4882a593Smuzhiyun 		W6692B_interrupt(card, 1);
786*4882a593Smuzhiyun 	if (ista & W_INT_D_RME)
787*4882a593Smuzhiyun 		handle_rxD(card);
788*4882a593Smuzhiyun 	if (ista & W_INT_D_RMR)
789*4882a593Smuzhiyun 		W6692_empty_Dfifo(card, W_D_FIFO_THRESH);
790*4882a593Smuzhiyun 	if (ista & W_INT_D_XFR)
791*4882a593Smuzhiyun 		handle_txD(card);
792*4882a593Smuzhiyun 	if (ista & W_INT_D_EXI)
793*4882a593Smuzhiyun 		handle_statusD(card);
794*4882a593Smuzhiyun 	if (ista & (W_INT_XINT0 | W_INT_XINT1)) /* XINT0/1 - never */
795*4882a593Smuzhiyun 		pr_debug("%s: W6692 spurious XINT!\n", card->name);
796*4882a593Smuzhiyun /* End IRQ Handler */
797*4882a593Smuzhiyun 	spin_unlock(&card->lock);
798*4882a593Smuzhiyun 	return IRQ_HANDLED;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun static void
dbusy_timer_handler(struct timer_list * t)802*4882a593Smuzhiyun dbusy_timer_handler(struct timer_list *t)
803*4882a593Smuzhiyun {
804*4882a593Smuzhiyun 	struct dchannel *dch = from_timer(dch, t, timer);
805*4882a593Smuzhiyun 	struct w6692_hw	*card = dch->hw;
806*4882a593Smuzhiyun 	int		rbch, star;
807*4882a593Smuzhiyun 	u_long		flags;
808*4882a593Smuzhiyun 
809*4882a593Smuzhiyun 	if (test_bit(FLG_BUSY_TIMER, &dch->Flags)) {
810*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
811*4882a593Smuzhiyun 		rbch = ReadW6692(card, W_D_RBCH);
812*4882a593Smuzhiyun 		star = ReadW6692(card, W_D_STAR);
813*4882a593Smuzhiyun 		pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
814*4882a593Smuzhiyun 			 card->name, rbch, star);
815*4882a593Smuzhiyun 		if (star & W_D_STAR_XBZ)	/* D-Channel Busy */
816*4882a593Smuzhiyun 			test_and_set_bit(FLG_L1_BUSY, &dch->Flags);
817*4882a593Smuzhiyun 		else {
818*4882a593Smuzhiyun 			/* discard frame; reset transceiver */
819*4882a593Smuzhiyun 			test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags);
820*4882a593Smuzhiyun 			if (dch->tx_idx)
821*4882a593Smuzhiyun 				dch->tx_idx = 0;
822*4882a593Smuzhiyun 			else
823*4882a593Smuzhiyun 				pr_info("%s: W6692 D-Channel Busy no tx_idx\n",
824*4882a593Smuzhiyun 					card->name);
825*4882a593Smuzhiyun 			/* Transmitter reset */
826*4882a593Smuzhiyun 			WriteW6692(card, W_D_CMDR, W_D_CMDR_XRST);
827*4882a593Smuzhiyun 		}
828*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
829*4882a593Smuzhiyun 	}
830*4882a593Smuzhiyun }
831*4882a593Smuzhiyun 
initW6692(struct w6692_hw * card)832*4882a593Smuzhiyun static void initW6692(struct w6692_hw *card)
833*4882a593Smuzhiyun {
834*4882a593Smuzhiyun 	u8	val;
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	timer_setup(&card->dch.timer, dbusy_timer_handler, 0);
837*4882a593Smuzhiyun 	w6692_mode(&card->bc[0], ISDN_P_NONE);
838*4882a593Smuzhiyun 	w6692_mode(&card->bc[1], ISDN_P_NONE);
839*4882a593Smuzhiyun 	WriteW6692(card, W_D_CTL, 0x00);
840*4882a593Smuzhiyun 	disable_hwirq(card);
841*4882a593Smuzhiyun 	WriteW6692(card, W_D_SAM, 0xff);
842*4882a593Smuzhiyun 	WriteW6692(card, W_D_TAM, 0xff);
843*4882a593Smuzhiyun 	WriteW6692(card, W_D_MODE, W_D_MODE_RACT);
844*4882a593Smuzhiyun 	card->state = W_L1CMD_RST;
845*4882a593Smuzhiyun 	ph_command(card, W_L1CMD_RST);
846*4882a593Smuzhiyun 	ph_command(card, W_L1CMD_ECK);
847*4882a593Smuzhiyun 	/* enable all IRQ but extern */
848*4882a593Smuzhiyun 	card->imask = 0x18;
849*4882a593Smuzhiyun 	WriteW6692(card, W_D_EXIM, 0x00);
850*4882a593Smuzhiyun 	WriteW6692B(&card->bc[0], W_B_EXIM, 0);
851*4882a593Smuzhiyun 	WriteW6692B(&card->bc[1], W_B_EXIM, 0);
852*4882a593Smuzhiyun 	/* Reset D-chan receiver and transmitter */
853*4882a593Smuzhiyun 	WriteW6692(card, W_D_CMDR, W_D_CMDR_RRST | W_D_CMDR_XRST);
854*4882a593Smuzhiyun 	/* Reset B-chan receiver and transmitter */
855*4882a593Smuzhiyun 	WriteW6692B(&card->bc[0], W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
856*4882a593Smuzhiyun 	WriteW6692B(&card->bc[1], W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST);
857*4882a593Smuzhiyun 	/* enable peripheral */
858*4882a593Smuzhiyun 	if (card->subtype == W6692_USR) {
859*4882a593Smuzhiyun 		/* seems that USR implemented some power control features
860*4882a593Smuzhiyun 		 * Pin 79 is connected to the oscilator circuit so we
861*4882a593Smuzhiyun 		 * have to handle it here
862*4882a593Smuzhiyun 		 */
863*4882a593Smuzhiyun 		card->pctl = 0x80;
864*4882a593Smuzhiyun 		card->xdata = 0;
865*4882a593Smuzhiyun 		WriteW6692(card, W_PCTL, card->pctl);
866*4882a593Smuzhiyun 		WriteW6692(card, W_XDATA, card->xdata);
867*4882a593Smuzhiyun 	} else {
868*4882a593Smuzhiyun 		card->pctl = W_PCTL_OE5 | W_PCTL_OE4 | W_PCTL_OE2 |
869*4882a593Smuzhiyun 			W_PCTL_OE1 | W_PCTL_OE0;
870*4882a593Smuzhiyun 		card->xaddr = 0x00;/* all sw off */
871*4882a593Smuzhiyun 		if (card->fmask & pots)
872*4882a593Smuzhiyun 			card->xdata |= 0x06;	/*  POWER UP/ LED OFF / ALAW */
873*4882a593Smuzhiyun 		if (card->fmask & led)
874*4882a593Smuzhiyun 			card->xdata |= 0x04;	/* LED OFF */
875*4882a593Smuzhiyun 		if ((card->fmask & pots) || (card->fmask & led)) {
876*4882a593Smuzhiyun 			WriteW6692(card, W_PCTL, card->pctl);
877*4882a593Smuzhiyun 			WriteW6692(card, W_XADDR, card->xaddr);
878*4882a593Smuzhiyun 			WriteW6692(card, W_XDATA, card->xdata);
879*4882a593Smuzhiyun 			val = ReadW6692(card, W_XADDR);
880*4882a593Smuzhiyun 			if (debug & DEBUG_HW)
881*4882a593Smuzhiyun 				pr_notice("%s: W_XADDR=%02x\n",
882*4882a593Smuzhiyun 					  card->name, val);
883*4882a593Smuzhiyun 		}
884*4882a593Smuzhiyun 	}
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun static void
reset_w6692(struct w6692_hw * card)888*4882a593Smuzhiyun reset_w6692(struct w6692_hw *card)
889*4882a593Smuzhiyun {
890*4882a593Smuzhiyun 	WriteW6692(card, W_D_CTL, W_D_CTL_SRST);
891*4882a593Smuzhiyun 	mdelay(10);
892*4882a593Smuzhiyun 	WriteW6692(card, W_D_CTL, 0);
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun 
895*4882a593Smuzhiyun static int
init_card(struct w6692_hw * card)896*4882a593Smuzhiyun init_card(struct w6692_hw *card)
897*4882a593Smuzhiyun {
898*4882a593Smuzhiyun 	int	cnt = 3;
899*4882a593Smuzhiyun 	u_long	flags;
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	spin_lock_irqsave(&card->lock, flags);
902*4882a593Smuzhiyun 	disable_hwirq(card);
903*4882a593Smuzhiyun 	spin_unlock_irqrestore(&card->lock, flags);
904*4882a593Smuzhiyun 	if (request_irq(card->irq, w6692_irq, IRQF_SHARED, card->name, card)) {
905*4882a593Smuzhiyun 		pr_info("%s: couldn't get interrupt %d\n", card->name,
906*4882a593Smuzhiyun 			card->irq);
907*4882a593Smuzhiyun 		return -EIO;
908*4882a593Smuzhiyun 	}
909*4882a593Smuzhiyun 	while (cnt--) {
910*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
911*4882a593Smuzhiyun 		initW6692(card);
912*4882a593Smuzhiyun 		enable_hwirq(card);
913*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
914*4882a593Smuzhiyun 		/* Timeout 10ms */
915*4882a593Smuzhiyun 		msleep_interruptible(10);
916*4882a593Smuzhiyun 		if (debug & DEBUG_HW)
917*4882a593Smuzhiyun 			pr_notice("%s: IRQ %d count %d\n", card->name,
918*4882a593Smuzhiyun 				  card->irq, card->irqcnt);
919*4882a593Smuzhiyun 		if (!card->irqcnt) {
920*4882a593Smuzhiyun 			pr_info("%s: IRQ(%d) getting no IRQs during init %d\n",
921*4882a593Smuzhiyun 				card->name, card->irq, 3 - cnt);
922*4882a593Smuzhiyun 			reset_w6692(card);
923*4882a593Smuzhiyun 		} else
924*4882a593Smuzhiyun 			return 0;
925*4882a593Smuzhiyun 	}
926*4882a593Smuzhiyun 	free_irq(card->irq, card);
927*4882a593Smuzhiyun 	return -EIO;
928*4882a593Smuzhiyun }
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun static int
w6692_l2l1B(struct mISDNchannel * ch,struct sk_buff * skb)931*4882a593Smuzhiyun w6692_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun 	struct bchannel *bch = container_of(ch, struct bchannel, ch);
934*4882a593Smuzhiyun 	struct w6692_ch	*bc = container_of(bch, struct w6692_ch, bch);
935*4882a593Smuzhiyun 	struct w6692_hw *card = bch->hw;
936*4882a593Smuzhiyun 	int ret = -EINVAL;
937*4882a593Smuzhiyun 	struct mISDNhead *hh = mISDN_HEAD_P(skb);
938*4882a593Smuzhiyun 	unsigned long flags;
939*4882a593Smuzhiyun 
940*4882a593Smuzhiyun 	switch (hh->prim) {
941*4882a593Smuzhiyun 	case PH_DATA_REQ:
942*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
943*4882a593Smuzhiyun 		ret = bchannel_senddata(bch, skb);
944*4882a593Smuzhiyun 		if (ret > 0) { /* direct TX */
945*4882a593Smuzhiyun 			ret = 0;
946*4882a593Smuzhiyun 			W6692_fill_Bfifo(bc);
947*4882a593Smuzhiyun 		}
948*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
949*4882a593Smuzhiyun 		return ret;
950*4882a593Smuzhiyun 	case PH_ACTIVATE_REQ:
951*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
952*4882a593Smuzhiyun 		if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
953*4882a593Smuzhiyun 			ret = w6692_mode(bc, ch->protocol);
954*4882a593Smuzhiyun 		else
955*4882a593Smuzhiyun 			ret = 0;
956*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
957*4882a593Smuzhiyun 		if (!ret)
958*4882a593Smuzhiyun 			_queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
959*4882a593Smuzhiyun 				    NULL, GFP_KERNEL);
960*4882a593Smuzhiyun 		break;
961*4882a593Smuzhiyun 	case PH_DEACTIVATE_REQ:
962*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
963*4882a593Smuzhiyun 		mISDN_clear_bchannel(bch);
964*4882a593Smuzhiyun 		w6692_mode(bc, ISDN_P_NONE);
965*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
966*4882a593Smuzhiyun 		_queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
967*4882a593Smuzhiyun 			    NULL, GFP_KERNEL);
968*4882a593Smuzhiyun 		ret = 0;
969*4882a593Smuzhiyun 		break;
970*4882a593Smuzhiyun 	default:
971*4882a593Smuzhiyun 		pr_info("%s: %s unknown prim(%x,%x)\n",
972*4882a593Smuzhiyun 			card->name, __func__, hh->prim, hh->id);
973*4882a593Smuzhiyun 		ret = -EINVAL;
974*4882a593Smuzhiyun 	}
975*4882a593Smuzhiyun 	if (!ret)
976*4882a593Smuzhiyun 		dev_kfree_skb(skb);
977*4882a593Smuzhiyun 	return ret;
978*4882a593Smuzhiyun }
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun static int
channel_bctrl(struct bchannel * bch,struct mISDN_ctrl_req * cq)981*4882a593Smuzhiyun channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
982*4882a593Smuzhiyun {
983*4882a593Smuzhiyun 	return mISDN_ctrl_bchannel(bch, cq);
984*4882a593Smuzhiyun }
985*4882a593Smuzhiyun 
986*4882a593Smuzhiyun static int
open_bchannel(struct w6692_hw * card,struct channel_req * rq)987*4882a593Smuzhiyun open_bchannel(struct w6692_hw *card, struct channel_req *rq)
988*4882a593Smuzhiyun {
989*4882a593Smuzhiyun 	struct bchannel *bch;
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun 	if (rq->adr.channel == 0 || rq->adr.channel > 2)
992*4882a593Smuzhiyun 		return -EINVAL;
993*4882a593Smuzhiyun 	if (rq->protocol == ISDN_P_NONE)
994*4882a593Smuzhiyun 		return -EINVAL;
995*4882a593Smuzhiyun 	bch = &card->bc[rq->adr.channel - 1].bch;
996*4882a593Smuzhiyun 	if (test_and_set_bit(FLG_OPEN, &bch->Flags))
997*4882a593Smuzhiyun 		return -EBUSY; /* b-channel can be only open once */
998*4882a593Smuzhiyun 	bch->ch.protocol = rq->protocol;
999*4882a593Smuzhiyun 	rq->ch = &bch->ch;
1000*4882a593Smuzhiyun 	return 0;
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun static int
channel_ctrl(struct w6692_hw * card,struct mISDN_ctrl_req * cq)1004*4882a593Smuzhiyun channel_ctrl(struct w6692_hw *card, struct mISDN_ctrl_req *cq)
1005*4882a593Smuzhiyun {
1006*4882a593Smuzhiyun 	int	ret = 0;
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun 	switch (cq->op) {
1009*4882a593Smuzhiyun 	case MISDN_CTRL_GETOP:
1010*4882a593Smuzhiyun 		cq->op = MISDN_CTRL_L1_TIMER3;
1011*4882a593Smuzhiyun 		break;
1012*4882a593Smuzhiyun 	case MISDN_CTRL_L1_TIMER3:
1013*4882a593Smuzhiyun 		ret = l1_event(card->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
1014*4882a593Smuzhiyun 		break;
1015*4882a593Smuzhiyun 	default:
1016*4882a593Smuzhiyun 		pr_info("%s: unknown CTRL OP %x\n", card->name, cq->op);
1017*4882a593Smuzhiyun 		ret = -EINVAL;
1018*4882a593Smuzhiyun 		break;
1019*4882a593Smuzhiyun 	}
1020*4882a593Smuzhiyun 	return ret;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun 
1023*4882a593Smuzhiyun static int
w6692_bctrl(struct mISDNchannel * ch,u32 cmd,void * arg)1024*4882a593Smuzhiyun w6692_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1025*4882a593Smuzhiyun {
1026*4882a593Smuzhiyun 	struct bchannel *bch = container_of(ch, struct bchannel, ch);
1027*4882a593Smuzhiyun 	struct w6692_ch *bc = container_of(bch, struct w6692_ch, bch);
1028*4882a593Smuzhiyun 	struct w6692_hw *card = bch->hw;
1029*4882a593Smuzhiyun 	int ret = -EINVAL;
1030*4882a593Smuzhiyun 	u_long flags;
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 	pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
1033*4882a593Smuzhiyun 	switch (cmd) {
1034*4882a593Smuzhiyun 	case CLOSE_CHANNEL:
1035*4882a593Smuzhiyun 		test_and_clear_bit(FLG_OPEN, &bch->Flags);
1036*4882a593Smuzhiyun 		cancel_work_sync(&bch->workq);
1037*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
1038*4882a593Smuzhiyun 		mISDN_clear_bchannel(bch);
1039*4882a593Smuzhiyun 		w6692_mode(bc, ISDN_P_NONE);
1040*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
1041*4882a593Smuzhiyun 		ch->protocol = ISDN_P_NONE;
1042*4882a593Smuzhiyun 		ch->peer = NULL;
1043*4882a593Smuzhiyun 		module_put(THIS_MODULE);
1044*4882a593Smuzhiyun 		ret = 0;
1045*4882a593Smuzhiyun 		break;
1046*4882a593Smuzhiyun 	case CONTROL_CHANNEL:
1047*4882a593Smuzhiyun 		ret = channel_bctrl(bch, arg);
1048*4882a593Smuzhiyun 		break;
1049*4882a593Smuzhiyun 	default:
1050*4882a593Smuzhiyun 		pr_info("%s: %s unknown prim(%x)\n",
1051*4882a593Smuzhiyun 			card->name, __func__, cmd);
1052*4882a593Smuzhiyun 	}
1053*4882a593Smuzhiyun 	return ret;
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun 
1056*4882a593Smuzhiyun static int
w6692_l2l1D(struct mISDNchannel * ch,struct sk_buff * skb)1057*4882a593Smuzhiyun w6692_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1058*4882a593Smuzhiyun {
1059*4882a593Smuzhiyun 	struct mISDNdevice	*dev = container_of(ch, struct mISDNdevice, D);
1060*4882a593Smuzhiyun 	struct dchannel		*dch = container_of(dev, struct dchannel, dev);
1061*4882a593Smuzhiyun 	struct w6692_hw		*card = container_of(dch, struct w6692_hw, dch);
1062*4882a593Smuzhiyun 	int			ret = -EINVAL;
1063*4882a593Smuzhiyun 	struct mISDNhead	*hh = mISDN_HEAD_P(skb);
1064*4882a593Smuzhiyun 	u32			id;
1065*4882a593Smuzhiyun 	u_long			flags;
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 	switch (hh->prim) {
1068*4882a593Smuzhiyun 	case PH_DATA_REQ:
1069*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
1070*4882a593Smuzhiyun 		ret = dchannel_senddata(dch, skb);
1071*4882a593Smuzhiyun 		if (ret > 0) { /* direct TX */
1072*4882a593Smuzhiyun 			id = hh->id; /* skb can be freed */
1073*4882a593Smuzhiyun 			W6692_fill_Dfifo(card);
1074*4882a593Smuzhiyun 			ret = 0;
1075*4882a593Smuzhiyun 			spin_unlock_irqrestore(&card->lock, flags);
1076*4882a593Smuzhiyun 			queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1077*4882a593Smuzhiyun 		} else
1078*4882a593Smuzhiyun 			spin_unlock_irqrestore(&card->lock, flags);
1079*4882a593Smuzhiyun 		return ret;
1080*4882a593Smuzhiyun 	case PH_ACTIVATE_REQ:
1081*4882a593Smuzhiyun 		ret = l1_event(dch->l1, hh->prim);
1082*4882a593Smuzhiyun 		break;
1083*4882a593Smuzhiyun 	case PH_DEACTIVATE_REQ:
1084*4882a593Smuzhiyun 		test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1085*4882a593Smuzhiyun 		ret = l1_event(dch->l1, hh->prim);
1086*4882a593Smuzhiyun 		break;
1087*4882a593Smuzhiyun 	}
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 	if (!ret)
1090*4882a593Smuzhiyun 		dev_kfree_skb(skb);
1091*4882a593Smuzhiyun 	return ret;
1092*4882a593Smuzhiyun }
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun static int
w6692_l1callback(struct dchannel * dch,u32 cmd)1095*4882a593Smuzhiyun w6692_l1callback(struct dchannel *dch, u32 cmd)
1096*4882a593Smuzhiyun {
1097*4882a593Smuzhiyun 	struct w6692_hw *card = container_of(dch, struct w6692_hw, dch);
1098*4882a593Smuzhiyun 	u_long flags;
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 	pr_debug("%s: cmd(%x) state(%02x)\n", card->name, cmd, card->state);
1101*4882a593Smuzhiyun 	switch (cmd) {
1102*4882a593Smuzhiyun 	case INFO3_P8:
1103*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
1104*4882a593Smuzhiyun 		ph_command(card, W_L1CMD_AR8);
1105*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
1106*4882a593Smuzhiyun 		break;
1107*4882a593Smuzhiyun 	case INFO3_P10:
1108*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
1109*4882a593Smuzhiyun 		ph_command(card, W_L1CMD_AR10);
1110*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
1111*4882a593Smuzhiyun 		break;
1112*4882a593Smuzhiyun 	case HW_RESET_REQ:
1113*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
1114*4882a593Smuzhiyun 		if (card->state != W_L1IND_DRD)
1115*4882a593Smuzhiyun 			ph_command(card, W_L1CMD_RST);
1116*4882a593Smuzhiyun 		ph_command(card, W_L1CMD_ECK);
1117*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
1118*4882a593Smuzhiyun 		break;
1119*4882a593Smuzhiyun 	case HW_DEACT_REQ:
1120*4882a593Smuzhiyun 		skb_queue_purge(&dch->squeue);
1121*4882a593Smuzhiyun 		if (dch->tx_skb) {
1122*4882a593Smuzhiyun 			dev_kfree_skb(dch->tx_skb);
1123*4882a593Smuzhiyun 			dch->tx_skb = NULL;
1124*4882a593Smuzhiyun 		}
1125*4882a593Smuzhiyun 		dch->tx_idx = 0;
1126*4882a593Smuzhiyun 		if (dch->rx_skb) {
1127*4882a593Smuzhiyun 			dev_kfree_skb(dch->rx_skb);
1128*4882a593Smuzhiyun 			dch->rx_skb = NULL;
1129*4882a593Smuzhiyun 		}
1130*4882a593Smuzhiyun 		test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1131*4882a593Smuzhiyun 		if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1132*4882a593Smuzhiyun 			del_timer(&dch->timer);
1133*4882a593Smuzhiyun 		break;
1134*4882a593Smuzhiyun 	case HW_POWERUP_REQ:
1135*4882a593Smuzhiyun 		spin_lock_irqsave(&card->lock, flags);
1136*4882a593Smuzhiyun 		ph_command(card, W_L1CMD_ECK);
1137*4882a593Smuzhiyun 		spin_unlock_irqrestore(&card->lock, flags);
1138*4882a593Smuzhiyun 		break;
1139*4882a593Smuzhiyun 	case PH_ACTIVATE_IND:
1140*4882a593Smuzhiyun 		test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1141*4882a593Smuzhiyun 		_queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1142*4882a593Smuzhiyun 			    GFP_ATOMIC);
1143*4882a593Smuzhiyun 		break;
1144*4882a593Smuzhiyun 	case PH_DEACTIVATE_IND:
1145*4882a593Smuzhiyun 		test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1146*4882a593Smuzhiyun 		_queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1147*4882a593Smuzhiyun 			    GFP_ATOMIC);
1148*4882a593Smuzhiyun 		break;
1149*4882a593Smuzhiyun 	default:
1150*4882a593Smuzhiyun 		pr_debug("%s: %s unknown command %x\n", card->name,
1151*4882a593Smuzhiyun 			 __func__, cmd);
1152*4882a593Smuzhiyun 		return -1;
1153*4882a593Smuzhiyun 	}
1154*4882a593Smuzhiyun 	return 0;
1155*4882a593Smuzhiyun }
1156*4882a593Smuzhiyun 
1157*4882a593Smuzhiyun static int
open_dchannel(struct w6692_hw * card,struct channel_req * rq,void * caller)1158*4882a593Smuzhiyun open_dchannel(struct w6692_hw *card, struct channel_req *rq, void *caller)
1159*4882a593Smuzhiyun {
1160*4882a593Smuzhiyun 	pr_debug("%s: %s dev(%d) open from %p\n", card->name, __func__,
1161*4882a593Smuzhiyun 		 card->dch.dev.id, caller);
1162*4882a593Smuzhiyun 	if (rq->protocol != ISDN_P_TE_S0)
1163*4882a593Smuzhiyun 		return -EINVAL;
1164*4882a593Smuzhiyun 	if (rq->adr.channel == 1)
1165*4882a593Smuzhiyun 		/* E-Channel not supported */
1166*4882a593Smuzhiyun 		return -EINVAL;
1167*4882a593Smuzhiyun 	rq->ch = &card->dch.dev.D;
1168*4882a593Smuzhiyun 	rq->ch->protocol = rq->protocol;
1169*4882a593Smuzhiyun 	if (card->dch.state == 7)
1170*4882a593Smuzhiyun 		_queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1171*4882a593Smuzhiyun 			    0, NULL, GFP_KERNEL);
1172*4882a593Smuzhiyun 	return 0;
1173*4882a593Smuzhiyun }
1174*4882a593Smuzhiyun 
1175*4882a593Smuzhiyun static int
w6692_dctrl(struct mISDNchannel * ch,u32 cmd,void * arg)1176*4882a593Smuzhiyun w6692_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1177*4882a593Smuzhiyun {
1178*4882a593Smuzhiyun 	struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1179*4882a593Smuzhiyun 	struct dchannel *dch = container_of(dev, struct dchannel, dev);
1180*4882a593Smuzhiyun 	struct w6692_hw *card = container_of(dch, struct w6692_hw, dch);
1181*4882a593Smuzhiyun 	struct channel_req *rq;
1182*4882a593Smuzhiyun 	int err = 0;
1183*4882a593Smuzhiyun 
1184*4882a593Smuzhiyun 	pr_debug("%s: DCTRL: %x %p\n", card->name, cmd, arg);
1185*4882a593Smuzhiyun 	switch (cmd) {
1186*4882a593Smuzhiyun 	case OPEN_CHANNEL:
1187*4882a593Smuzhiyun 		rq = arg;
1188*4882a593Smuzhiyun 		if (rq->protocol == ISDN_P_TE_S0)
1189*4882a593Smuzhiyun 			err = open_dchannel(card, rq, __builtin_return_address(0));
1190*4882a593Smuzhiyun 		else
1191*4882a593Smuzhiyun 			err = open_bchannel(card, rq);
1192*4882a593Smuzhiyun 		if (err)
1193*4882a593Smuzhiyun 			break;
1194*4882a593Smuzhiyun 		if (!try_module_get(THIS_MODULE))
1195*4882a593Smuzhiyun 			pr_info("%s: cannot get module\n", card->name);
1196*4882a593Smuzhiyun 		break;
1197*4882a593Smuzhiyun 	case CLOSE_CHANNEL:
1198*4882a593Smuzhiyun 		pr_debug("%s: dev(%d) close from %p\n", card->name,
1199*4882a593Smuzhiyun 			 dch->dev.id, __builtin_return_address(0));
1200*4882a593Smuzhiyun 		module_put(THIS_MODULE);
1201*4882a593Smuzhiyun 		break;
1202*4882a593Smuzhiyun 	case CONTROL_CHANNEL:
1203*4882a593Smuzhiyun 		err = channel_ctrl(card, arg);
1204*4882a593Smuzhiyun 		break;
1205*4882a593Smuzhiyun 	default:
1206*4882a593Smuzhiyun 		pr_debug("%s: unknown DCTRL command %x\n", card->name, cmd);
1207*4882a593Smuzhiyun 		return -EINVAL;
1208*4882a593Smuzhiyun 	}
1209*4882a593Smuzhiyun 	return err;
1210*4882a593Smuzhiyun }
1211*4882a593Smuzhiyun 
1212*4882a593Smuzhiyun static int
setup_w6692(struct w6692_hw * card)1213*4882a593Smuzhiyun setup_w6692(struct w6692_hw *card)
1214*4882a593Smuzhiyun {
1215*4882a593Smuzhiyun 	u32	val;
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun 	if (!request_region(card->addr, 256, card->name)) {
1218*4882a593Smuzhiyun 		pr_info("%s: config port %x-%x already in use\n", card->name,
1219*4882a593Smuzhiyun 			card->addr, card->addr + 255);
1220*4882a593Smuzhiyun 		return -EIO;
1221*4882a593Smuzhiyun 	}
1222*4882a593Smuzhiyun 	W6692Version(card);
1223*4882a593Smuzhiyun 	card->bc[0].addr = card->addr;
1224*4882a593Smuzhiyun 	card->bc[1].addr = card->addr + 0x40;
1225*4882a593Smuzhiyun 	val = ReadW6692(card, W_ISTA);
1226*4882a593Smuzhiyun 	if (debug & DEBUG_HW)
1227*4882a593Smuzhiyun 		pr_notice("%s ISTA=%02x\n", card->name, val);
1228*4882a593Smuzhiyun 	val = ReadW6692(card, W_IMASK);
1229*4882a593Smuzhiyun 	if (debug & DEBUG_HW)
1230*4882a593Smuzhiyun 		pr_notice("%s IMASK=%02x\n", card->name, val);
1231*4882a593Smuzhiyun 	val = ReadW6692(card, W_D_EXIR);
1232*4882a593Smuzhiyun 	if (debug & DEBUG_HW)
1233*4882a593Smuzhiyun 		pr_notice("%s D_EXIR=%02x\n", card->name, val);
1234*4882a593Smuzhiyun 	val = ReadW6692(card, W_D_EXIM);
1235*4882a593Smuzhiyun 	if (debug & DEBUG_HW)
1236*4882a593Smuzhiyun 		pr_notice("%s D_EXIM=%02x\n", card->name, val);
1237*4882a593Smuzhiyun 	val = ReadW6692(card, W_D_RSTA);
1238*4882a593Smuzhiyun 	if (debug & DEBUG_HW)
1239*4882a593Smuzhiyun 		pr_notice("%s D_RSTA=%02x\n", card->name, val);
1240*4882a593Smuzhiyun 	return 0;
1241*4882a593Smuzhiyun }
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun static void
release_card(struct w6692_hw * card)1244*4882a593Smuzhiyun release_card(struct w6692_hw *card)
1245*4882a593Smuzhiyun {
1246*4882a593Smuzhiyun 	u_long	flags;
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun 	spin_lock_irqsave(&card->lock, flags);
1249*4882a593Smuzhiyun 	disable_hwirq(card);
1250*4882a593Smuzhiyun 	w6692_mode(&card->bc[0], ISDN_P_NONE);
1251*4882a593Smuzhiyun 	w6692_mode(&card->bc[1], ISDN_P_NONE);
1252*4882a593Smuzhiyun 	if ((card->fmask & led) || card->subtype == W6692_USR) {
1253*4882a593Smuzhiyun 		card->xdata |= 0x04;	/*  LED OFF */
1254*4882a593Smuzhiyun 		WriteW6692(card, W_XDATA, card->xdata);
1255*4882a593Smuzhiyun 	}
1256*4882a593Smuzhiyun 	spin_unlock_irqrestore(&card->lock, flags);
1257*4882a593Smuzhiyun 	free_irq(card->irq, card);
1258*4882a593Smuzhiyun 	l1_event(card->dch.l1, CLOSE_CHANNEL);
1259*4882a593Smuzhiyun 	mISDN_unregister_device(&card->dch.dev);
1260*4882a593Smuzhiyun 	release_region(card->addr, 256);
1261*4882a593Smuzhiyun 	mISDN_freebchannel(&card->bc[1].bch);
1262*4882a593Smuzhiyun 	mISDN_freebchannel(&card->bc[0].bch);
1263*4882a593Smuzhiyun 	mISDN_freedchannel(&card->dch);
1264*4882a593Smuzhiyun 	write_lock_irqsave(&card_lock, flags);
1265*4882a593Smuzhiyun 	list_del(&card->list);
1266*4882a593Smuzhiyun 	write_unlock_irqrestore(&card_lock, flags);
1267*4882a593Smuzhiyun 	pci_disable_device(card->pdev);
1268*4882a593Smuzhiyun 	pci_set_drvdata(card->pdev, NULL);
1269*4882a593Smuzhiyun 	kfree(card);
1270*4882a593Smuzhiyun }
1271*4882a593Smuzhiyun 
1272*4882a593Smuzhiyun static int
setup_instance(struct w6692_hw * card)1273*4882a593Smuzhiyun setup_instance(struct w6692_hw *card)
1274*4882a593Smuzhiyun {
1275*4882a593Smuzhiyun 	int		i, err;
1276*4882a593Smuzhiyun 	u_long		flags;
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	snprintf(card->name, MISDN_MAX_IDLEN - 1, "w6692.%d", w6692_cnt + 1);
1279*4882a593Smuzhiyun 	write_lock_irqsave(&card_lock, flags);
1280*4882a593Smuzhiyun 	list_add_tail(&card->list, &Cards);
1281*4882a593Smuzhiyun 	write_unlock_irqrestore(&card_lock, flags);
1282*4882a593Smuzhiyun 	card->fmask = (1 << w6692_cnt);
1283*4882a593Smuzhiyun 	_set_debug(card);
1284*4882a593Smuzhiyun 	spin_lock_init(&card->lock);
1285*4882a593Smuzhiyun 	mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, W6692_ph_bh);
1286*4882a593Smuzhiyun 	card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
1287*4882a593Smuzhiyun 	card->dch.dev.D.send = w6692_l2l1D;
1288*4882a593Smuzhiyun 	card->dch.dev.D.ctrl = w6692_dctrl;
1289*4882a593Smuzhiyun 	card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1290*4882a593Smuzhiyun 		(1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1291*4882a593Smuzhiyun 	card->dch.hw = card;
1292*4882a593Smuzhiyun 	card->dch.dev.nrbchan = 2;
1293*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
1294*4882a593Smuzhiyun 		mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM,
1295*4882a593Smuzhiyun 				   W_B_FIFO_THRESH);
1296*4882a593Smuzhiyun 		card->bc[i].bch.hw = card;
1297*4882a593Smuzhiyun 		card->bc[i].bch.nr = i + 1;
1298*4882a593Smuzhiyun 		card->bc[i].bch.ch.nr = i + 1;
1299*4882a593Smuzhiyun 		card->bc[i].bch.ch.send = w6692_l2l1B;
1300*4882a593Smuzhiyun 		card->bc[i].bch.ch.ctrl = w6692_bctrl;
1301*4882a593Smuzhiyun 		set_channelmap(i + 1, card->dch.dev.channelmap);
1302*4882a593Smuzhiyun 		list_add(&card->bc[i].bch.ch.list, &card->dch.dev.bchannels);
1303*4882a593Smuzhiyun 	}
1304*4882a593Smuzhiyun 	err = setup_w6692(card);
1305*4882a593Smuzhiyun 	if (err)
1306*4882a593Smuzhiyun 		goto error_setup;
1307*4882a593Smuzhiyun 	err = mISDN_register_device(&card->dch.dev, &card->pdev->dev,
1308*4882a593Smuzhiyun 				    card->name);
1309*4882a593Smuzhiyun 	if (err)
1310*4882a593Smuzhiyun 		goto error_reg;
1311*4882a593Smuzhiyun 	err = init_card(card);
1312*4882a593Smuzhiyun 	if (err)
1313*4882a593Smuzhiyun 		goto error_init;
1314*4882a593Smuzhiyun 	err = create_l1(&card->dch, w6692_l1callback);
1315*4882a593Smuzhiyun 	if (!err) {
1316*4882a593Smuzhiyun 		w6692_cnt++;
1317*4882a593Smuzhiyun 		pr_notice("W6692 %d cards installed\n", w6692_cnt);
1318*4882a593Smuzhiyun 		return 0;
1319*4882a593Smuzhiyun 	}
1320*4882a593Smuzhiyun 
1321*4882a593Smuzhiyun 	free_irq(card->irq, card);
1322*4882a593Smuzhiyun error_init:
1323*4882a593Smuzhiyun 	mISDN_unregister_device(&card->dch.dev);
1324*4882a593Smuzhiyun error_reg:
1325*4882a593Smuzhiyun 	release_region(card->addr, 256);
1326*4882a593Smuzhiyun error_setup:
1327*4882a593Smuzhiyun 	mISDN_freebchannel(&card->bc[1].bch);
1328*4882a593Smuzhiyun 	mISDN_freebchannel(&card->bc[0].bch);
1329*4882a593Smuzhiyun 	mISDN_freedchannel(&card->dch);
1330*4882a593Smuzhiyun 	write_lock_irqsave(&card_lock, flags);
1331*4882a593Smuzhiyun 	list_del(&card->list);
1332*4882a593Smuzhiyun 	write_unlock_irqrestore(&card_lock, flags);
1333*4882a593Smuzhiyun 	kfree(card);
1334*4882a593Smuzhiyun 	return err;
1335*4882a593Smuzhiyun }
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun static int
w6692_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1338*4882a593Smuzhiyun w6692_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1339*4882a593Smuzhiyun {
1340*4882a593Smuzhiyun 	int		err = -ENOMEM;
1341*4882a593Smuzhiyun 	struct w6692_hw	*card;
1342*4882a593Smuzhiyun 	struct w6692map	*m = (struct w6692map *)ent->driver_data;
1343*4882a593Smuzhiyun 
1344*4882a593Smuzhiyun 	card = kzalloc(sizeof(struct w6692_hw), GFP_KERNEL);
1345*4882a593Smuzhiyun 	if (!card) {
1346*4882a593Smuzhiyun 		pr_info("No kmem for w6692 card\n");
1347*4882a593Smuzhiyun 		return err;
1348*4882a593Smuzhiyun 	}
1349*4882a593Smuzhiyun 	card->pdev = pdev;
1350*4882a593Smuzhiyun 	card->subtype = m->subtype;
1351*4882a593Smuzhiyun 	err = pci_enable_device(pdev);
1352*4882a593Smuzhiyun 	if (err) {
1353*4882a593Smuzhiyun 		kfree(card);
1354*4882a593Smuzhiyun 		return err;
1355*4882a593Smuzhiyun 	}
1356*4882a593Smuzhiyun 
1357*4882a593Smuzhiyun 	printk(KERN_INFO "mISDN_w6692: found adapter %s at %s\n",
1358*4882a593Smuzhiyun 	       m->name, pci_name(pdev));
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	card->addr = pci_resource_start(pdev, 1);
1361*4882a593Smuzhiyun 	card->irq = pdev->irq;
1362*4882a593Smuzhiyun 	pci_set_drvdata(pdev, card);
1363*4882a593Smuzhiyun 	err = setup_instance(card);
1364*4882a593Smuzhiyun 	if (err)
1365*4882a593Smuzhiyun 		pci_set_drvdata(pdev, NULL);
1366*4882a593Smuzhiyun 	return err;
1367*4882a593Smuzhiyun }
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun static void
w6692_remove_pci(struct pci_dev * pdev)1370*4882a593Smuzhiyun w6692_remove_pci(struct pci_dev *pdev)
1371*4882a593Smuzhiyun {
1372*4882a593Smuzhiyun 	struct w6692_hw	*card = pci_get_drvdata(pdev);
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun 	if (card)
1375*4882a593Smuzhiyun 		release_card(card);
1376*4882a593Smuzhiyun 	else
1377*4882a593Smuzhiyun 		if (debug)
1378*4882a593Smuzhiyun 			pr_notice("%s: drvdata already removed\n", __func__);
1379*4882a593Smuzhiyun }
1380*4882a593Smuzhiyun 
1381*4882a593Smuzhiyun static const struct pci_device_id w6692_ids[] = {
1382*4882a593Smuzhiyun 	{ PCI_VENDOR_ID_DYNALINK, PCI_DEVICE_ID_DYNALINK_IS64PH,
1383*4882a593Smuzhiyun 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, (ulong)&w6692_map[0]},
1384*4882a593Smuzhiyun 	{ PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692,
1385*4882a593Smuzhiyun 	  PCI_VENDOR_ID_USR, PCI_DEVICE_ID_USR_6692, 0, 0,
1386*4882a593Smuzhiyun 	  (ulong)&w6692_map[2]},
1387*4882a593Smuzhiyun 	{ PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692,
1388*4882a593Smuzhiyun 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, (ulong)&w6692_map[1]},
1389*4882a593Smuzhiyun 	{ }
1390*4882a593Smuzhiyun };
1391*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, w6692_ids);
1392*4882a593Smuzhiyun 
1393*4882a593Smuzhiyun static struct pci_driver w6692_driver = {
1394*4882a593Smuzhiyun 	.name =  "w6692",
1395*4882a593Smuzhiyun 	.probe = w6692_probe,
1396*4882a593Smuzhiyun 	.remove = w6692_remove_pci,
1397*4882a593Smuzhiyun 	.id_table = w6692_ids,
1398*4882a593Smuzhiyun };
1399*4882a593Smuzhiyun 
w6692_init(void)1400*4882a593Smuzhiyun static int __init w6692_init(void)
1401*4882a593Smuzhiyun {
1402*4882a593Smuzhiyun 	int err;
1403*4882a593Smuzhiyun 
1404*4882a593Smuzhiyun 	pr_notice("Winbond W6692 PCI driver Rev. %s\n", W6692_REV);
1405*4882a593Smuzhiyun 
1406*4882a593Smuzhiyun 	err = pci_register_driver(&w6692_driver);
1407*4882a593Smuzhiyun 	return err;
1408*4882a593Smuzhiyun }
1409*4882a593Smuzhiyun 
w6692_cleanup(void)1410*4882a593Smuzhiyun static void __exit w6692_cleanup(void)
1411*4882a593Smuzhiyun {
1412*4882a593Smuzhiyun 	pci_unregister_driver(&w6692_driver);
1413*4882a593Smuzhiyun }
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun module_init(w6692_init);
1416*4882a593Smuzhiyun module_exit(w6692_cleanup);
1417