xref: /OK3568_Linux_fs/kernel/drivers/isdn/hardware/mISDN/netjet.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * NETjet common header file
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author	Karsten Keil
6*4882a593Smuzhiyun  *              based on work of Matt Henderson and Daniel Potts,
7*4882a593Smuzhiyun  *              Traverse Technologies P/L www.traverse.com.au
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright 2009  by Karsten Keil <keil@isdn4linux.de>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define NJ_CTRL			0x00
13*4882a593Smuzhiyun #define NJ_DMACTRL		0x01
14*4882a593Smuzhiyun #define NJ_AUXCTRL		0x02
15*4882a593Smuzhiyun #define NJ_AUXDATA		0x03
16*4882a593Smuzhiyun #define NJ_IRQMASK0		0x04
17*4882a593Smuzhiyun #define NJ_IRQMASK1		0x05
18*4882a593Smuzhiyun #define NJ_IRQSTAT0		0x06
19*4882a593Smuzhiyun #define NJ_IRQSTAT1		0x07
20*4882a593Smuzhiyun #define NJ_DMA_READ_START	0x08
21*4882a593Smuzhiyun #define NJ_DMA_READ_IRQ		0x0c
22*4882a593Smuzhiyun #define NJ_DMA_READ_END		0x10
23*4882a593Smuzhiyun #define NJ_DMA_READ_ADR		0x14
24*4882a593Smuzhiyun #define NJ_DMA_WRITE_START	0x18
25*4882a593Smuzhiyun #define NJ_DMA_WRITE_IRQ	0x1c
26*4882a593Smuzhiyun #define NJ_DMA_WRITE_END	0x20
27*4882a593Smuzhiyun #define NJ_DMA_WRITE_ADR	0x24
28*4882a593Smuzhiyun #define NJ_PULSE_CNT		0x28
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define NJ_ISAC_OFF		0xc0
31*4882a593Smuzhiyun #define NJ_ISACIRQ		0x10
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define NJ_IRQM0_RD_MASK	0x03
34*4882a593Smuzhiyun #define NJ_IRQM0_RD_IRQ		0x01
35*4882a593Smuzhiyun #define NJ_IRQM0_RD_END		0x02
36*4882a593Smuzhiyun #define NJ_IRQM0_WR_MASK	0x0c
37*4882a593Smuzhiyun #define NJ_IRQM0_WR_IRQ		0x04
38*4882a593Smuzhiyun #define NJ_IRQM0_WR_END		0x08
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /* one page here is no need to be smaller */
41*4882a593Smuzhiyun #define NJ_DMA_SIZE		4096
42*4882a593Smuzhiyun /* 2 * 64 byte is a compromise between IRQ count and latency */
43*4882a593Smuzhiyun #define NJ_DMA_RXSIZE		128  /* 2 * 64 */
44*4882a593Smuzhiyun #define NJ_DMA_TXSIZE		128  /* 2 * 64 */
45