1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/err.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/irqchip.h>
11 #include <linux/irqdomain.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/soc/qcom/irq.h>
20 #include <linux/spinlock.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23
24 #include <linux/qcom_scm.h>
25
26 #define PDC_MAX_IRQS 168
27 #define PDC_MAX_GPIO_IRQS 256
28
29 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
30 #define ENABLE_INTR(reg, intr) (reg | (1 << intr))
31
32 #define IRQ_ENABLE_BANK 0x10
33 #define IRQ_i_CFG 0x110
34
35 #define PDC_NO_PARENT_IRQ ~0UL
36
37 struct pdc_pin_region {
38 u32 pin_base;
39 u32 parent_base;
40 u32 cnt;
41 };
42
43 struct spi_cfg_regs {
44 union {
45 u64 start;
46 void __iomem *base;
47 };
48 resource_size_t size;
49 bool scm_io;
50 };
51
52 static DEFINE_RAW_SPINLOCK(pdc_lock);
53 static void __iomem *pdc_base;
54 static struct pdc_pin_region *pdc_region;
55 static int pdc_region_cnt;
56 static struct spi_cfg_regs *spi_cfg;
57
pdc_reg_write(int reg,u32 i,u32 val)58 static void pdc_reg_write(int reg, u32 i, u32 val)
59 {
60 writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
61 }
62
pdc_reg_read(int reg,u32 i)63 static u32 pdc_reg_read(int reg, u32 i)
64 {
65 return readl_relaxed(pdc_base + reg + i * sizeof(u32));
66 }
67
pdc_enable_intr(struct irq_data * d,bool on)68 static void pdc_enable_intr(struct irq_data *d, bool on)
69 {
70 int pin_out = d->hwirq;
71 unsigned long flags;
72 u32 index, mask;
73 u32 enable;
74
75 index = pin_out / 32;
76 mask = pin_out % 32;
77
78 raw_spin_lock_irqsave(&pdc_lock, flags);
79 enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
80 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
81 pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
82 raw_spin_unlock_irqrestore(&pdc_lock, flags);
83 }
84
qcom_pdc_gic_disable(struct irq_data * d)85 static void qcom_pdc_gic_disable(struct irq_data *d)
86 {
87 pdc_enable_intr(d, false);
88 irq_chip_disable_parent(d);
89 }
90
qcom_pdc_gic_enable(struct irq_data * d)91 static void qcom_pdc_gic_enable(struct irq_data *d)
92 {
93 pdc_enable_intr(d, true);
94 irq_chip_enable_parent(d);
95 }
96
__spi_pin_read(unsigned int pin)97 static u32 __spi_pin_read(unsigned int pin)
98 {
99 void __iomem *cfg_reg = spi_cfg->base + pin * 4;
100 u64 scm_cfg_reg = spi_cfg->start + pin * 4;
101
102 if (spi_cfg->scm_io) {
103 unsigned int val;
104
105 qcom_scm_io_readl(scm_cfg_reg, &val);
106 return val;
107 } else {
108 return readl(cfg_reg);
109 }
110 }
111
__spi_pin_write(unsigned int pin,unsigned int val)112 static void __spi_pin_write(unsigned int pin, unsigned int val)
113 {
114 void __iomem *cfg_reg = spi_cfg->base + pin * 4;
115 u64 scm_cfg_reg = spi_cfg->start + pin * 4;
116
117 if (spi_cfg->scm_io)
118 qcom_scm_io_writel(scm_cfg_reg, val);
119 else
120 writel(val, cfg_reg);
121 }
122
spi_configure_type(irq_hw_number_t hwirq,unsigned int type)123 static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type)
124 {
125 int spi = hwirq - 32;
126 u32 pin = spi / 32;
127 u32 mask = BIT(spi % 32);
128 u32 val;
129 unsigned long flags;
130
131 if (!spi_cfg)
132 return 0;
133
134 if (pin * 4 > spi_cfg->size)
135 return -EFAULT;
136
137 raw_spin_lock_irqsave(&pdc_lock, flags);
138 val = __spi_pin_read(pin);
139 val &= ~mask;
140 if (type & IRQ_TYPE_LEVEL_MASK)
141 val |= mask;
142 __spi_pin_write(pin, val);
143 raw_spin_unlock_irqrestore(&pdc_lock, flags);
144
145 return 0;
146 }
147
148 /*
149 * GIC does not handle falling edge or active low. To allow falling edge and
150 * active low interrupts to be handled at GIC, PDC has an inverter that inverts
151 * falling edge into a rising edge and active low into an active high.
152 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
153 * set as per the table below.
154 * Level sensitive active low LOW
155 * Rising edge sensitive NOT USED
156 * Falling edge sensitive LOW
157 * Dual Edge sensitive NOT USED
158 * Level sensitive active High HIGH
159 * Falling Edge sensitive NOT USED
160 * Rising edge sensitive HIGH
161 * Dual Edge sensitive HIGH
162 */
163 enum pdc_irq_config_bits {
164 PDC_LEVEL_LOW = 0b000,
165 PDC_EDGE_FALLING = 0b010,
166 PDC_LEVEL_HIGH = 0b100,
167 PDC_EDGE_RISING = 0b110,
168 PDC_EDGE_DUAL = 0b111,
169 };
170
171 /**
172 * qcom_pdc_gic_set_type: Configure PDC for the interrupt
173 *
174 * @d: the interrupt data
175 * @type: the interrupt type
176 *
177 * If @type is edge triggered, forward that as Rising edge as PDC
178 * takes care of converting falling edge to rising edge signal
179 * If @type is level, then forward that as level high as PDC
180 * takes care of converting falling edge to rising edge signal
181 */
qcom_pdc_gic_set_type(struct irq_data * d,unsigned int type)182 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
183 {
184 int parent_hwirq = d->parent_data->hwirq;
185 enum pdc_irq_config_bits pdc_type;
186 enum pdc_irq_config_bits old_pdc_type;
187 int ret;
188
189 switch (type) {
190 case IRQ_TYPE_EDGE_RISING:
191 pdc_type = PDC_EDGE_RISING;
192 break;
193 case IRQ_TYPE_EDGE_FALLING:
194 pdc_type = PDC_EDGE_FALLING;
195 type = IRQ_TYPE_EDGE_RISING;
196 break;
197 case IRQ_TYPE_EDGE_BOTH:
198 pdc_type = PDC_EDGE_DUAL;
199 type = IRQ_TYPE_EDGE_RISING;
200 break;
201 case IRQ_TYPE_LEVEL_HIGH:
202 pdc_type = PDC_LEVEL_HIGH;
203 break;
204 case IRQ_TYPE_LEVEL_LOW:
205 pdc_type = PDC_LEVEL_LOW;
206 type = IRQ_TYPE_LEVEL_HIGH;
207 break;
208 default:
209 WARN_ON(1);
210 return -EINVAL;
211 }
212
213 old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
214 pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
215
216 /* Additionally, configure (only) the GPIO in the f/w */
217 ret = spi_configure_type(parent_hwirq, type);
218 if (ret)
219 return ret;
220
221 ret = irq_chip_set_type_parent(d, type);
222 if (ret)
223 return ret;
224
225 /*
226 * When we change types the PDC can give a phantom interrupt.
227 * Clear it. Specifically the phantom shows up when reconfiguring
228 * polarity of interrupt without changing the state of the signal
229 * but let's be consistent and clear it always.
230 *
231 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
232 * interrupt will be cleared before the rest of the system sees it.
233 */
234 if (old_pdc_type != pdc_type)
235 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
236
237 return 0;
238 }
239
240 static struct irq_chip qcom_pdc_gic_chip = {
241 .name = "PDC",
242 .irq_eoi = irq_chip_eoi_parent,
243 .irq_mask = irq_chip_mask_parent,
244 .irq_unmask = irq_chip_unmask_parent,
245 .irq_disable = qcom_pdc_gic_disable,
246 .irq_enable = qcom_pdc_gic_enable,
247 .irq_get_irqchip_state = irq_chip_get_parent_state,
248 .irq_set_irqchip_state = irq_chip_set_parent_state,
249 .irq_retrigger = irq_chip_retrigger_hierarchy,
250 .irq_set_type = qcom_pdc_gic_set_type,
251 .flags = IRQCHIP_MASK_ON_SUSPEND |
252 IRQCHIP_SET_TYPE_MASKED |
253 IRQCHIP_SKIP_SET_WAKE |
254 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
255 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
256 .irq_set_affinity = irq_chip_set_affinity_parent,
257 };
258
get_parent_hwirq(int pin)259 static irq_hw_number_t get_parent_hwirq(int pin)
260 {
261 int i;
262 struct pdc_pin_region *region;
263
264 for (i = 0; i < pdc_region_cnt; i++) {
265 region = &pdc_region[i];
266 if (pin >= region->pin_base &&
267 pin < region->pin_base + region->cnt)
268 return (region->parent_base + pin - region->pin_base);
269 }
270
271 return PDC_NO_PARENT_IRQ;
272 }
273
qcom_pdc_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)274 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
275 unsigned long *hwirq, unsigned int *type)
276 {
277 if (is_of_node(fwspec->fwnode)) {
278 if (fwspec->param_count != 2)
279 return -EINVAL;
280
281 *hwirq = fwspec->param[0];
282 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
283 return 0;
284 }
285
286 return -EINVAL;
287 }
288
qcom_pdc_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)289 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
290 unsigned int nr_irqs, void *data)
291 {
292 struct irq_fwspec *fwspec = data;
293 struct irq_fwspec parent_fwspec;
294 irq_hw_number_t hwirq, parent_hwirq;
295 unsigned int type;
296 int ret;
297
298 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
299 if (ret)
300 return ret;
301
302 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
303 &qcom_pdc_gic_chip, NULL);
304 if (ret)
305 return ret;
306
307 parent_hwirq = get_parent_hwirq(hwirq);
308 if (parent_hwirq == PDC_NO_PARENT_IRQ)
309 return irq_domain_disconnect_hierarchy(domain->parent, virq);
310
311 if (type & IRQ_TYPE_EDGE_BOTH)
312 type = IRQ_TYPE_EDGE_RISING;
313
314 if (type & IRQ_TYPE_LEVEL_MASK)
315 type = IRQ_TYPE_LEVEL_HIGH;
316
317 parent_fwspec.fwnode = domain->parent->fwnode;
318 parent_fwspec.param_count = 3;
319 parent_fwspec.param[0] = 0;
320 parent_fwspec.param[1] = parent_hwirq;
321 parent_fwspec.param[2] = type;
322
323 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
324 &parent_fwspec);
325 }
326
327 static const struct irq_domain_ops qcom_pdc_ops = {
328 .translate = qcom_pdc_translate,
329 .alloc = qcom_pdc_alloc,
330 .free = irq_domain_free_irqs_common,
331 };
332
qcom_pdc_gpio_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)333 static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
334 unsigned int nr_irqs, void *data)
335 {
336 struct irq_fwspec *fwspec = data;
337 struct irq_fwspec parent_fwspec;
338 irq_hw_number_t hwirq, parent_hwirq;
339 unsigned int type;
340 int ret;
341
342 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
343 if (ret)
344 return ret;
345
346 if (hwirq == GPIO_NO_WAKE_IRQ)
347 return irq_domain_disconnect_hierarchy(domain, virq);
348
349 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
350 &qcom_pdc_gic_chip, NULL);
351 if (ret)
352 return ret;
353
354 parent_hwirq = get_parent_hwirq(hwirq);
355 if (parent_hwirq == PDC_NO_PARENT_IRQ)
356 return irq_domain_disconnect_hierarchy(domain->parent, virq);
357
358 if (type & IRQ_TYPE_EDGE_BOTH)
359 type = IRQ_TYPE_EDGE_RISING;
360
361 if (type & IRQ_TYPE_LEVEL_MASK)
362 type = IRQ_TYPE_LEVEL_HIGH;
363
364 parent_fwspec.fwnode = domain->parent->fwnode;
365 parent_fwspec.param_count = 3;
366 parent_fwspec.param[0] = 0;
367 parent_fwspec.param[1] = parent_hwirq;
368 parent_fwspec.param[2] = type;
369
370 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
371 &parent_fwspec);
372 }
373
qcom_pdc_gpio_domain_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)374 static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
375 struct irq_fwspec *fwspec,
376 enum irq_domain_bus_token bus_token)
377 {
378 return bus_token == DOMAIN_BUS_WAKEUP;
379 }
380
381 static const struct irq_domain_ops qcom_pdc_gpio_ops = {
382 .select = qcom_pdc_gpio_domain_select,
383 .alloc = qcom_pdc_gpio_alloc,
384 .free = irq_domain_free_irqs_common,
385 };
386
pdc_setup_pin_mapping(struct device_node * np)387 static int pdc_setup_pin_mapping(struct device_node *np)
388 {
389 int ret, n, i;
390 u32 irq_index, reg_index, val;
391
392 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
393 if (n <= 0 || n % 3)
394 return -EINVAL;
395
396 pdc_region_cnt = n / 3;
397 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
398 if (!pdc_region) {
399 pdc_region_cnt = 0;
400 return -ENOMEM;
401 }
402
403 for (n = 0; n < pdc_region_cnt; n++) {
404 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
405 n * 3 + 0,
406 &pdc_region[n].pin_base);
407 if (ret)
408 return ret;
409 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
410 n * 3 + 1,
411 &pdc_region[n].parent_base);
412 if (ret)
413 return ret;
414 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
415 n * 3 + 2,
416 &pdc_region[n].cnt);
417 if (ret)
418 return ret;
419
420 for (i = 0; i < pdc_region[n].cnt; i++) {
421 reg_index = (i + pdc_region[n].pin_base) >> 5;
422 irq_index = (i + pdc_region[n].pin_base) & 0x1f;
423 val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
424 val &= ~BIT(irq_index);
425 pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
426 }
427 }
428
429 return 0;
430 }
431
qcom_pdc_init(struct device_node * node,struct device_node * parent)432 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
433 {
434 struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
435 struct resource res;
436 int ret;
437
438 pdc_base = of_iomap(node, 0);
439 if (!pdc_base) {
440 pr_err("%pOF: unable to map PDC registers\n", node);
441 return -ENXIO;
442 }
443
444 parent_domain = irq_find_host(parent);
445 if (!parent_domain) {
446 pr_err("%pOF: unable to find PDC's parent domain\n", node);
447 ret = -ENXIO;
448 goto fail;
449 }
450
451 ret = pdc_setup_pin_mapping(node);
452 if (ret) {
453 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
454 goto fail;
455 }
456
457 pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
458 of_fwnode_handle(node),
459 &qcom_pdc_ops, NULL);
460 if (!pdc_domain) {
461 pr_err("%pOF: GIC domain add failed\n", node);
462 ret = -ENOMEM;
463 goto fail;
464 }
465
466 ret = of_address_to_resource(node, 1, &res);
467 if (!ret) {
468 spi_cfg = kcalloc(1, sizeof(*spi_cfg), GFP_KERNEL);
469 if (!spi_cfg) {
470 ret = -ENOMEM;
471 goto remove;
472 }
473 spi_cfg->scm_io = of_find_property(node,
474 "qcom,scm-spi-cfg", NULL);
475 spi_cfg->size = resource_size(&res);
476 if (spi_cfg->scm_io) {
477 spi_cfg->start = res.start;
478 } else {
479 spi_cfg->base = ioremap(res.start, spi_cfg->size);
480 if (!spi_cfg->base) {
481 ret = -ENOMEM;
482 goto remove;
483 }
484 }
485 }
486
487 pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
488 IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
489 PDC_MAX_GPIO_IRQS,
490 of_fwnode_handle(node),
491 &qcom_pdc_gpio_ops, NULL);
492 if (!pdc_gpio_domain) {
493 pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
494 ret = -ENOMEM;
495 goto remove;
496 }
497
498 irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
499
500 return 0;
501
502 remove:
503 irq_domain_remove(pdc_domain);
504 kfree(spi_cfg);
505 fail:
506 kfree(pdc_region);
507 iounmap(pdc_base);
508 return ret;
509 }
510
qcom_pdc_probe(struct platform_device * pdev)511 static int qcom_pdc_probe(struct platform_device *pdev)
512 {
513 struct device_node *np = pdev->dev.of_node;
514 struct device_node *parent = of_irq_find_parent(np);
515
516 return qcom_pdc_init(np, parent);
517 }
518
519 static const struct of_device_id qcom_pdc_match_table[] = {
520 { .compatible = "qcom,pdc" },
521 {}
522 };
523 MODULE_DEVICE_TABLE(of, qcom_pdc_match_table);
524
525 static struct platform_driver qcom_pdc_driver = {
526 .probe = qcom_pdc_probe,
527 .driver = {
528 .name = "qcom-pdc",
529 .of_match_table = qcom_pdc_match_table,
530 .suppress_bind_attrs = true,
531 },
532 };
533 module_platform_driver(qcom_pdc_driver);
534 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
535 MODULE_LICENSE("GPL v2");
536