1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Xtensa built-in interrupt controller
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2002 - 2013 Tensilica, Inc.
5*4882a593Smuzhiyun * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
8*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
9*4882a593Smuzhiyun * for more details.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Chris Zankel <chris@zankel.net>
12*4882a593Smuzhiyun * Kevin Chea
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/irqdomain.h>
17*4882a593Smuzhiyun #include <linux/irq.h>
18*4882a593Smuzhiyun #include <linux/irqchip.h>
19*4882a593Smuzhiyun #include <linux/of.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun unsigned int cached_irq_mask;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * Device Tree IRQ specifier translation function which works with one or
25*4882a593Smuzhiyun * two cell bindings. First cell value maps directly to the hwirq number.
26*4882a593Smuzhiyun * Second cell if present specifies whether hwirq number is external (1) or
27*4882a593Smuzhiyun * internal (0).
28*4882a593Smuzhiyun */
xtensa_pic_irq_domain_xlate(struct irq_domain * d,struct device_node * ctrlr,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)29*4882a593Smuzhiyun static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
30*4882a593Smuzhiyun struct device_node *ctrlr,
31*4882a593Smuzhiyun const u32 *intspec, unsigned int intsize,
32*4882a593Smuzhiyun unsigned long *out_hwirq, unsigned int *out_type)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun return xtensa_irq_domain_xlate(intspec, intsize,
35*4882a593Smuzhiyun intspec[0], intspec[0],
36*4882a593Smuzhiyun out_hwirq, out_type);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static const struct irq_domain_ops xtensa_irq_domain_ops = {
40*4882a593Smuzhiyun .xlate = xtensa_pic_irq_domain_xlate,
41*4882a593Smuzhiyun .map = xtensa_irq_map,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
xtensa_irq_mask(struct irq_data * d)44*4882a593Smuzhiyun static void xtensa_irq_mask(struct irq_data *d)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun cached_irq_mask &= ~(1 << d->hwirq);
47*4882a593Smuzhiyun xtensa_set_sr(cached_irq_mask, intenable);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
xtensa_irq_unmask(struct irq_data * d)50*4882a593Smuzhiyun static void xtensa_irq_unmask(struct irq_data *d)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun cached_irq_mask |= 1 << d->hwirq;
53*4882a593Smuzhiyun xtensa_set_sr(cached_irq_mask, intenable);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
xtensa_irq_enable(struct irq_data * d)56*4882a593Smuzhiyun static void xtensa_irq_enable(struct irq_data *d)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun xtensa_irq_unmask(d);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
xtensa_irq_disable(struct irq_data * d)61*4882a593Smuzhiyun static void xtensa_irq_disable(struct irq_data *d)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun xtensa_irq_mask(d);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
xtensa_irq_ack(struct irq_data * d)66*4882a593Smuzhiyun static void xtensa_irq_ack(struct irq_data *d)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun xtensa_set_sr(1 << d->hwirq, intclear);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
xtensa_irq_retrigger(struct irq_data * d)71*4882a593Smuzhiyun static int xtensa_irq_retrigger(struct irq_data *d)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun unsigned int mask = 1u << d->hwirq;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun xtensa_set_sr(mask, intset);
78*4882a593Smuzhiyun return 1;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static struct irq_chip xtensa_irq_chip = {
82*4882a593Smuzhiyun .name = "xtensa",
83*4882a593Smuzhiyun .irq_enable = xtensa_irq_enable,
84*4882a593Smuzhiyun .irq_disable = xtensa_irq_disable,
85*4882a593Smuzhiyun .irq_mask = xtensa_irq_mask,
86*4882a593Smuzhiyun .irq_unmask = xtensa_irq_unmask,
87*4882a593Smuzhiyun .irq_ack = xtensa_irq_ack,
88*4882a593Smuzhiyun .irq_retrigger = xtensa_irq_retrigger,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
xtensa_pic_init_legacy(struct device_node * interrupt_parent)91*4882a593Smuzhiyun int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct irq_domain *root_domain =
94*4882a593Smuzhiyun irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
95*4882a593Smuzhiyun &xtensa_irq_domain_ops, &xtensa_irq_chip);
96*4882a593Smuzhiyun irq_set_default_host(root_domain);
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
xtensa_pic_init(struct device_node * np,struct device_node * interrupt_parent)100*4882a593Smuzhiyun static int __init xtensa_pic_init(struct device_node *np,
101*4882a593Smuzhiyun struct device_node *interrupt_parent)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct irq_domain *root_domain =
104*4882a593Smuzhiyun irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
105*4882a593Smuzhiyun &xtensa_irq_chip);
106*4882a593Smuzhiyun irq_set_default_host(root_domain);
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);
110