xref: /OK3568_Linux_fs/kernel/drivers/irqchip/irq-uniphier-aidet.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for UniPhier AIDET (ARM Interrupt Detector)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017 Socionext Inc.
6*4882a593Smuzhiyun  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/irqdomain.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/of_irq.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/spinlock.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define UNIPHIER_AIDET_NR_IRQS		256
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define UNIPHIER_AIDET_DETCONF		0x04	/* inverter register base */
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun struct uniphier_aidet_priv {
25*4882a593Smuzhiyun 	struct irq_domain *domain;
26*4882a593Smuzhiyun 	void __iomem *reg_base;
27*4882a593Smuzhiyun 	spinlock_t lock;
28*4882a593Smuzhiyun 	u32 saved_vals[UNIPHIER_AIDET_NR_IRQS / 32];
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
uniphier_aidet_reg_update(struct uniphier_aidet_priv * priv,unsigned int reg,u32 mask,u32 val)31*4882a593Smuzhiyun static void uniphier_aidet_reg_update(struct uniphier_aidet_priv *priv,
32*4882a593Smuzhiyun 				      unsigned int reg, u32 mask, u32 val)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	unsigned long flags;
35*4882a593Smuzhiyun 	u32 tmp;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	spin_lock_irqsave(&priv->lock, flags);
38*4882a593Smuzhiyun 	tmp = readl_relaxed(priv->reg_base + reg);
39*4882a593Smuzhiyun 	tmp &= ~mask;
40*4882a593Smuzhiyun 	tmp |= mask & val;
41*4882a593Smuzhiyun 	writel_relaxed(tmp, priv->reg_base + reg);
42*4882a593Smuzhiyun 	spin_unlock_irqrestore(&priv->lock, flags);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
uniphier_aidet_detconf_update(struct uniphier_aidet_priv * priv,unsigned long index,unsigned int val)45*4882a593Smuzhiyun static void uniphier_aidet_detconf_update(struct uniphier_aidet_priv *priv,
46*4882a593Smuzhiyun 					  unsigned long index, unsigned int val)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	unsigned int reg;
49*4882a593Smuzhiyun 	u32 mask;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	reg = UNIPHIER_AIDET_DETCONF + index / 32 * 4;
52*4882a593Smuzhiyun 	mask = BIT(index % 32);
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	uniphier_aidet_reg_update(priv, reg, mask, val ? mask : 0);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun 
uniphier_aidet_irq_set_type(struct irq_data * data,unsigned int type)57*4882a593Smuzhiyun static int uniphier_aidet_irq_set_type(struct irq_data *data, unsigned int type)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	struct uniphier_aidet_priv *priv = data->chip_data;
60*4882a593Smuzhiyun 	unsigned int val;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	/* enable inverter for active low triggers */
63*4882a593Smuzhiyun 	switch (type) {
64*4882a593Smuzhiyun 	case IRQ_TYPE_EDGE_RISING:
65*4882a593Smuzhiyun 	case IRQ_TYPE_LEVEL_HIGH:
66*4882a593Smuzhiyun 		val = 0;
67*4882a593Smuzhiyun 		break;
68*4882a593Smuzhiyun 	case IRQ_TYPE_EDGE_FALLING:
69*4882a593Smuzhiyun 		val = 1;
70*4882a593Smuzhiyun 		type = IRQ_TYPE_EDGE_RISING;
71*4882a593Smuzhiyun 		break;
72*4882a593Smuzhiyun 	case IRQ_TYPE_LEVEL_LOW:
73*4882a593Smuzhiyun 		val = 1;
74*4882a593Smuzhiyun 		type = IRQ_TYPE_LEVEL_HIGH;
75*4882a593Smuzhiyun 		break;
76*4882a593Smuzhiyun 	default:
77*4882a593Smuzhiyun 		return -EINVAL;
78*4882a593Smuzhiyun 	}
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	uniphier_aidet_detconf_update(priv, data->hwirq, val);
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	return irq_chip_set_type_parent(data, type);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun static struct irq_chip uniphier_aidet_irq_chip = {
86*4882a593Smuzhiyun 	.name = "AIDET",
87*4882a593Smuzhiyun 	.irq_mask = irq_chip_mask_parent,
88*4882a593Smuzhiyun 	.irq_unmask = irq_chip_unmask_parent,
89*4882a593Smuzhiyun 	.irq_eoi = irq_chip_eoi_parent,
90*4882a593Smuzhiyun 	.irq_set_affinity = irq_chip_set_affinity_parent,
91*4882a593Smuzhiyun 	.irq_set_type = uniphier_aidet_irq_set_type,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
uniphier_aidet_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * out_hwirq,unsigned int * out_type)94*4882a593Smuzhiyun static int uniphier_aidet_domain_translate(struct irq_domain *domain,
95*4882a593Smuzhiyun 					   struct irq_fwspec *fwspec,
96*4882a593Smuzhiyun 					   unsigned long *out_hwirq,
97*4882a593Smuzhiyun 					   unsigned int *out_type)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	if (WARN_ON(fwspec->param_count < 2))
100*4882a593Smuzhiyun 		return -EINVAL;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	*out_hwirq = fwspec->param[0];
103*4882a593Smuzhiyun 	*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	return 0;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun 
uniphier_aidet_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)108*4882a593Smuzhiyun static int uniphier_aidet_domain_alloc(struct irq_domain *domain,
109*4882a593Smuzhiyun 				       unsigned int virq, unsigned int nr_irqs,
110*4882a593Smuzhiyun 				       void *arg)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	struct irq_fwspec parent_fwspec;
113*4882a593Smuzhiyun 	irq_hw_number_t hwirq;
114*4882a593Smuzhiyun 	unsigned int type;
115*4882a593Smuzhiyun 	int ret;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	if (nr_irqs != 1)
118*4882a593Smuzhiyun 		return -EINVAL;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	ret = uniphier_aidet_domain_translate(domain, arg, &hwirq, &type);
121*4882a593Smuzhiyun 	if (ret)
122*4882a593Smuzhiyun 		return ret;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	switch (type) {
125*4882a593Smuzhiyun 	case IRQ_TYPE_EDGE_RISING:
126*4882a593Smuzhiyun 	case IRQ_TYPE_LEVEL_HIGH:
127*4882a593Smuzhiyun 		break;
128*4882a593Smuzhiyun 	case IRQ_TYPE_EDGE_FALLING:
129*4882a593Smuzhiyun 		type = IRQ_TYPE_EDGE_RISING;
130*4882a593Smuzhiyun 		break;
131*4882a593Smuzhiyun 	case IRQ_TYPE_LEVEL_LOW:
132*4882a593Smuzhiyun 		type = IRQ_TYPE_LEVEL_HIGH;
133*4882a593Smuzhiyun 		break;
134*4882a593Smuzhiyun 	default:
135*4882a593Smuzhiyun 		return -EINVAL;
136*4882a593Smuzhiyun 	}
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	if (hwirq >= UNIPHIER_AIDET_NR_IRQS)
139*4882a593Smuzhiyun 		return -ENXIO;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
142*4882a593Smuzhiyun 					    &uniphier_aidet_irq_chip,
143*4882a593Smuzhiyun 					    domain->host_data);
144*4882a593Smuzhiyun 	if (ret)
145*4882a593Smuzhiyun 		return ret;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/* parent is GIC */
148*4882a593Smuzhiyun 	parent_fwspec.fwnode = domain->parent->fwnode;
149*4882a593Smuzhiyun 	parent_fwspec.param_count = 3;
150*4882a593Smuzhiyun 	parent_fwspec.param[0] = 0;		/* SPI */
151*4882a593Smuzhiyun 	parent_fwspec.param[1] = hwirq;
152*4882a593Smuzhiyun 	parent_fwspec.param[2] = type;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static const struct irq_domain_ops uniphier_aidet_domain_ops = {
158*4882a593Smuzhiyun 	.alloc = uniphier_aidet_domain_alloc,
159*4882a593Smuzhiyun 	.free = irq_domain_free_irqs_common,
160*4882a593Smuzhiyun 	.translate = uniphier_aidet_domain_translate,
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
uniphier_aidet_probe(struct platform_device * pdev)163*4882a593Smuzhiyun static int uniphier_aidet_probe(struct platform_device *pdev)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
166*4882a593Smuzhiyun 	struct device_node *parent_np;
167*4882a593Smuzhiyun 	struct irq_domain *parent_domain;
168*4882a593Smuzhiyun 	struct uniphier_aidet_priv *priv;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	parent_np = of_irq_find_parent(dev->of_node);
171*4882a593Smuzhiyun 	if (!parent_np)
172*4882a593Smuzhiyun 		return -ENXIO;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	parent_domain = irq_find_host(parent_np);
175*4882a593Smuzhiyun 	of_node_put(parent_np);
176*4882a593Smuzhiyun 	if (!parent_domain)
177*4882a593Smuzhiyun 		return -EPROBE_DEFER;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
180*4882a593Smuzhiyun 	if (!priv)
181*4882a593Smuzhiyun 		return -ENOMEM;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	priv->reg_base = devm_platform_ioremap_resource(pdev, 0);
184*4882a593Smuzhiyun 	if (IS_ERR(priv->reg_base))
185*4882a593Smuzhiyun 		return PTR_ERR(priv->reg_base);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	spin_lock_init(&priv->lock);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	priv->domain = irq_domain_create_hierarchy(
190*4882a593Smuzhiyun 					parent_domain, 0,
191*4882a593Smuzhiyun 					UNIPHIER_AIDET_NR_IRQS,
192*4882a593Smuzhiyun 					of_node_to_fwnode(dev->of_node),
193*4882a593Smuzhiyun 					&uniphier_aidet_domain_ops, priv);
194*4882a593Smuzhiyun 	if (!priv->domain)
195*4882a593Smuzhiyun 		return -ENOMEM;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	platform_set_drvdata(pdev, priv);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	return 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
uniphier_aidet_suspend(struct device * dev)202*4882a593Smuzhiyun static int __maybe_unused uniphier_aidet_suspend(struct device *dev)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	struct uniphier_aidet_priv *priv = dev_get_drvdata(dev);
205*4882a593Smuzhiyun 	int i;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(priv->saved_vals); i++)
208*4882a593Smuzhiyun 		priv->saved_vals[i] = readl_relaxed(
209*4882a593Smuzhiyun 			priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun 
uniphier_aidet_resume(struct device * dev)214*4882a593Smuzhiyun static int __maybe_unused uniphier_aidet_resume(struct device *dev)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun 	struct uniphier_aidet_priv *priv = dev_get_drvdata(dev);
217*4882a593Smuzhiyun 	int i;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(priv->saved_vals); i++)
220*4882a593Smuzhiyun 		writel_relaxed(priv->saved_vals[i],
221*4882a593Smuzhiyun 			       priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	return 0;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun static const struct dev_pm_ops uniphier_aidet_pm_ops = {
227*4882a593Smuzhiyun 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(uniphier_aidet_suspend,
228*4882a593Smuzhiyun 				      uniphier_aidet_resume)
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun static const struct of_device_id uniphier_aidet_match[] = {
232*4882a593Smuzhiyun 	{ .compatible = "socionext,uniphier-ld4-aidet" },
233*4882a593Smuzhiyun 	{ .compatible = "socionext,uniphier-pro4-aidet" },
234*4882a593Smuzhiyun 	{ .compatible = "socionext,uniphier-sld8-aidet" },
235*4882a593Smuzhiyun 	{ .compatible = "socionext,uniphier-pro5-aidet" },
236*4882a593Smuzhiyun 	{ .compatible = "socionext,uniphier-pxs2-aidet" },
237*4882a593Smuzhiyun 	{ .compatible = "socionext,uniphier-ld11-aidet" },
238*4882a593Smuzhiyun 	{ .compatible = "socionext,uniphier-ld20-aidet" },
239*4882a593Smuzhiyun 	{ .compatible = "socionext,uniphier-pxs3-aidet" },
240*4882a593Smuzhiyun 	{ /* sentinel */ }
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun static struct platform_driver uniphier_aidet_driver = {
244*4882a593Smuzhiyun 	.probe = uniphier_aidet_probe,
245*4882a593Smuzhiyun 	.driver = {
246*4882a593Smuzhiyun 		.name = "uniphier-aidet",
247*4882a593Smuzhiyun 		.of_match_table = uniphier_aidet_match,
248*4882a593Smuzhiyun 		.pm = &uniphier_aidet_pm_ops,
249*4882a593Smuzhiyun 	},
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun builtin_platform_driver(uniphier_aidet_driver);
252