1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * H8S interrupt controller driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/irq.h>
9*4882a593Smuzhiyun #include <linux/irqchip.h>
10*4882a593Smuzhiyun #include <linux/of_address.h>
11*4882a593Smuzhiyun #include <linux/of_irq.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static void *intc_baseaddr;
15*4882a593Smuzhiyun #define IPRA (intc_baseaddr)
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static const unsigned char ipr_table[] = {
18*4882a593Smuzhiyun 0x03, 0x02, 0x01, 0x00, 0x13, 0x12, 0x11, 0x10, /* 16 - 23 */
19*4882a593Smuzhiyun 0x23, 0x22, 0x21, 0x20, 0x33, 0x32, 0x31, 0x30, /* 24 - 31 */
20*4882a593Smuzhiyun 0x43, 0x42, 0x41, 0x40, 0x53, 0x53, 0x52, 0x52, /* 32 - 39 */
21*4882a593Smuzhiyun 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, /* 40 - 47 */
22*4882a593Smuzhiyun 0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */
23*4882a593Smuzhiyun 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, /* 56 - 63 */
24*4882a593Smuzhiyun 0x61, 0x61, 0x61, 0x61, 0x60, 0x60, 0x60, 0x60, /* 64 - 71 */
25*4882a593Smuzhiyun 0x73, 0x73, 0x73, 0x73, 0x72, 0x72, 0x72, 0x72, /* 72 - 79 */
26*4882a593Smuzhiyun 0x71, 0x71, 0x71, 0x71, 0x70, 0x83, 0x82, 0x81, /* 80 - 87 */
27*4882a593Smuzhiyun 0x80, 0x80, 0x80, 0x80, 0x93, 0x93, 0x93, 0x93, /* 88 - 95 */
28*4882a593Smuzhiyun 0x92, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x91, /* 96 - 103 */
29*4882a593Smuzhiyun 0x90, 0x90, 0x90, 0x90, 0xa3, 0xa3, 0xa3, 0xa3, /* 104 - 111 */
30*4882a593Smuzhiyun 0xa2, 0xa2, 0xa2, 0xa2, 0xa1, 0xa1, 0xa1, 0xa1, /* 112 - 119 */
31*4882a593Smuzhiyun 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, /* 120 - 127 */
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
h8s_disable_irq(struct irq_data * data)34*4882a593Smuzhiyun static void h8s_disable_irq(struct irq_data *data)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun int pos;
37*4882a593Smuzhiyun void __iomem *addr;
38*4882a593Smuzhiyun unsigned short pri;
39*4882a593Smuzhiyun int irq = data->irq;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
42*4882a593Smuzhiyun pos = (ipr_table[irq - 16] & 0x0f) * 4;
43*4882a593Smuzhiyun pri = ~(0x000f << pos);
44*4882a593Smuzhiyun pri &= readw(addr);
45*4882a593Smuzhiyun writew(pri, addr);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
h8s_enable_irq(struct irq_data * data)48*4882a593Smuzhiyun static void h8s_enable_irq(struct irq_data *data)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun int pos;
51*4882a593Smuzhiyun void __iomem *addr;
52*4882a593Smuzhiyun unsigned short pri;
53*4882a593Smuzhiyun int irq = data->irq;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
56*4882a593Smuzhiyun pos = (ipr_table[irq - 16] & 0x0f) * 4;
57*4882a593Smuzhiyun pri = ~(0x000f << pos);
58*4882a593Smuzhiyun pri &= readw(addr);
59*4882a593Smuzhiyun pri |= 1 << pos;
60*4882a593Smuzhiyun writew(pri, addr);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct irq_chip h8s_irq_chip = {
64*4882a593Smuzhiyun .name = "H8S-INTC",
65*4882a593Smuzhiyun .irq_enable = h8s_enable_irq,
66*4882a593Smuzhiyun .irq_disable = h8s_disable_irq,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw_irq_num)69*4882a593Smuzhiyun static __init int irq_map(struct irq_domain *h, unsigned int virq,
70*4882a593Smuzhiyun irq_hw_number_t hw_irq_num)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun irq_set_chip_and_handler(virq, &h8s_irq_chip, handle_simple_irq);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static const struct irq_domain_ops irq_ops = {
78*4882a593Smuzhiyun .map = irq_map,
79*4882a593Smuzhiyun .xlate = irq_domain_xlate_onecell,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
h8s_intc_of_init(struct device_node * intc,struct device_node * parent)82*4882a593Smuzhiyun static int __init h8s_intc_of_init(struct device_node *intc,
83*4882a593Smuzhiyun struct device_node *parent)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct irq_domain *domain;
86*4882a593Smuzhiyun int n;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun intc_baseaddr = of_iomap(intc, 0);
89*4882a593Smuzhiyun BUG_ON(!intc_baseaddr);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* All interrupt priority is 0 (disable) */
92*4882a593Smuzhiyun /* IPRA to IPRK */
93*4882a593Smuzhiyun for (n = 0; n <= 'k' - 'a'; n++)
94*4882a593Smuzhiyun writew(0x0000, IPRA + (n * 2));
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
97*4882a593Smuzhiyun BUG_ON(!domain);
98*4882a593Smuzhiyun irq_set_default_host(domain);
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun IRQCHIP_DECLARE(h8s_intc, "renesas,h8s-intc", h8s_intc_of_init);
103