1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * H8/300H interrupt controller driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/irq.h>
10*4882a593Smuzhiyun #include <linux/irqchip.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of_irq.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static const char ipr_bit[] = {
16*4882a593Smuzhiyun 7, 6, 5, 5,
17*4882a593Smuzhiyun 4, 4, 4, 4, 3, 3, 3, 3,
18*4882a593Smuzhiyun 2, 2, 2, 2, 1, 1, 1, 1,
19*4882a593Smuzhiyun 0, 0, 0, 0, 15, 15, 15, 15,
20*4882a593Smuzhiyun 14, 14, 14, 14, 13, 13, 13, 13,
21*4882a593Smuzhiyun -1, -1, -1, -1, 11, 11, 11, 11,
22*4882a593Smuzhiyun 10, 10, 10, 10, 9, 9, 9, 9,
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static void __iomem *intc_baseaddr;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define IPR (intc_baseaddr + 6)
28*4882a593Smuzhiyun
h8300h_disable_irq(struct irq_data * data)29*4882a593Smuzhiyun static void h8300h_disable_irq(struct irq_data *data)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun int bit;
32*4882a593Smuzhiyun int irq = data->irq - 12;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun bit = ipr_bit[irq];
35*4882a593Smuzhiyun if (bit >= 0) {
36*4882a593Smuzhiyun if (bit < 8)
37*4882a593Smuzhiyun ctrl_bclr(bit & 7, IPR);
38*4882a593Smuzhiyun else
39*4882a593Smuzhiyun ctrl_bclr(bit & 7, (IPR+1));
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
h8300h_enable_irq(struct irq_data * data)43*4882a593Smuzhiyun static void h8300h_enable_irq(struct irq_data *data)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun int bit;
46*4882a593Smuzhiyun int irq = data->irq - 12;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun bit = ipr_bit[irq];
49*4882a593Smuzhiyun if (bit >= 0) {
50*4882a593Smuzhiyun if (bit < 8)
51*4882a593Smuzhiyun ctrl_bset(bit & 7, IPR);
52*4882a593Smuzhiyun else
53*4882a593Smuzhiyun ctrl_bset(bit & 7, (IPR+1));
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct irq_chip h8300h_irq_chip = {
58*4882a593Smuzhiyun .name = "H8/300H-INTC",
59*4882a593Smuzhiyun .irq_enable = h8300h_enable_irq,
60*4882a593Smuzhiyun .irq_disable = h8300h_disable_irq,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw_irq_num)63*4882a593Smuzhiyun static int irq_map(struct irq_domain *h, unsigned int virq,
64*4882a593Smuzhiyun irq_hw_number_t hw_irq_num)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun irq_set_chip_and_handler(virq, &h8300h_irq_chip, handle_simple_irq);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct irq_domain_ops irq_ops = {
72*4882a593Smuzhiyun .map = irq_map,
73*4882a593Smuzhiyun .xlate = irq_domain_xlate_onecell,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
h8300h_intc_of_init(struct device_node * intc,struct device_node * parent)76*4882a593Smuzhiyun static int __init h8300h_intc_of_init(struct device_node *intc,
77*4882a593Smuzhiyun struct device_node *parent)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct irq_domain *domain;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun intc_baseaddr = of_iomap(intc, 0);
82*4882a593Smuzhiyun BUG_ON(!intc_baseaddr);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* All interrupt priority low */
85*4882a593Smuzhiyun writeb(0x00, IPR + 0);
86*4882a593Smuzhiyun writeb(0x00, IPR + 1);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
89*4882a593Smuzhiyun BUG_ON(!domain);
90*4882a593Smuzhiyun irq_set_default_host(domain);
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun IRQCHIP_DECLARE(h8300h_intc, "renesas,h8300h-intc", h8300h_intc_of_init);
95