1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * RDA8810PL SoC irqchip driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright RDA Microelectronics Company Limited
6*4882a593Smuzhiyun * Copyright (c) 2017 Andreas Färber
7*4882a593Smuzhiyun * Copyright (c) 2018 Manivannan Sadhasivam
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/irqchip.h>
14*4882a593Smuzhiyun #include <linux/irqdomain.h>
15*4882a593Smuzhiyun #include <linux/of_address.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/exception.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define RDA_INTC_FINALSTATUS 0x00
20*4882a593Smuzhiyun #define RDA_INTC_MASK_SET 0x08
21*4882a593Smuzhiyun #define RDA_INTC_MASK_CLR 0x0c
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define RDA_IRQ_MASK_ALL 0xFFFFFFFF
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define RDA_NR_IRQS 32
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static void __iomem *rda_intc_base;
28*4882a593Smuzhiyun static struct irq_domain *rda_irq_domain;
29*4882a593Smuzhiyun
rda_intc_mask_irq(struct irq_data * d)30*4882a593Smuzhiyun static void rda_intc_mask_irq(struct irq_data *d)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun writel_relaxed(BIT(d->hwirq), rda_intc_base + RDA_INTC_MASK_CLR);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
rda_intc_unmask_irq(struct irq_data * d)35*4882a593Smuzhiyun static void rda_intc_unmask_irq(struct irq_data *d)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun writel_relaxed(BIT(d->hwirq), rda_intc_base + RDA_INTC_MASK_SET);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
rda_intc_set_type(struct irq_data * data,unsigned int flow_type)40*4882a593Smuzhiyun static int rda_intc_set_type(struct irq_data *data, unsigned int flow_type)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun /* Hardware supports only level triggered interrupts */
43*4882a593Smuzhiyun if ((flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) == flow_type)
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return -EINVAL;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
rda_handle_irq(struct pt_regs * regs)49*4882a593Smuzhiyun static void __exception_irq_entry rda_handle_irq(struct pt_regs *regs)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun u32 stat = readl_relaxed(rda_intc_base + RDA_INTC_FINALSTATUS);
52*4882a593Smuzhiyun u32 hwirq;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun while (stat) {
55*4882a593Smuzhiyun hwirq = __fls(stat);
56*4882a593Smuzhiyun handle_domain_irq(rda_irq_domain, hwirq, regs);
57*4882a593Smuzhiyun stat &= ~BIT(hwirq);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static struct irq_chip rda_irq_chip = {
62*4882a593Smuzhiyun .name = "rda-intc",
63*4882a593Smuzhiyun .irq_mask = rda_intc_mask_irq,
64*4882a593Smuzhiyun .irq_unmask = rda_intc_unmask_irq,
65*4882a593Smuzhiyun .irq_set_type = rda_intc_set_type,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
rda_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw)68*4882a593Smuzhiyun static int rda_irq_map(struct irq_domain *d,
69*4882a593Smuzhiyun unsigned int virq, irq_hw_number_t hw)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun irq_set_status_flags(virq, IRQ_LEVEL);
72*4882a593Smuzhiyun irq_set_chip_and_handler(virq, &rda_irq_chip, handle_level_irq);
73*4882a593Smuzhiyun irq_set_chip_data(virq, d->host_data);
74*4882a593Smuzhiyun irq_set_probe(virq);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const struct irq_domain_ops rda_irq_domain_ops = {
80*4882a593Smuzhiyun .map = rda_irq_map,
81*4882a593Smuzhiyun .xlate = irq_domain_xlate_onecell,
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
rda8810_intc_init(struct device_node * node,struct device_node * parent)84*4882a593Smuzhiyun static int __init rda8810_intc_init(struct device_node *node,
85*4882a593Smuzhiyun struct device_node *parent)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun rda_intc_base = of_io_request_and_map(node, 0, "rda-intc");
88*4882a593Smuzhiyun if (IS_ERR(rda_intc_base))
89*4882a593Smuzhiyun return PTR_ERR(rda_intc_base);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Mask all interrupt sources */
92*4882a593Smuzhiyun writel_relaxed(RDA_IRQ_MASK_ALL, rda_intc_base + RDA_INTC_MASK_CLR);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun rda_irq_domain = irq_domain_create_linear(&node->fwnode, RDA_NR_IRQS,
95*4882a593Smuzhiyun &rda_irq_domain_ops,
96*4882a593Smuzhiyun rda_intc_base);
97*4882a593Smuzhiyun if (!rda_irq_domain) {
98*4882a593Smuzhiyun iounmap(rda_intc_base);
99*4882a593Smuzhiyun return -ENOMEM;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun set_handle_irq(rda_handle_irq);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun IRQCHIP_DECLARE(rda_intc, "rda,8810pl-intc", rda8810_intc_init);
108