xref: /OK3568_Linux_fs/kernel/drivers/irqchip/irq-mtk-sysirq.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2014 MediaTek Inc.
4*4882a593Smuzhiyun  * Author: Joe.C <yingjoe.chen@mediatek.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/irq.h>
8*4882a593Smuzhiyun #include <linux/irqchip.h>
9*4882a593Smuzhiyun #include <linux/irqdomain.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_irq.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/spinlock.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun struct mtk_sysirq_chip_data {
18*4882a593Smuzhiyun 	raw_spinlock_t lock;
19*4882a593Smuzhiyun 	u32 nr_intpol_bases;
20*4882a593Smuzhiyun 	void __iomem **intpol_bases;
21*4882a593Smuzhiyun 	u32 *intpol_words;
22*4882a593Smuzhiyun 	u8 *intpol_idx;
23*4882a593Smuzhiyun 	u16 *which_word;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
mtk_sysirq_set_type(struct irq_data * data,unsigned int type)26*4882a593Smuzhiyun static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun 	irq_hw_number_t hwirq = data->hwirq;
29*4882a593Smuzhiyun 	struct mtk_sysirq_chip_data *chip_data = data->chip_data;
30*4882a593Smuzhiyun 	u8 intpol_idx = chip_data->intpol_idx[hwirq];
31*4882a593Smuzhiyun 	void __iomem *base;
32*4882a593Smuzhiyun 	u32 offset, reg_index, value;
33*4882a593Smuzhiyun 	unsigned long flags;
34*4882a593Smuzhiyun 	int ret;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	base = chip_data->intpol_bases[intpol_idx];
37*4882a593Smuzhiyun 	reg_index = chip_data->which_word[hwirq];
38*4882a593Smuzhiyun 	offset = hwirq & 0x1f;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	raw_spin_lock_irqsave(&chip_data->lock, flags);
41*4882a593Smuzhiyun 	value = readl_relaxed(base + reg_index * 4);
42*4882a593Smuzhiyun 	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
43*4882a593Smuzhiyun 		if (type == IRQ_TYPE_LEVEL_LOW)
44*4882a593Smuzhiyun 			type = IRQ_TYPE_LEVEL_HIGH;
45*4882a593Smuzhiyun 		else
46*4882a593Smuzhiyun 			type = IRQ_TYPE_EDGE_RISING;
47*4882a593Smuzhiyun 		value |= (1 << offset);
48*4882a593Smuzhiyun 	} else {
49*4882a593Smuzhiyun 		value &= ~(1 << offset);
50*4882a593Smuzhiyun 	}
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	writel_relaxed(value, base + reg_index * 4);
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	data = data->parent_data;
55*4882a593Smuzhiyun 	ret = data->chip->irq_set_type(data, type);
56*4882a593Smuzhiyun 	raw_spin_unlock_irqrestore(&chip_data->lock, flags);
57*4882a593Smuzhiyun 	return ret;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun static struct irq_chip mtk_sysirq_chip = {
61*4882a593Smuzhiyun 	.name			= "MT_SYSIRQ",
62*4882a593Smuzhiyun 	.irq_mask		= irq_chip_mask_parent,
63*4882a593Smuzhiyun 	.irq_unmask		= irq_chip_unmask_parent,
64*4882a593Smuzhiyun 	.irq_eoi		= irq_chip_eoi_parent,
65*4882a593Smuzhiyun 	.irq_set_type		= mtk_sysirq_set_type,
66*4882a593Smuzhiyun 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
67*4882a593Smuzhiyun 	.irq_set_affinity	= irq_chip_set_affinity_parent,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
mtk_sysirq_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)70*4882a593Smuzhiyun static int mtk_sysirq_domain_translate(struct irq_domain *d,
71*4882a593Smuzhiyun 				       struct irq_fwspec *fwspec,
72*4882a593Smuzhiyun 				       unsigned long *hwirq,
73*4882a593Smuzhiyun 				       unsigned int *type)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	if (is_of_node(fwspec->fwnode)) {
76*4882a593Smuzhiyun 		if (fwspec->param_count != 3)
77*4882a593Smuzhiyun 			return -EINVAL;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 		/* No PPI should point to this domain */
80*4882a593Smuzhiyun 		if (fwspec->param[0] != 0)
81*4882a593Smuzhiyun 			return -EINVAL;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 		*hwirq = fwspec->param[1];
84*4882a593Smuzhiyun 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
85*4882a593Smuzhiyun 		return 0;
86*4882a593Smuzhiyun 	}
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	return -EINVAL;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
mtk_sysirq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)91*4882a593Smuzhiyun static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
92*4882a593Smuzhiyun 				   unsigned int nr_irqs, void *arg)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	int i;
95*4882a593Smuzhiyun 	irq_hw_number_t hwirq;
96*4882a593Smuzhiyun 	struct irq_fwspec *fwspec = arg;
97*4882a593Smuzhiyun 	struct irq_fwspec gic_fwspec = *fwspec;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	if (fwspec->param_count != 3)
100*4882a593Smuzhiyun 		return -EINVAL;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	/* sysirq doesn't support PPI */
103*4882a593Smuzhiyun 	if (fwspec->param[0])
104*4882a593Smuzhiyun 		return -EINVAL;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	hwirq = fwspec->param[1];
107*4882a593Smuzhiyun 	for (i = 0; i < nr_irqs; i++)
108*4882a593Smuzhiyun 		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
109*4882a593Smuzhiyun 					      &mtk_sysirq_chip,
110*4882a593Smuzhiyun 					      domain->host_data);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	gic_fwspec.fwnode = domain->parent->fwnode;
113*4882a593Smuzhiyun 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun static const struct irq_domain_ops sysirq_domain_ops = {
117*4882a593Smuzhiyun 	.translate	= mtk_sysirq_domain_translate,
118*4882a593Smuzhiyun 	.alloc		= mtk_sysirq_domain_alloc,
119*4882a593Smuzhiyun 	.free		= irq_domain_free_irqs_common,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
mtk_sysirq_of_init(struct device_node * node,struct device_node * parent)122*4882a593Smuzhiyun static int __init mtk_sysirq_of_init(struct device_node *node,
123*4882a593Smuzhiyun 				     struct device_node *parent)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	struct irq_domain *domain, *domain_parent;
126*4882a593Smuzhiyun 	struct mtk_sysirq_chip_data *chip_data;
127*4882a593Smuzhiyun 	int ret, size, intpol_num = 0, nr_intpol_bases = 0, i = 0;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	domain_parent = irq_find_host(parent);
130*4882a593Smuzhiyun 	if (!domain_parent) {
131*4882a593Smuzhiyun 		pr_err("mtk_sysirq: interrupt-parent not found\n");
132*4882a593Smuzhiyun 		return -EINVAL;
133*4882a593Smuzhiyun 	}
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
136*4882a593Smuzhiyun 	if (!chip_data)
137*4882a593Smuzhiyun 		return -ENOMEM;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	while (of_get_address(node, i++, NULL, NULL))
140*4882a593Smuzhiyun 		nr_intpol_bases++;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	if (nr_intpol_bases == 0) {
143*4882a593Smuzhiyun 		pr_err("mtk_sysirq: base address not specified\n");
144*4882a593Smuzhiyun 		ret = -EINVAL;
145*4882a593Smuzhiyun 		goto out_free_chip;
146*4882a593Smuzhiyun 	}
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	chip_data->intpol_words = kcalloc(nr_intpol_bases,
149*4882a593Smuzhiyun 					  sizeof(*chip_data->intpol_words),
150*4882a593Smuzhiyun 					  GFP_KERNEL);
151*4882a593Smuzhiyun 	if (!chip_data->intpol_words) {
152*4882a593Smuzhiyun 		ret = -ENOMEM;
153*4882a593Smuzhiyun 		goto out_free_chip;
154*4882a593Smuzhiyun 	}
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	chip_data->intpol_bases = kcalloc(nr_intpol_bases,
157*4882a593Smuzhiyun 					  sizeof(*chip_data->intpol_bases),
158*4882a593Smuzhiyun 					  GFP_KERNEL);
159*4882a593Smuzhiyun 	if (!chip_data->intpol_bases) {
160*4882a593Smuzhiyun 		ret = -ENOMEM;
161*4882a593Smuzhiyun 		goto out_free_intpol_words;
162*4882a593Smuzhiyun 	}
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	for (i = 0; i < nr_intpol_bases; i++) {
165*4882a593Smuzhiyun 		struct resource res;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 		ret = of_address_to_resource(node, i, &res);
168*4882a593Smuzhiyun 		size = resource_size(&res);
169*4882a593Smuzhiyun 		intpol_num += size * 8;
170*4882a593Smuzhiyun 		chip_data->intpol_words[i] = size / 4;
171*4882a593Smuzhiyun 		chip_data->intpol_bases[i] = of_iomap(node, i);
172*4882a593Smuzhiyun 		if (ret || !chip_data->intpol_bases[i]) {
173*4882a593Smuzhiyun 			pr_err("%pOF: couldn't map region %d\n", node, i);
174*4882a593Smuzhiyun 			ret = -ENODEV;
175*4882a593Smuzhiyun 			goto out_free_intpol;
176*4882a593Smuzhiyun 		}
177*4882a593Smuzhiyun 	}
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	chip_data->intpol_idx = kcalloc(intpol_num,
180*4882a593Smuzhiyun 					sizeof(*chip_data->intpol_idx),
181*4882a593Smuzhiyun 					GFP_KERNEL);
182*4882a593Smuzhiyun 	if (!chip_data->intpol_idx) {
183*4882a593Smuzhiyun 		ret = -ENOMEM;
184*4882a593Smuzhiyun 		goto out_free_intpol;
185*4882a593Smuzhiyun 	}
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	chip_data->which_word = kcalloc(intpol_num,
188*4882a593Smuzhiyun 					sizeof(*chip_data->which_word),
189*4882a593Smuzhiyun 					GFP_KERNEL);
190*4882a593Smuzhiyun 	if (!chip_data->which_word) {
191*4882a593Smuzhiyun 		ret = -ENOMEM;
192*4882a593Smuzhiyun 		goto out_free_intpol_idx;
193*4882a593Smuzhiyun 	}
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	/*
196*4882a593Smuzhiyun 	 * assign an index of the intpol_bases for each irq
197*4882a593Smuzhiyun 	 * to set it fast later
198*4882a593Smuzhiyun 	 */
199*4882a593Smuzhiyun 	for (i = 0; i < intpol_num ; i++) {
200*4882a593Smuzhiyun 		u32 word = i / 32, j;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 		for (j = 0; word >= chip_data->intpol_words[j] ; j++)
203*4882a593Smuzhiyun 			word -= chip_data->intpol_words[j];
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 		chip_data->intpol_idx[i] = j;
206*4882a593Smuzhiyun 		chip_data->which_word[i] = word;
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
210*4882a593Smuzhiyun 					  &sysirq_domain_ops, chip_data);
211*4882a593Smuzhiyun 	if (!domain) {
212*4882a593Smuzhiyun 		ret = -ENOMEM;
213*4882a593Smuzhiyun 		goto out_free_which_word;
214*4882a593Smuzhiyun 	}
215*4882a593Smuzhiyun 	raw_spin_lock_init(&chip_data->lock);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	return 0;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun out_free_which_word:
220*4882a593Smuzhiyun 	kfree(chip_data->which_word);
221*4882a593Smuzhiyun out_free_intpol_idx:
222*4882a593Smuzhiyun 	kfree(chip_data->intpol_idx);
223*4882a593Smuzhiyun out_free_intpol:
224*4882a593Smuzhiyun 	for (i = 0; i < nr_intpol_bases; i++)
225*4882a593Smuzhiyun 		if (chip_data->intpol_bases[i])
226*4882a593Smuzhiyun 			iounmap(chip_data->intpol_bases[i]);
227*4882a593Smuzhiyun 	kfree(chip_data->intpol_bases);
228*4882a593Smuzhiyun out_free_intpol_words:
229*4882a593Smuzhiyun 	kfree(chip_data->intpol_words);
230*4882a593Smuzhiyun out_free_chip:
231*4882a593Smuzhiyun 	kfree(chip_data);
232*4882a593Smuzhiyun 	return ret;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
235