xref: /OK3568_Linux_fs/kernel/drivers/irqchip/irq-ls-extirq.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun #define pr_fmt(fmt) "irq-ls-extirq: " fmt
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include <linux/irq.h>
6*4882a593Smuzhiyun #include <linux/irqchip.h>
7*4882a593Smuzhiyun #include <linux/irqdomain.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
10*4882a593Smuzhiyun #include <linux/regmap.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define MAXIRQ 12
16*4882a593Smuzhiyun #define LS1021A_SCFGREVCR 0x200
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun struct ls_extirq_data {
19*4882a593Smuzhiyun 	struct regmap		*syscon;
20*4882a593Smuzhiyun 	u32			intpcr;
21*4882a593Smuzhiyun 	bool			bit_reverse;
22*4882a593Smuzhiyun 	u32			nirq;
23*4882a593Smuzhiyun 	struct irq_fwspec	map[MAXIRQ];
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun static int
ls_extirq_set_type(struct irq_data * data,unsigned int type)27*4882a593Smuzhiyun ls_extirq_set_type(struct irq_data *data, unsigned int type)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun 	struct ls_extirq_data *priv = data->chip_data;
30*4882a593Smuzhiyun 	irq_hw_number_t hwirq = data->hwirq;
31*4882a593Smuzhiyun 	u32 value, mask;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	if (priv->bit_reverse)
34*4882a593Smuzhiyun 		mask = 1U << (31 - hwirq);
35*4882a593Smuzhiyun 	else
36*4882a593Smuzhiyun 		mask = 1U << hwirq;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	switch (type) {
39*4882a593Smuzhiyun 	case IRQ_TYPE_LEVEL_LOW:
40*4882a593Smuzhiyun 		type = IRQ_TYPE_LEVEL_HIGH;
41*4882a593Smuzhiyun 		value = mask;
42*4882a593Smuzhiyun 		break;
43*4882a593Smuzhiyun 	case IRQ_TYPE_EDGE_FALLING:
44*4882a593Smuzhiyun 		type = IRQ_TYPE_EDGE_RISING;
45*4882a593Smuzhiyun 		value = mask;
46*4882a593Smuzhiyun 		break;
47*4882a593Smuzhiyun 	case IRQ_TYPE_LEVEL_HIGH:
48*4882a593Smuzhiyun 	case IRQ_TYPE_EDGE_RISING:
49*4882a593Smuzhiyun 		value = 0;
50*4882a593Smuzhiyun 		break;
51*4882a593Smuzhiyun 	default:
52*4882a593Smuzhiyun 		return -EINVAL;
53*4882a593Smuzhiyun 	}
54*4882a593Smuzhiyun 	regmap_update_bits(priv->syscon, priv->intpcr, mask, value);
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	return irq_chip_set_type_parent(data, type);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static struct irq_chip ls_extirq_chip = {
60*4882a593Smuzhiyun 	.name			= "ls-extirq",
61*4882a593Smuzhiyun 	.irq_mask		= irq_chip_mask_parent,
62*4882a593Smuzhiyun 	.irq_unmask		= irq_chip_unmask_parent,
63*4882a593Smuzhiyun 	.irq_eoi		= irq_chip_eoi_parent,
64*4882a593Smuzhiyun 	.irq_set_type		= ls_extirq_set_type,
65*4882a593Smuzhiyun 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
66*4882a593Smuzhiyun 	.irq_set_affinity	= irq_chip_set_affinity_parent,
67*4882a593Smuzhiyun 	.flags                  = IRQCHIP_SET_TYPE_MASKED,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun static int
ls_extirq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)71*4882a593Smuzhiyun ls_extirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
72*4882a593Smuzhiyun 		       unsigned int nr_irqs, void *arg)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	struct ls_extirq_data *priv = domain->host_data;
75*4882a593Smuzhiyun 	struct irq_fwspec *fwspec = arg;
76*4882a593Smuzhiyun 	irq_hw_number_t hwirq;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	if (fwspec->param_count != 2)
79*4882a593Smuzhiyun 		return -EINVAL;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	hwirq = fwspec->param[0];
82*4882a593Smuzhiyun 	if (hwirq >= priv->nirq)
83*4882a593Smuzhiyun 		return -EINVAL;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip,
86*4882a593Smuzhiyun 				      priv);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	return irq_domain_alloc_irqs_parent(domain, virq, 1, &priv->map[hwirq]);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun static const struct irq_domain_ops extirq_domain_ops = {
92*4882a593Smuzhiyun 	.xlate		= irq_domain_xlate_twocell,
93*4882a593Smuzhiyun 	.alloc		= ls_extirq_domain_alloc,
94*4882a593Smuzhiyun 	.free		= irq_domain_free_irqs_common,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static int
ls_extirq_parse_map(struct ls_extirq_data * priv,struct device_node * node)98*4882a593Smuzhiyun ls_extirq_parse_map(struct ls_extirq_data *priv, struct device_node *node)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	const __be32 *map;
101*4882a593Smuzhiyun 	u32 mapsize;
102*4882a593Smuzhiyun 	int ret;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	map = of_get_property(node, "interrupt-map", &mapsize);
105*4882a593Smuzhiyun 	if (!map)
106*4882a593Smuzhiyun 		return -ENOENT;
107*4882a593Smuzhiyun 	if (mapsize % sizeof(*map))
108*4882a593Smuzhiyun 		return -EINVAL;
109*4882a593Smuzhiyun 	mapsize /= sizeof(*map);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	while (mapsize) {
112*4882a593Smuzhiyun 		struct device_node *ipar;
113*4882a593Smuzhiyun 		u32 hwirq, intsize, j;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 		if (mapsize < 3)
116*4882a593Smuzhiyun 			return -EINVAL;
117*4882a593Smuzhiyun 		hwirq = be32_to_cpup(map);
118*4882a593Smuzhiyun 		if (hwirq >= MAXIRQ)
119*4882a593Smuzhiyun 			return -EINVAL;
120*4882a593Smuzhiyun 		priv->nirq = max(priv->nirq, hwirq + 1);
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 		ipar = of_find_node_by_phandle(be32_to_cpup(map + 2));
123*4882a593Smuzhiyun 		map += 3;
124*4882a593Smuzhiyun 		mapsize -= 3;
125*4882a593Smuzhiyun 		if (!ipar)
126*4882a593Smuzhiyun 			return -EINVAL;
127*4882a593Smuzhiyun 		priv->map[hwirq].fwnode = &ipar->fwnode;
128*4882a593Smuzhiyun 		ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);
129*4882a593Smuzhiyun 		if (ret)
130*4882a593Smuzhiyun 			return ret;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 		if (intsize > mapsize)
133*4882a593Smuzhiyun 			return -EINVAL;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 		priv->map[hwirq].param_count = intsize;
136*4882a593Smuzhiyun 		for (j = 0; j < intsize; ++j)
137*4882a593Smuzhiyun 			priv->map[hwirq].param[j] = be32_to_cpup(map++);
138*4882a593Smuzhiyun 		mapsize -= intsize;
139*4882a593Smuzhiyun 	}
140*4882a593Smuzhiyun 	return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static int __init
ls_extirq_of_init(struct device_node * node,struct device_node * parent)144*4882a593Smuzhiyun ls_extirq_of_init(struct device_node *node, struct device_node *parent)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	struct irq_domain *domain, *parent_domain;
148*4882a593Smuzhiyun 	struct ls_extirq_data *priv;
149*4882a593Smuzhiyun 	int ret;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	parent_domain = irq_find_host(parent);
152*4882a593Smuzhiyun 	if (!parent_domain) {
153*4882a593Smuzhiyun 		pr_err("Cannot find parent domain\n");
154*4882a593Smuzhiyun 		return -ENODEV;
155*4882a593Smuzhiyun 	}
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
158*4882a593Smuzhiyun 	if (!priv)
159*4882a593Smuzhiyun 		return -ENOMEM;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	priv->syscon = syscon_node_to_regmap(node->parent);
162*4882a593Smuzhiyun 	if (IS_ERR(priv->syscon)) {
163*4882a593Smuzhiyun 		ret = PTR_ERR(priv->syscon);
164*4882a593Smuzhiyun 		pr_err("Failed to lookup parent regmap\n");
165*4882a593Smuzhiyun 		goto out;
166*4882a593Smuzhiyun 	}
167*4882a593Smuzhiyun 	ret = of_property_read_u32(node, "reg", &priv->intpcr);
168*4882a593Smuzhiyun 	if (ret) {
169*4882a593Smuzhiyun 		pr_err("Missing INTPCR offset value\n");
170*4882a593Smuzhiyun 		goto out;
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	ret = ls_extirq_parse_map(priv, node);
174*4882a593Smuzhiyun 	if (ret)
175*4882a593Smuzhiyun 		goto out;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	if (of_device_is_compatible(node, "fsl,ls1021a-extirq")) {
178*4882a593Smuzhiyun 		u32 revcr;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 		ret = regmap_read(priv->syscon, LS1021A_SCFGREVCR, &revcr);
181*4882a593Smuzhiyun 		if (ret)
182*4882a593Smuzhiyun 			goto out;
183*4882a593Smuzhiyun 		priv->bit_reverse = (revcr != 0);
184*4882a593Smuzhiyun 	}
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node,
187*4882a593Smuzhiyun 					  &extirq_domain_ops, priv);
188*4882a593Smuzhiyun 	if (!domain)
189*4882a593Smuzhiyun 		ret = -ENOMEM;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun out:
192*4882a593Smuzhiyun 	if (ret)
193*4882a593Smuzhiyun 		kfree(priv);
194*4882a593Smuzhiyun 	return ret;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init);
198