1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * J-Core SoC AIC driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
7*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
8*4882a593Smuzhiyun * for more details.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/irqchip.h>
14*4882a593Smuzhiyun #include <linux/irqdomain.h>
15*4882a593Smuzhiyun #include <linux/cpu.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_address.h>
18*4882a593Smuzhiyun #include <linux/of_irq.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define JCORE_AIC_MAX_HWIRQ 127
21*4882a593Smuzhiyun #define JCORE_AIC1_MIN_HWIRQ 16
22*4882a593Smuzhiyun #define JCORE_AIC2_MIN_HWIRQ 64
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define JCORE_AIC1_INTPRI_REG 8
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static struct irq_chip jcore_aic;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * The J-Core AIC1 and AIC2 are cpu-local interrupt controllers and do
30*4882a593Smuzhiyun * not distinguish or use distinct irq number ranges for per-cpu event
31*4882a593Smuzhiyun * interrupts (timer, IPI). Since information to determine whether a
32*4882a593Smuzhiyun * particular irq number should be treated as per-cpu is not available
33*4882a593Smuzhiyun * at mapping time, we use a wrapper handler function which chooses
34*4882a593Smuzhiyun * the right handler at runtime based on whether IRQF_PERCPU was used
35*4882a593Smuzhiyun * when requesting the irq.
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun
handle_jcore_irq(struct irq_desc * desc)38*4882a593Smuzhiyun static void handle_jcore_irq(struct irq_desc *desc)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun if (irqd_is_per_cpu(irq_desc_get_irq_data(desc)))
41*4882a593Smuzhiyun handle_percpu_irq(desc);
42*4882a593Smuzhiyun else
43*4882a593Smuzhiyun handle_simple_irq(desc);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
jcore_aic_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)46*4882a593Smuzhiyun static int jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq,
47*4882a593Smuzhiyun irq_hw_number_t hwirq)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct irq_chip *aic = d->host_data;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun irq_set_chip_and_handler(irq, aic, handle_jcore_irq);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static const struct irq_domain_ops jcore_aic_irqdomain_ops = {
57*4882a593Smuzhiyun .map = jcore_aic_irqdomain_map,
58*4882a593Smuzhiyun .xlate = irq_domain_xlate_onecell,
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
noop(struct irq_data * data)61*4882a593Smuzhiyun static void noop(struct irq_data *data)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
aic_irq_of_init(struct device_node * node,struct device_node * parent)65*4882a593Smuzhiyun static int __init aic_irq_of_init(struct device_node *node,
66*4882a593Smuzhiyun struct device_node *parent)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun unsigned min_irq = JCORE_AIC2_MIN_HWIRQ;
69*4882a593Smuzhiyun unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1;
70*4882a593Smuzhiyun struct irq_domain *domain;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun pr_info("Initializing J-Core AIC\n");
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* AIC1 needs priority initialization to receive interrupts. */
75*4882a593Smuzhiyun if (of_device_is_compatible(node, "jcore,aic1")) {
76*4882a593Smuzhiyun unsigned cpu;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun for_each_present_cpu(cpu) {
79*4882a593Smuzhiyun void __iomem *base = of_iomap(node, cpu);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (!base) {
82*4882a593Smuzhiyun pr_err("Unable to map AIC for cpu %u\n", cpu);
83*4882a593Smuzhiyun return -ENOMEM;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun __raw_writel(0xffffffff, base + JCORE_AIC1_INTPRI_REG);
86*4882a593Smuzhiyun iounmap(base);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun min_irq = JCORE_AIC1_MIN_HWIRQ;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun * The irq chip framework requires either mask/unmask or enable/disable
93*4882a593Smuzhiyun * function pointers to be provided, but the hardware does not have any
94*4882a593Smuzhiyun * such mechanism; the only interrupt masking is at the cpu level and
95*4882a593Smuzhiyun * it affects all interrupts. We provide dummy mask/unmask. The hardware
96*4882a593Smuzhiyun * handles all interrupt control and clears pending status when the cpu
97*4882a593Smuzhiyun * accepts the interrupt.
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun jcore_aic.irq_mask = noop;
100*4882a593Smuzhiyun jcore_aic.irq_unmask = noop;
101*4882a593Smuzhiyun jcore_aic.name = "AIC";
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun domain = irq_domain_add_linear(node, dom_sz, &jcore_aic_irqdomain_ops,
104*4882a593Smuzhiyun &jcore_aic);
105*4882a593Smuzhiyun if (!domain)
106*4882a593Smuzhiyun return -ENOMEM;
107*4882a593Smuzhiyun irq_create_strict_mappings(domain, min_irq, min_irq, dom_sz - min_irq);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2", aic_irq_of_init);
113*4882a593Smuzhiyun IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1", aic_irq_of_init);
114