1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for MIPS Goldfish Programmable Interrupt Controller.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Miodrag Dinic <miodrag.dinic@mips.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/irqchip.h>
13*4882a593Smuzhiyun #include <linux/irqchip/chained_irq.h>
14*4882a593Smuzhiyun #include <linux/irqdomain.h>
15*4882a593Smuzhiyun #include <linux/of_address.h>
16*4882a593Smuzhiyun #include <linux/of_irq.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define GFPIC_NR_IRQS 32
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* 8..39 Cascaded Goldfish PIC interrupts */
21*4882a593Smuzhiyun #define GFPIC_IRQ_BASE 8
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define GFPIC_REG_IRQ_PENDING 0x04
24*4882a593Smuzhiyun #define GFPIC_REG_IRQ_DISABLE_ALL 0x08
25*4882a593Smuzhiyun #define GFPIC_REG_IRQ_DISABLE 0x0c
26*4882a593Smuzhiyun #define GFPIC_REG_IRQ_ENABLE 0x10
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct goldfish_pic_data {
29*4882a593Smuzhiyun void __iomem *base;
30*4882a593Smuzhiyun struct irq_domain *irq_domain;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
goldfish_pic_cascade(struct irq_desc * desc)33*4882a593Smuzhiyun static void goldfish_pic_cascade(struct irq_desc *desc)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
36*4882a593Smuzhiyun struct irq_chip *host_chip = irq_desc_get_chip(desc);
37*4882a593Smuzhiyun u32 pending, hwirq, virq;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun chained_irq_enter(host_chip, desc);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
42*4882a593Smuzhiyun while (pending) {
43*4882a593Smuzhiyun hwirq = __fls(pending);
44*4882a593Smuzhiyun virq = irq_linear_revmap(gfpic->irq_domain, hwirq);
45*4882a593Smuzhiyun generic_handle_irq(virq);
46*4882a593Smuzhiyun pending &= ~(1 << hwirq);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun chained_irq_exit(host_chip, desc);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static const struct irq_domain_ops goldfish_irq_domain_ops = {
53*4882a593Smuzhiyun .xlate = irq_domain_xlate_onecell,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
goldfish_pic_of_init(struct device_node * of_node,struct device_node * parent)56*4882a593Smuzhiyun static int __init goldfish_pic_of_init(struct device_node *of_node,
57*4882a593Smuzhiyun struct device_node *parent)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct goldfish_pic_data *gfpic;
60*4882a593Smuzhiyun struct irq_chip_generic *gc;
61*4882a593Smuzhiyun struct irq_chip_type *ct;
62*4882a593Smuzhiyun unsigned int parent_irq;
63*4882a593Smuzhiyun int ret = 0;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
66*4882a593Smuzhiyun if (!gfpic) {
67*4882a593Smuzhiyun ret = -ENOMEM;
68*4882a593Smuzhiyun goto out_err;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun parent_irq = irq_of_parse_and_map(of_node, 0);
72*4882a593Smuzhiyun if (!parent_irq) {
73*4882a593Smuzhiyun pr_err("Failed to map parent IRQ!\n");
74*4882a593Smuzhiyun ret = -EINVAL;
75*4882a593Smuzhiyun goto out_free;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun gfpic->base = of_iomap(of_node, 0);
79*4882a593Smuzhiyun if (!gfpic->base) {
80*4882a593Smuzhiyun pr_err("Failed to map base address!\n");
81*4882a593Smuzhiyun ret = -ENOMEM;
82*4882a593Smuzhiyun goto out_unmap_irq;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Mask interrupts. */
86*4882a593Smuzhiyun writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
89*4882a593Smuzhiyun handle_level_irq);
90*4882a593Smuzhiyun if (!gc) {
91*4882a593Smuzhiyun pr_err("Failed to allocate chip structures!\n");
92*4882a593Smuzhiyun ret = -ENOMEM;
93*4882a593Smuzhiyun goto out_iounmap;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun ct = gc->chip_types;
97*4882a593Smuzhiyun ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
98*4882a593Smuzhiyun ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
99*4882a593Smuzhiyun ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
100*4882a593Smuzhiyun ct->chip.irq_mask = irq_gc_mask_disable_reg;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0,
103*4882a593Smuzhiyun IRQ_NOPROBE | IRQ_LEVEL, 0);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
106*4882a593Smuzhiyun GFPIC_IRQ_BASE, 0,
107*4882a593Smuzhiyun &goldfish_irq_domain_ops,
108*4882a593Smuzhiyun NULL);
109*4882a593Smuzhiyun if (!gfpic->irq_domain) {
110*4882a593Smuzhiyun pr_err("Failed to add irqdomain!\n");
111*4882a593Smuzhiyun ret = -ENOMEM;
112*4882a593Smuzhiyun goto out_destroy_generic_chip;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun irq_set_chained_handler_and_data(parent_irq,
116*4882a593Smuzhiyun goldfish_pic_cascade, gfpic);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun pr_info("Successfully registered.\n");
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun out_destroy_generic_chip:
122*4882a593Smuzhiyun irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS),
123*4882a593Smuzhiyun IRQ_NOPROBE | IRQ_LEVEL, 0);
124*4882a593Smuzhiyun out_iounmap:
125*4882a593Smuzhiyun iounmap(gfpic->base);
126*4882a593Smuzhiyun out_unmap_irq:
127*4882a593Smuzhiyun irq_dispose_mapping(parent_irq);
128*4882a593Smuzhiyun out_free:
129*4882a593Smuzhiyun kfree(gfpic);
130*4882a593Smuzhiyun out_err:
131*4882a593Smuzhiyun pr_err("Failed to initialize! (errno = %d)\n", ret);
132*4882a593Smuzhiyun return ret;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);
136