1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Special GIC quirks for the ARM RealView
4*4882a593Smuzhiyun * Copyright (C) 2015 Linus Walleij
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <linux/of.h>
7*4882a593Smuzhiyun #include <linux/regmap.h>
8*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/irqchip.h>
11*4882a593Smuzhiyun #include <linux/irqchip/arm-gic.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define REALVIEW_SYS_LOCK_OFFSET 0x20
14*4882a593Smuzhiyun #define REALVIEW_SYS_PLD_CTRL1 0x74
15*4882a593Smuzhiyun #define REALVIEW_EB_REVB_SYS_PLD_CTRL1 0xD8
16*4882a593Smuzhiyun #define VERSATILE_LOCK_VAL 0xA05F
17*4882a593Smuzhiyun #define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24)
18*4882a593Smuzhiyun #define PLD_INTMODE_LEGACY 0x0
19*4882a593Smuzhiyun #define PLD_INTMODE_NEW_DCC BIT(22)
20*4882a593Smuzhiyun #define PLD_INTMODE_NEW_NO_DCC BIT(23)
21*4882a593Smuzhiyun #define PLD_INTMODE_FIQ_ENABLE BIT(24)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* For some reason RealView EB Rev B moved this register */
24*4882a593Smuzhiyun static const struct of_device_id syscon_pldset_of_match[] = {
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun .compatible = "arm,realview-eb11mp-revb-syscon",
27*4882a593Smuzhiyun .data = (void *)REALVIEW_EB_REVB_SYS_PLD_CTRL1,
28*4882a593Smuzhiyun },
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun .compatible = "arm,realview-eb11mp-revc-syscon",
31*4882a593Smuzhiyun .data = (void *)REALVIEW_SYS_PLD_CTRL1,
32*4882a593Smuzhiyun },
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun .compatible = "arm,realview-eb-syscon",
35*4882a593Smuzhiyun .data = (void *)REALVIEW_SYS_PLD_CTRL1,
36*4882a593Smuzhiyun },
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun .compatible = "arm,realview-pb11mp-syscon",
39*4882a593Smuzhiyun .data = (void *)REALVIEW_SYS_PLD_CTRL1,
40*4882a593Smuzhiyun },
41*4882a593Smuzhiyun {},
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static int __init
realview_gic_of_init(struct device_node * node,struct device_node * parent)45*4882a593Smuzhiyun realview_gic_of_init(struct device_node *node, struct device_node *parent)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct regmap *map;
48*4882a593Smuzhiyun struct device_node *np;
49*4882a593Smuzhiyun const struct of_device_id *gic_id;
50*4882a593Smuzhiyun u32 pld1_ctrl;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun np = of_find_matching_node_and_match(NULL, syscon_pldset_of_match,
53*4882a593Smuzhiyun &gic_id);
54*4882a593Smuzhiyun if (!np)
55*4882a593Smuzhiyun return -ENODEV;
56*4882a593Smuzhiyun pld1_ctrl = (u32)gic_id->data;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* The PB11MPCore GIC needs to be configured in the syscon */
59*4882a593Smuzhiyun map = syscon_node_to_regmap(np);
60*4882a593Smuzhiyun of_node_put(np);
61*4882a593Smuzhiyun if (!IS_ERR(map)) {
62*4882a593Smuzhiyun /* new irq mode with no DCC */
63*4882a593Smuzhiyun regmap_write(map, REALVIEW_SYS_LOCK_OFFSET,
64*4882a593Smuzhiyun VERSATILE_LOCK_VAL);
65*4882a593Smuzhiyun regmap_update_bits(map, pld1_ctrl,
66*4882a593Smuzhiyun PLD_INTMODE_NEW_NO_DCC,
67*4882a593Smuzhiyun PLD_INTMODE_MASK);
68*4882a593Smuzhiyun regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000);
69*4882a593Smuzhiyun pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n");
70*4882a593Smuzhiyun } else {
71*4882a593Smuzhiyun pr_err("RealView GIC setup: could not find syscon\n");
72*4882a593Smuzhiyun return -ENODEV;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun return gic_of_init(node, parent);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
77*4882a593Smuzhiyun IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);
78