1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 NVIDIA CORPORATION, All Rights Reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/of_device.h>
8*4882a593Smuzhiyun #include <linux/of_irq.h>
9*4882a593Smuzhiyun #include <linux/irqchip/arm-gic.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/pm_runtime.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct gic_clk_data {
15*4882a593Smuzhiyun unsigned int num_clocks;
16*4882a593Smuzhiyun const char *const *clocks;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct gic_chip_pm {
20*4882a593Smuzhiyun struct gic_chip_data *chip_data;
21*4882a593Smuzhiyun const struct gic_clk_data *clk_data;
22*4882a593Smuzhiyun struct clk_bulk_data *clks;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
gic_runtime_resume(struct device * dev)25*4882a593Smuzhiyun static int gic_runtime_resume(struct device *dev)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct gic_chip_pm *chip_pm = dev_get_drvdata(dev);
28*4882a593Smuzhiyun struct gic_chip_data *gic = chip_pm->chip_data;
29*4882a593Smuzhiyun const struct gic_clk_data *data = chip_pm->clk_data;
30*4882a593Smuzhiyun int ret;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun ret = clk_bulk_prepare_enable(data->num_clocks, chip_pm->clks);
33*4882a593Smuzhiyun if (ret) {
34*4882a593Smuzhiyun dev_err(dev, "clk_enable failed: %d\n", ret);
35*4882a593Smuzhiyun return ret;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * On the very first resume, the pointer to chip_pm->chip_data
40*4882a593Smuzhiyun * will be NULL and this is intentional, because we do not
41*4882a593Smuzhiyun * want to restore the GIC on the very first resume. So if
42*4882a593Smuzhiyun * the pointer is not valid just return.
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun if (!gic)
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun gic_dist_restore(gic);
48*4882a593Smuzhiyun gic_cpu_restore(gic);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
gic_runtime_suspend(struct device * dev)53*4882a593Smuzhiyun static int gic_runtime_suspend(struct device *dev)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct gic_chip_pm *chip_pm = dev_get_drvdata(dev);
56*4882a593Smuzhiyun struct gic_chip_data *gic = chip_pm->chip_data;
57*4882a593Smuzhiyun const struct gic_clk_data *data = chip_pm->clk_data;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun gic_dist_save(gic);
60*4882a593Smuzhiyun gic_cpu_save(gic);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun clk_bulk_disable_unprepare(data->num_clocks, chip_pm->clks);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
gic_probe(struct platform_device * pdev)67*4882a593Smuzhiyun static int gic_probe(struct platform_device *pdev)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct device *dev = &pdev->dev;
70*4882a593Smuzhiyun const struct gic_clk_data *data;
71*4882a593Smuzhiyun struct gic_chip_pm *chip_pm;
72*4882a593Smuzhiyun int ret, irq, i;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun data = of_device_get_match_data(&pdev->dev);
75*4882a593Smuzhiyun if (!data) {
76*4882a593Smuzhiyun dev_err(&pdev->dev, "no device match found\n");
77*4882a593Smuzhiyun return -ENODEV;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun chip_pm = devm_kzalloc(dev, sizeof(*chip_pm), GFP_KERNEL);
81*4882a593Smuzhiyun if (!chip_pm)
82*4882a593Smuzhiyun return -ENOMEM;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun irq = irq_of_parse_and_map(dev->of_node, 0);
85*4882a593Smuzhiyun if (!irq) {
86*4882a593Smuzhiyun dev_err(dev, "no parent interrupt found!\n");
87*4882a593Smuzhiyun return -EINVAL;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun chip_pm->clks = devm_kcalloc(dev, data->num_clocks,
91*4882a593Smuzhiyun sizeof(*chip_pm->clks), GFP_KERNEL);
92*4882a593Smuzhiyun if (!chip_pm->clks)
93*4882a593Smuzhiyun return -ENOMEM;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun for (i = 0; i < data->num_clocks; i++)
96*4882a593Smuzhiyun chip_pm->clks[i].id = data->clocks[i];
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun ret = devm_clk_bulk_get(dev, data->num_clocks, chip_pm->clks);
99*4882a593Smuzhiyun if (ret)
100*4882a593Smuzhiyun goto irq_dispose;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun chip_pm->clk_data = data;
103*4882a593Smuzhiyun dev_set_drvdata(dev, chip_pm);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun pm_runtime_enable(dev);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun ret = pm_runtime_get_sync(dev);
108*4882a593Smuzhiyun if (ret < 0)
109*4882a593Smuzhiyun goto rpm_disable;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun ret = gic_of_init_child(dev, &chip_pm->chip_data, irq);
112*4882a593Smuzhiyun if (ret)
113*4882a593Smuzhiyun goto rpm_put;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun pm_runtime_put(dev);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun dev_info(dev, "GIC IRQ controller registered\n");
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun rpm_put:
122*4882a593Smuzhiyun pm_runtime_put_sync(dev);
123*4882a593Smuzhiyun rpm_disable:
124*4882a593Smuzhiyun pm_runtime_disable(dev);
125*4882a593Smuzhiyun irq_dispose:
126*4882a593Smuzhiyun irq_dispose_mapping(irq);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return ret;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const struct dev_pm_ops gic_pm_ops = {
132*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(gic_runtime_suspend,
133*4882a593Smuzhiyun gic_runtime_resume, NULL)
134*4882a593Smuzhiyun SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
135*4882a593Smuzhiyun pm_runtime_force_resume)
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun static const char * const gic400_clocks[] = {
139*4882a593Smuzhiyun "clk",
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static const struct gic_clk_data gic400_data = {
143*4882a593Smuzhiyun .num_clocks = ARRAY_SIZE(gic400_clocks),
144*4882a593Smuzhiyun .clocks = gic400_clocks,
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const struct of_device_id gic_match[] = {
148*4882a593Smuzhiyun { .compatible = "nvidia,tegra210-agic", .data = &gic400_data },
149*4882a593Smuzhiyun {},
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, gic_match);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static struct platform_driver gic_driver = {
154*4882a593Smuzhiyun .probe = gic_probe,
155*4882a593Smuzhiyun .driver = {
156*4882a593Smuzhiyun .name = "gic",
157*4882a593Smuzhiyun .of_match_table = gic_match,
158*4882a593Smuzhiyun .pm = &gic_pm_ops,
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun builtin_platform_driver(gic_driver);
163