1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Aspeed 24XX/25XX I2C Interrupt Controller.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012-2017 ASPEED Technology Inc.
6*4882a593Smuzhiyun * Copyright 2017 IBM Corporation
7*4882a593Smuzhiyun * Copyright 2017 Google, Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/irq.h>
11*4882a593Smuzhiyun #include <linux/irqchip.h>
12*4882a593Smuzhiyun #include <linux/irqchip/chained_irq.h>
13*4882a593Smuzhiyun #include <linux/irqdomain.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/of_irq.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define ASPEED_I2C_IC_NUM_BUS 14
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct aspeed_i2c_ic {
22*4882a593Smuzhiyun void __iomem *base;
23*4882a593Smuzhiyun int parent_irq;
24*4882a593Smuzhiyun struct irq_domain *irq_domain;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * The aspeed chip provides a single hardware interrupt for all of the I2C
29*4882a593Smuzhiyun * busses, so we use a dummy interrupt chip to translate this single interrupt
30*4882a593Smuzhiyun * into multiple interrupts, each associated with a single I2C bus.
31*4882a593Smuzhiyun */
aspeed_i2c_ic_irq_handler(struct irq_desc * desc)32*4882a593Smuzhiyun static void aspeed_i2c_ic_irq_handler(struct irq_desc *desc)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct aspeed_i2c_ic *i2c_ic = irq_desc_get_handler_data(desc);
35*4882a593Smuzhiyun struct irq_chip *chip = irq_desc_get_chip(desc);
36*4882a593Smuzhiyun unsigned long bit, status;
37*4882a593Smuzhiyun unsigned int bus_irq;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun chained_irq_enter(chip, desc);
40*4882a593Smuzhiyun status = readl(i2c_ic->base);
41*4882a593Smuzhiyun for_each_set_bit(bit, &status, ASPEED_I2C_IC_NUM_BUS) {
42*4882a593Smuzhiyun bus_irq = irq_find_mapping(i2c_ic->irq_domain, bit);
43*4882a593Smuzhiyun generic_handle_irq(bus_irq);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun chained_irq_exit(chip, desc);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * Set simple handler and mark IRQ as valid. Nothing interesting to do here
50*4882a593Smuzhiyun * since we are using a dummy interrupt chip.
51*4882a593Smuzhiyun */
aspeed_i2c_ic_map_irq_domain(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)52*4882a593Smuzhiyun static int aspeed_i2c_ic_map_irq_domain(struct irq_domain *domain,
53*4882a593Smuzhiyun unsigned int irq, irq_hw_number_t hwirq)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
56*4882a593Smuzhiyun irq_set_chip_data(irq, domain->host_data);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static const struct irq_domain_ops aspeed_i2c_ic_irq_domain_ops = {
62*4882a593Smuzhiyun .map = aspeed_i2c_ic_map_irq_domain,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
aspeed_i2c_ic_of_init(struct device_node * node,struct device_node * parent)65*4882a593Smuzhiyun static int __init aspeed_i2c_ic_of_init(struct device_node *node,
66*4882a593Smuzhiyun struct device_node *parent)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct aspeed_i2c_ic *i2c_ic;
69*4882a593Smuzhiyun int ret = 0;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun i2c_ic = kzalloc(sizeof(*i2c_ic), GFP_KERNEL);
72*4882a593Smuzhiyun if (!i2c_ic)
73*4882a593Smuzhiyun return -ENOMEM;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun i2c_ic->base = of_iomap(node, 0);
76*4882a593Smuzhiyun if (!i2c_ic->base) {
77*4882a593Smuzhiyun ret = -ENOMEM;
78*4882a593Smuzhiyun goto err_free_ic;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun i2c_ic->parent_irq = irq_of_parse_and_map(node, 0);
82*4882a593Smuzhiyun if (!i2c_ic->parent_irq) {
83*4882a593Smuzhiyun ret = -EINVAL;
84*4882a593Smuzhiyun goto err_iounmap;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun i2c_ic->irq_domain = irq_domain_add_linear(node, ASPEED_I2C_IC_NUM_BUS,
88*4882a593Smuzhiyun &aspeed_i2c_ic_irq_domain_ops,
89*4882a593Smuzhiyun NULL);
90*4882a593Smuzhiyun if (!i2c_ic->irq_domain) {
91*4882a593Smuzhiyun ret = -ENOMEM;
92*4882a593Smuzhiyun goto err_iounmap;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun i2c_ic->irq_domain->name = "aspeed-i2c-domain";
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun irq_set_chained_handler_and_data(i2c_ic->parent_irq,
98*4882a593Smuzhiyun aspeed_i2c_ic_irq_handler, i2c_ic);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun pr_info("i2c controller registered, irq %d\n", i2c_ic->parent_irq);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun err_iounmap:
105*4882a593Smuzhiyun iounmap(i2c_ic->base);
106*4882a593Smuzhiyun err_free_ic:
107*4882a593Smuzhiyun kfree(i2c_ic);
108*4882a593Smuzhiyun return ret;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun IRQCHIP_DECLARE(ast2400_i2c_ic, "aspeed,ast2400-i2c-ic", aspeed_i2c_ic_of_init);
112*4882a593Smuzhiyun IRQCHIP_DECLARE(ast2500_i2c_ic, "aspeed,ast2500-i2c-ic", aspeed_i2c_ic_of_init);
113