1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ALPHASCALE_ASM9260_ICOLL_H 7*4882a593Smuzhiyun #define _ALPHASCALE_ASM9260_ICOLL_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define ASM9260_NUM_IRQS 64 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * this device provide 4 offsets for each register: 12*4882a593Smuzhiyun * 0x0 - plain read write mode 13*4882a593Smuzhiyun * 0x4 - set mode, OR logic. 14*4882a593Smuzhiyun * 0x8 - clr mode, XOR logic. 15*4882a593Smuzhiyun * 0xc - togle mode. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_VECTOR 0x0000 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * bits 31:2 21*4882a593Smuzhiyun * This register presents the vector address for the interrupt currently 22*4882a593Smuzhiyun * active on the CPU IRQ input. Writing to this register notifies the 23*4882a593Smuzhiyun * interrupt collector that the interrupt service routine for the current 24*4882a593Smuzhiyun * interrupt has been entered. 25*4882a593Smuzhiyun * The exception trap should have a LDPC instruction from this address: 26*4882a593Smuzhiyun * LDPC ASM9260_HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * The Interrupt Collector Level Acknowledge Register is used by software to 31*4882a593Smuzhiyun * indicate the completion of an interrupt on a specific level. 32*4882a593Smuzhiyun * This register is written at the very end of an interrupt service routine. If 33*4882a593Smuzhiyun * nesting is used then the CPU irq must be turned on before writing to this 34*4882a593Smuzhiyun * register to avoid a race condition in the CPU interrupt hardware. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_LEVELACK 0x0010 37*4882a593Smuzhiyun #define ASM9260_BM_LEVELn(nr) BIT(nr) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_CTRL 0x0020 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * ASM9260_BM_CTRL_SFTRST and ASM9260_BM_CTRL_CLKGATE are not available on 42*4882a593Smuzhiyun * asm9260. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define ASM9260_BM_CTRL_SFTRST BIT(31) 45*4882a593Smuzhiyun #define ASM9260_BM_CTRL_CLKGATE BIT(30) 46*4882a593Smuzhiyun /* disable interrupt level nesting */ 47*4882a593Smuzhiyun #define ASM9260_BM_CTRL_NO_NESTING BIT(19) 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Set this bit to one enable the RISC32-style read side effect associated with 50*4882a593Smuzhiyun * the vector address register. In this mode, interrupt in-service is signaled 51*4882a593Smuzhiyun * by the read of the ASM9260_HW_ICOLL_VECTOR register to acquire the interrupt 52*4882a593Smuzhiyun * vector address. Set this bit to zero for normal operation, in which the ISR 53*4882a593Smuzhiyun * signals in-service explicitly by means of a write to the 54*4882a593Smuzhiyun * ASM9260_HW_ICOLL_VECTOR register. 55*4882a593Smuzhiyun * 0 - Must Write to Vector register to go in-service. 56*4882a593Smuzhiyun * 1 - Go in-service as a read side effect 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define ASM9260_BM_CTRL_ARM_RSE_MODE BIT(18) 59*4882a593Smuzhiyun #define ASM9260_BM_CTRL_IRQ_ENABLE BIT(16) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_STAT_OFFSET 0x0030 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * bits 5:0 64*4882a593Smuzhiyun * Vector number of current interrupt. Multiply by 4 and add to vector base 65*4882a593Smuzhiyun * address to obtain the value in ASM9260_HW_ICOLL_VECTOR. 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * RAW0 and RAW1 provides a read-only view of the raw interrupt request lines 70*4882a593Smuzhiyun * coming from various parts of the chip. Its purpose is to improve diagnostic 71*4882a593Smuzhiyun * observability. 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_RAW0 0x0040 74*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_RAW1 0x0050 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_INTERRUPT0 0x0060 77*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_INTERRUPTn(n) (0x0060 + ((n) >> 2) * 0x10) 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * WARNING: Modifying the priority of an enabled interrupt may result in 80*4882a593Smuzhiyun * undefined behavior. 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun #define ASM9260_BM_INT_PRIORITY_MASK 0x3 83*4882a593Smuzhiyun #define ASM9260_BM_INT_ENABLE BIT(2) 84*4882a593Smuzhiyun #define ASM9260_BM_INT_SOFTIRQ BIT(3) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n) (((n) & 0x3) << 3) 87*4882a593Smuzhiyun #define ASM9260_BM_ICOLL_INTERRUPTn_ENABLE(n) (1 << (2 + \ 88*4882a593Smuzhiyun ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n))) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_VBASE 0x0160 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * bits 31:2 93*4882a593Smuzhiyun * This bitfield holds the upper 30 bits of the base address of the vector 94*4882a593Smuzhiyun * table. 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_CLEAR0 0x01d0 98*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_CLEAR1 0x01e0 99*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_CLEARn(n) (((n >> 5) * 0x10) \ 100*4882a593Smuzhiyun + SET_REG) 101*4882a593Smuzhiyun #define ASM9260_BM_CLEAR_BIT(n) BIT(n & 0x1f) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Scratchpad */ 104*4882a593Smuzhiyun #define ASM9260_HW_ICOLL_UNDEF_VECTOR 0x01f0 105*4882a593Smuzhiyun #endif 106