1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IOMMU API for Rockchip
4 *
5 * Module Authors: Simon Xue <xxm@rock-chips.com>
6 * Daniel Kurtz <djkurtz@chromium.org>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/compiler.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/dma-iommu.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iommu.h>
19 #include <linux/iopoll.h>
20 #include <linux/list.h>
21 #include <linux/mm.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/of_iommu.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <soc/rockchip/rockchip_iommu.h>
32
33 /** MMU register offsets */
34 #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */
35 #define RK_MMU_STATUS 0x04
36 #define RK_MMU_COMMAND 0x08
37 #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */
38 #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */
39 #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */
40 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
41 #define RK_MMU_INT_MASK 0x1C /* IRQ enable */
42 #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */
43 #define RK_MMU_AUTO_GATING 0x24
44
45 #define DTE_ADDR_DUMMY 0xCAFEBABE
46
47 #define RK_MMU_POLL_PERIOD_US 100
48 #define RK_MMU_FORCE_RESET_TIMEOUT_US 100000
49 #define RK_MMU_POLL_TIMEOUT_US 1000
50
51 /* RK_MMU_STATUS fields */
52 #define RK_MMU_STATUS_PAGING_ENABLED BIT(0)
53 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1)
54 #define RK_MMU_STATUS_STALL_ACTIVE BIT(2)
55 #define RK_MMU_STATUS_IDLE BIT(3)
56 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)
57 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)
58 #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31)
59
60 /* RK_MMU_COMMAND command values */
61 #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */
62 #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */
63 #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */
64 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
65 #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */
66 #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */
67 #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */
68
69 /* RK_MMU_INT_* register fields */
70 #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */
71 #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */
72 #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
73
74 #define NUM_DT_ENTRIES 1024
75 #define NUM_PT_ENTRIES 1024
76
77 #define SPAGE_ORDER 12
78 #define SPAGE_SIZE (1 << SPAGE_ORDER)
79
80 #define DISABLE_FETCH_DTE_TIME_LIMIT BIT(31)
81
82 #define CMD_RETRY_COUNT 10
83
84 /*
85 * Support mapping any size that fits in one page table:
86 * 4 KiB to 4 MiB
87 */
88 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
89
90 struct rk_iommu_domain {
91 struct list_head iommus;
92 u32 *dt; /* page directory table */
93 dma_addr_t dt_dma;
94 spinlock_t iommus_lock; /* lock for iommus list */
95 spinlock_t dt_lock; /* lock for modifying page directory table */
96 bool shootdown_entire;
97
98 struct iommu_domain domain;
99 };
100
101 struct rk_iommu_ops {
102 phys_addr_t (*pt_address)(u32 dte);
103 u32 (*mk_dtentries)(dma_addr_t pt_dma);
104 u32 (*mk_ptentries)(phys_addr_t page, int prot);
105 phys_addr_t (*dte_addr_phys)(u32 addr);
106 u32 (*dma_addr_dte)(dma_addr_t dt_dma);
107 u64 dma_bit_mask;
108 };
109
110 struct rk_iommu {
111 struct device *dev;
112 void __iomem **bases;
113 int num_mmu;
114 int num_irq;
115 struct clk_bulk_data *clocks;
116 int num_clocks;
117 bool reset_disabled;
118 bool skip_read; /* rk3126/rk3128 can't read vop iommu registers */
119 bool dlr_disable; /* avoid access iommu when runtime ops called */
120 bool cmd_retry;
121 bool master_handle_irq;
122 struct iommu_device iommu;
123 struct list_head node; /* entry in rk_iommu_domain.iommus */
124 struct iommu_domain *domain; /* domain to which iommu is attached */
125 struct iommu_group *group;
126 bool shootdown_entire;
127 bool iommu_enabled;
128 bool need_res_map;
129 };
130
131 struct rk_iommudata {
132 struct device_link *link; /* runtime PM link from IOMMU to master */
133 struct rk_iommu *iommu;
134 bool defer_attach;
135 };
136
137 static struct device *dma_dev;
138 static const struct rk_iommu_ops *rk_ops;
139 static struct rk_iommu *rk_iommu_from_dev(struct device *dev);
140 static char reserve_range[PAGE_SIZE] __aligned(PAGE_SIZE);
141 static phys_addr_t res_page;
142
rk_table_flush(struct rk_iommu_domain * dom,dma_addr_t dma,unsigned int count)143 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
144 unsigned int count)
145 {
146 size_t size = count * sizeof(u32); /* count of u32 entry */
147
148 dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
149 }
150
to_rk_domain(struct iommu_domain * dom)151 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
152 {
153 return container_of(dom, struct rk_iommu_domain, domain);
154 }
155
156 /*
157 * The Rockchip rk3288 iommu uses a 2-level page table.
158 * The first level is the "Directory Table" (DT).
159 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
160 * to a "Page Table".
161 * The second level is the 1024 Page Tables (PT).
162 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
163 * a 4 KB page of physical memory.
164 *
165 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
166 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
167 * address of the start of the DT page.
168 *
169 * The structure of the page table is as follows:
170 *
171 * DT
172 * MMU_DTE_ADDR -> +-----+
173 * | |
174 * +-----+ PT
175 * | DTE | -> +-----+
176 * +-----+ | | Memory
177 * | | +-----+ Page
178 * | | | PTE | -> +-----+
179 * +-----+ +-----+ | |
180 * | | | |
181 * | | | |
182 * +-----+ | |
183 * | |
184 * | |
185 * +-----+
186 */
187
188 /*
189 * Each DTE has a PT address and a valid bit:
190 * +---------------------+-----------+-+
191 * | PT address | Reserved |V|
192 * +---------------------+-----------+-+
193 * 31:12 - PT address (PTs always starts on a 4 KB boundary)
194 * 11: 1 - Reserved
195 * 0 - 1 if PT @ PT address is valid
196 */
197 #define RK_DTE_PT_ADDRESS_MASK 0xfffff000
198 #define RK_DTE_PT_VALID BIT(0)
199
rk_dte_pt_address(u32 dte)200 static inline phys_addr_t rk_dte_pt_address(u32 dte)
201 {
202 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
203 }
204
205 /*
206 * In v2:
207 * 31:12 - PT address bit 31:0
208 * 11: 8 - PT address bit 35:32
209 * 7: 4 - PT address bit 39:36
210 * 3: 1 - Reserved
211 * 0 - 1 if PT @ PT address is valid
212 */
213 #define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
214 #define DTE_HI_MASK1 GENMASK(11, 8)
215 #define DTE_HI_MASK2 GENMASK(7, 4)
216 #define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
217 #define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
218 #define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32)
219 #define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36)
220
rk_dte_pt_address_v2(u32 dte)221 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
222 {
223 u64 dte_v2 = dte;
224
225 dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
226 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
227 (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
228
229 return (phys_addr_t)dte_v2;
230 }
231
rk_dte_is_pt_valid(u32 dte)232 static inline bool rk_dte_is_pt_valid(u32 dte)
233 {
234 return dte & RK_DTE_PT_VALID;
235 }
236
rk_mk_dte(dma_addr_t pt_dma)237 static inline u32 rk_mk_dte(dma_addr_t pt_dma)
238 {
239 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
240 }
241
rk_mk_dte_v2(dma_addr_t pt_dma)242 static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
243 {
244 pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
245 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
246 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
247
248 return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
249 }
250
251 /*
252 * Each PTE has a Page address, some flags and a valid bit:
253 * +---------------------+---+-------+-+
254 * | Page address |Rsv| Flags |V|
255 * +---------------------+---+-------+-+
256 * 31:12 - Page address (Pages always start on a 4 KB boundary)
257 * 11: 9 - Reserved
258 * 8: 1 - Flags
259 * 8 - Read allocate - allocate cache space on read misses
260 * 7 - Read cache - enable cache & prefetch of data
261 * 6 - Write buffer - enable delaying writes on their way to memory
262 * 5 - Write allocate - allocate cache space on write misses
263 * 4 - Write cache - different writes can be merged together
264 * 3 - Override cache attributes
265 * if 1, bits 4-8 control cache attributes
266 * if 0, the system bus defaults are used
267 * 2 - Writable
268 * 1 - Readable
269 * 0 - 1 if Page @ Page address is valid
270 */
271 #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000
272 #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe
273 #define RK_PTE_PAGE_WRITABLE BIT(2)
274 #define RK_PTE_PAGE_READABLE BIT(1)
275 #define RK_PTE_PAGE_VALID BIT(0)
276
rk_pte_is_page_valid(u32 pte)277 static inline bool rk_pte_is_page_valid(u32 pte)
278 {
279 return pte & RK_PTE_PAGE_VALID;
280 }
281
282 #define RK_PTE_PAGE_REPRESENT BIT(3)
283
rk_pte_is_page_represent(u32 pte)284 static inline bool rk_pte_is_page_represent(u32 pte)
285 {
286 return pte & RK_PTE_PAGE_REPRESENT;
287 }
288
289 /* TODO: set cache flags per prot IOMMU_CACHE */
rk_mk_pte(phys_addr_t page,int prot)290 static u32 rk_mk_pte(phys_addr_t page, int prot)
291 {
292 u32 flags = 0;
293 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
294 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
295 flags |= (prot & IOMMU_PRIV) ? RK_PTE_PAGE_REPRESENT : 0;
296 page &= RK_PTE_PAGE_ADDRESS_MASK;
297 return page | flags | RK_PTE_PAGE_VALID;
298 }
299
rk_mk_pte_v2(phys_addr_t page,int prot)300 static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
301 {
302 u32 flags = 0;
303
304 /* If BIT(3) set, don't break iommu_map if BIT(0) set.
305 * Means we can reupdate a page that already presented. We can use
306 * this bit to reupdate a pre-mapped 4G range.
307 */
308 flags |= (prot & IOMMU_PRIV) ? RK_PTE_PAGE_REPRESENT : 0;
309
310 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
311 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
312
313 return rk_mk_dte_v2(page) | flags;
314 }
315
rk_mk_pte_invalid(u32 pte)316 static u32 rk_mk_pte_invalid(u32 pte)
317 {
318 return pte & ~(RK_PTE_PAGE_VALID | RK_PTE_PAGE_REPRESENT);
319 }
320
321 /*
322 * rk3288 iova (IOMMU Virtual Address) format
323 * 31 22.21 12.11 0
324 * +-----------+-----------+-------------+
325 * | DTE index | PTE index | Page offset |
326 * +-----------+-----------+-------------+
327 * 31:22 - DTE index - index of DTE in DT
328 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address
329 * 11: 0 - Page offset - offset into page @ PTE.page_address
330 */
331 #define RK_IOVA_DTE_MASK 0xffc00000
332 #define RK_IOVA_DTE_SHIFT 22
333 #define RK_IOVA_PTE_MASK 0x003ff000
334 #define RK_IOVA_PTE_SHIFT 12
335 #define RK_IOVA_PAGE_MASK 0x00000fff
336 #define RK_IOVA_PAGE_SHIFT 0
337
rk_iova_dte_index(dma_addr_t iova)338 static u32 rk_iova_dte_index(dma_addr_t iova)
339 {
340 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
341 }
342
rk_iova_pte_index(dma_addr_t iova)343 static u32 rk_iova_pte_index(dma_addr_t iova)
344 {
345 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
346 }
347
rk_iova_page_offset(dma_addr_t iova)348 static u32 rk_iova_page_offset(dma_addr_t iova)
349 {
350 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
351 }
352
rk_iommu_read(void __iomem * base,u32 offset)353 static u32 rk_iommu_read(void __iomem *base, u32 offset)
354 {
355 return readl(base + offset);
356 }
357
rk_iommu_write(void __iomem * base,u32 offset,u32 value)358 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
359 {
360 writel(value, base + offset);
361 }
362
rk_iommu_command(struct rk_iommu * iommu,u32 command)363 static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
364 {
365 int i;
366
367 for (i = 0; i < iommu->num_mmu; i++)
368 writel(command, iommu->bases[i] + RK_MMU_COMMAND);
369 }
370
rk_iommu_base_command(void __iomem * base,u32 command)371 static void rk_iommu_base_command(void __iomem *base, u32 command)
372 {
373 writel(command, base + RK_MMU_COMMAND);
374 }
rk_iommu_zap_lines(struct rk_iommu * iommu,dma_addr_t iova_start,size_t size)375 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
376 size_t size)
377 {
378 int i;
379 dma_addr_t iova_end = iova_start + size;
380 /*
381 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
382 * entire iotlb rather than iterate over individual iovas.
383 */
384 for (i = 0; i < iommu->num_mmu; i++) {
385 dma_addr_t iova;
386
387 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
388 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
389 }
390 }
391
rk_iommu_is_stall_active(struct rk_iommu * iommu)392 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
393 {
394 bool active = true;
395 int i;
396
397 for (i = 0; i < iommu->num_mmu; i++)
398 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
399 RK_MMU_STATUS_STALL_ACTIVE);
400
401 return active;
402 }
403
rk_iommu_is_paging_enabled(struct rk_iommu * iommu)404 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
405 {
406 bool enable = true;
407 int i;
408
409 for (i = 0; i < iommu->num_mmu; i++)
410 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
411 RK_MMU_STATUS_PAGING_ENABLED);
412
413 return enable;
414 }
415
rk_iommu_is_reset_done(struct rk_iommu * iommu)416 static bool rk_iommu_is_reset_done(struct rk_iommu *iommu)
417 {
418 bool done = true;
419 int i;
420
421 for (i = 0; i < iommu->num_mmu; i++)
422 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
423
424 return done;
425 }
426
rk_iommu_enable_stall(struct rk_iommu * iommu)427 static int rk_iommu_enable_stall(struct rk_iommu *iommu)
428 {
429 int ret, i;
430 bool val;
431 int retry_count = 0;
432
433 if (iommu->skip_read)
434 goto read_wa;
435
436 if (rk_iommu_is_stall_active(iommu))
437 return 0;
438
439 /* Stall can only be enabled if paging is enabled */
440 if (!rk_iommu_is_paging_enabled(iommu))
441 return 0;
442
443 read_wa:
444 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
445 if (iommu->skip_read)
446 return 0;
447
448 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
449 val, RK_MMU_POLL_PERIOD_US,
450 RK_MMU_POLL_TIMEOUT_US);
451 if (ret) {
452 for (i = 0; i < iommu->num_mmu; i++)
453 dev_err(iommu->dev, "Enable stall request timed out, retry_count = %d, status: %#08x\n",
454 retry_count,
455 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
456 if (iommu->cmd_retry && (retry_count++ < CMD_RETRY_COUNT))
457 goto read_wa;
458 }
459
460 return ret;
461 }
462
rk_iommu_disable_stall(struct rk_iommu * iommu)463 static int rk_iommu_disable_stall(struct rk_iommu *iommu)
464 {
465 int ret, i;
466 bool val;
467 int retry_count = 0;
468
469 if (iommu->skip_read)
470 goto read_wa;
471
472 if (!rk_iommu_is_stall_active(iommu))
473 return 0;
474
475 read_wa:
476 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
477 if (iommu->skip_read)
478 return 0;
479
480 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
481 !val, RK_MMU_POLL_PERIOD_US,
482 RK_MMU_POLL_TIMEOUT_US);
483 if (ret) {
484 for (i = 0; i < iommu->num_mmu; i++)
485 dev_err(iommu->dev, "Disable stall request timed out, retry_count = %d, status: %#08x\n",
486 retry_count,
487 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
488 if (iommu->cmd_retry && (retry_count++ < CMD_RETRY_COUNT))
489 goto read_wa;
490 }
491
492 return ret;
493 }
494
rk_iommu_enable_paging(struct rk_iommu * iommu)495 static int rk_iommu_enable_paging(struct rk_iommu *iommu)
496 {
497 int ret, i;
498 bool val;
499 int retry_count = 0;
500
501 if (iommu->skip_read)
502 goto read_wa;
503
504 if (rk_iommu_is_paging_enabled(iommu))
505 return 0;
506
507 read_wa:
508 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
509 if (iommu->skip_read)
510 return 0;
511
512 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
513 val, RK_MMU_POLL_PERIOD_US,
514 RK_MMU_POLL_TIMEOUT_US);
515 if (ret) {
516 for (i = 0; i < iommu->num_mmu; i++)
517 dev_err(iommu->dev, "Enable paging request timed out, retry_count = %d, status: %#08x\n",
518 retry_count,
519 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
520 if (iommu->cmd_retry && (retry_count++ < CMD_RETRY_COUNT))
521 goto read_wa;
522 }
523
524 return ret;
525 }
526
rk_iommu_disable_paging(struct rk_iommu * iommu)527 static int rk_iommu_disable_paging(struct rk_iommu *iommu)
528 {
529 int ret, i;
530 bool val;
531 int retry_count = 0;
532
533 if (iommu->skip_read)
534 goto read_wa;
535
536 if (!rk_iommu_is_paging_enabled(iommu))
537 return 0;
538
539 read_wa:
540 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
541 if (iommu->skip_read)
542 return 0;
543
544 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
545 !val, RK_MMU_POLL_PERIOD_US,
546 RK_MMU_POLL_TIMEOUT_US);
547 if (ret) {
548 for (i = 0; i < iommu->num_mmu; i++)
549 dev_err(iommu->dev, "Disable paging request timed out, retry_count = %d, status: %#08x\n",
550 retry_count,
551 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
552 if (iommu->cmd_retry && (retry_count++ < CMD_RETRY_COUNT))
553 goto read_wa;
554 }
555
556 return ret;
557 }
558
rk_iommu_read_dte_addr(void __iomem * base)559 static u32 rk_iommu_read_dte_addr(void __iomem *base)
560 {
561 return rk_iommu_read(base, RK_MMU_DTE_ADDR);
562 }
563
rk_iommu_force_reset(struct rk_iommu * iommu)564 static int rk_iommu_force_reset(struct rk_iommu *iommu)
565 {
566 int ret, i;
567 u32 dte_addr;
568 bool val;
569 u32 dte_address_mask;
570
571 if (iommu->reset_disabled)
572 return 0;
573
574 if (iommu->skip_read)
575 goto read_wa;
576
577 /*
578 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
579 * and verifying that upper 5 nybbles are read back.
580 */
581
582 /*
583 * In v2: upper 7 nybbles are read back.
584 */
585 for (i = 0; i < iommu->num_mmu; i++) {
586 dte_address_mask = rk_ops->pt_address(DTE_ADDR_DUMMY);
587 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_address_mask);
588
589 ret = readx_poll_timeout(rk_iommu_read_dte_addr, iommu->bases[i], dte_addr,
590 dte_addr == dte_address_mask,
591 RK_MMU_POLL_PERIOD_US, RK_MMU_POLL_TIMEOUT_US);
592 if (ret) {
593 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
594 return -EFAULT;
595 }
596 }
597
598 read_wa:
599 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
600 if (iommu->skip_read)
601 return 0;
602
603 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val,
604 val, RK_MMU_POLL_TIMEOUT_US,
605 RK_MMU_FORCE_RESET_TIMEOUT_US);
606 if (ret) {
607 dev_err(iommu->dev, "FORCE_RESET command timed out\n");
608 return ret;
609 }
610
611 return 0;
612 }
613
rk_dte_addr_phys(u32 addr)614 static inline phys_addr_t rk_dte_addr_phys(u32 addr)
615 {
616 return (phys_addr_t)addr;
617 }
618
rk_dma_addr_dte(dma_addr_t dt_dma)619 static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
620 {
621 return dt_dma;
622 }
623
624 #define DT_HI_MASK GENMASK_ULL(39, 32)
625 #define DTE_BASE_HI_MASK GENMASK(11, 4)
626 #define DT_SHIFT 28
627
rk_dte_addr_phys_v2(u32 addr)628 static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
629 {
630 u64 addr64 = addr;
631 return (phys_addr_t)(addr64 & RK_DTE_PT_ADDRESS_MASK) |
632 ((addr64 & DTE_BASE_HI_MASK) << DT_SHIFT);
633 }
634
rk_dma_addr_dte_v2(dma_addr_t dt_dma)635 static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
636 {
637 return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
638 ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
639 }
640
log_iova(struct rk_iommu * iommu,int index,dma_addr_t iova)641 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
642 {
643 void __iomem *base = iommu->bases[index];
644 u32 dte_index, pte_index, page_offset;
645 u32 mmu_dte_addr;
646 phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
647 u32 *dte_addr;
648 u32 dte;
649 phys_addr_t pte_addr_phys = 0;
650 u32 *pte_addr = NULL;
651 u32 pte = 0;
652 phys_addr_t page_addr_phys = 0;
653 u32 page_flags = 0;
654
655 dte_index = rk_iova_dte_index(iova);
656 pte_index = rk_iova_pte_index(iova);
657 page_offset = rk_iova_page_offset(iova);
658
659 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
660 mmu_dte_addr_phys = rk_ops->dte_addr_phys(mmu_dte_addr);
661
662 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
663 dte_addr = phys_to_virt(dte_addr_phys);
664 dte = *dte_addr;
665
666 if (!rk_dte_is_pt_valid(dte))
667 goto print_it;
668
669 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4);
670 pte_addr = phys_to_virt(pte_addr_phys);
671 pte = *pte_addr;
672
673 if (!rk_pte_is_page_valid(pte))
674 goto print_it;
675
676 page_addr_phys = rk_ops->pt_address(pte) + page_offset;
677 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
678
679 print_it:
680 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
681 &iova, dte_index, pte_index, page_offset);
682 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
683 &mmu_dte_addr_phys, &dte_addr_phys, dte,
684 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
685 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
686 }
687
rk_pagefault_done(struct rk_iommu * iommu)688 static int rk_pagefault_done(struct rk_iommu *iommu)
689 {
690 u32 status;
691 u32 int_status;
692 dma_addr_t iova;
693 int i;
694 u32 int_mask;
695 irqreturn_t ret = IRQ_NONE;
696
697 for (i = 0; i < iommu->num_mmu; i++) {
698 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
699 if (int_status == 0)
700 continue;
701
702 ret = IRQ_HANDLED;
703 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
704
705 if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
706 int flags;
707
708 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
709 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
710 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
711
712 dev_err(iommu->dev, "Page fault at %pad of type %s\n",
713 &iova,
714 (flags == IOMMU_FAULT_WRITE) ? "write" : "read");
715
716 log_iova(iommu, i, iova);
717
718 if (!iommu->master_handle_irq) {
719 /*
720 * Report page fault to any installed handlers.
721 * Ignore the return code, though, since we always zap cache
722 * and clear the page fault anyway.
723 */
724 if (iommu->domain)
725 report_iommu_fault(iommu->domain, iommu->dev, iova,
726 status);
727 else
728 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
729 }
730
731 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
732
733 /*
734 * Master may clear the int_mask to prevent iommu
735 * re-enter interrupt when mapping. So we postpone
736 * sending PAGE_FAULT_DONE command to mapping finished.
737 */
738 int_mask = rk_iommu_read(iommu->bases[i], RK_MMU_INT_MASK);
739 if (int_mask != 0x0)
740 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
741 }
742
743 if (int_status & RK_MMU_IRQ_BUS_ERROR)
744 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
745
746 if (int_status & ~RK_MMU_IRQ_MASK)
747 dev_err(iommu->dev, "unexpected int_status: %#08x\n",
748 int_status);
749
750 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
751 }
752
753 return ret;
754 }
755
rockchip_pagefault_done(struct device * master_dev)756 int rockchip_pagefault_done(struct device *master_dev)
757 {
758 struct rk_iommu *iommu = rk_iommu_from_dev(master_dev);
759
760 return rk_pagefault_done(iommu);
761 }
762 EXPORT_SYMBOL_GPL(rockchip_pagefault_done);
763
rockchip_get_iommu_base(struct device * master_dev,int idx)764 void __iomem *rockchip_get_iommu_base(struct device *master_dev, int idx)
765 {
766 struct rk_iommu *iommu = rk_iommu_from_dev(master_dev);
767
768 return iommu->bases[idx];
769 }
770 EXPORT_SYMBOL_GPL(rockchip_get_iommu_base);
771
rk_iommu_irq(int irq,void * dev_id)772 static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
773 {
774 struct rk_iommu *iommu = dev_id;
775 irqreturn_t ret = IRQ_NONE;
776 int err;
777
778 err = pm_runtime_get_if_in_use(iommu->dev);
779 if (WARN_ON_ONCE(err <= 0))
780 return ret;
781
782 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)))
783 goto out;
784
785 /* Master must call rockchip_pagefault_done to handle pagefault */
786 if (iommu->master_handle_irq) {
787 if (iommu->domain)
788 ret = report_iommu_fault(iommu->domain, iommu->dev, -1, 0x0);
789 } else {
790 ret = rk_pagefault_done(iommu);
791 }
792
793 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
794
795 out:
796 pm_runtime_put(iommu->dev);
797 return ret;
798 }
799
rk_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)800 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
801 dma_addr_t iova)
802 {
803 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
804 unsigned long flags;
805 phys_addr_t pt_phys, phys = 0;
806 u32 dte, pte;
807 u32 *page_table;
808
809 spin_lock_irqsave(&rk_domain->dt_lock, flags);
810
811 dte = rk_domain->dt[rk_iova_dte_index(iova)];
812 if (!rk_dte_is_pt_valid(dte))
813 goto out;
814
815 pt_phys = rk_ops->pt_address(dte);
816 page_table = (u32 *)phys_to_virt(pt_phys);
817 pte = page_table[rk_iova_pte_index(iova)];
818 if (!rk_pte_is_page_valid(pte))
819 goto out;
820
821 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova);
822 out:
823 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
824
825 return phys;
826 }
827
rk_iommu_zap_iova(struct rk_iommu_domain * rk_domain,dma_addr_t iova,size_t size)828 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
829 dma_addr_t iova, size_t size)
830 {
831 struct list_head *pos;
832 unsigned long flags;
833
834 /* Do not zap tlb cache line if shootdown_entire set */
835 if (rk_domain->shootdown_entire)
836 return;
837
838 /* shootdown these iova from all iommus using this domain */
839 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
840 list_for_each(pos, &rk_domain->iommus) {
841 struct rk_iommu *iommu;
842 int ret;
843
844 iommu = list_entry(pos, struct rk_iommu, node);
845
846 /* Only zap TLBs of IOMMUs that are powered on. */
847 ret = pm_runtime_get_if_in_use(iommu->dev);
848 if (WARN_ON_ONCE(ret < 0))
849 continue;
850 if (ret) {
851 WARN_ON(clk_bulk_enable(iommu->num_clocks,
852 iommu->clocks));
853 rk_iommu_zap_lines(iommu, iova, size);
854 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
855 pm_runtime_put(iommu->dev);
856 }
857 }
858 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
859 }
860
rk_iommu_zap_iova_first_last(struct rk_iommu_domain * rk_domain,dma_addr_t iova,size_t size)861 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
862 dma_addr_t iova, size_t size)
863 {
864 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
865 if (size > SPAGE_SIZE)
866 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
867 SPAGE_SIZE);
868 }
869
rk_dte_get_page_table(struct rk_iommu_domain * rk_domain,dma_addr_t iova)870 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
871 dma_addr_t iova)
872 {
873 u32 *page_table, *dte_addr;
874 u32 dte_index, dte;
875 phys_addr_t pt_phys;
876 dma_addr_t pt_dma;
877
878 assert_spin_locked(&rk_domain->dt_lock);
879
880 dte_index = rk_iova_dte_index(iova);
881 dte_addr = &rk_domain->dt[dte_index];
882 dte = *dte_addr;
883 if (rk_dte_is_pt_valid(dte))
884 goto done;
885
886 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
887 if (!page_table)
888 return ERR_PTR(-ENOMEM);
889
890 pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
891 if (dma_mapping_error(dma_dev, pt_dma)) {
892 dev_err(dma_dev, "DMA mapping error while allocating page table\n");
893 free_page((unsigned long)page_table);
894 return ERR_PTR(-ENOMEM);
895 }
896
897 dte = rk_ops->mk_dtentries(pt_dma);
898 *dte_addr = dte;
899
900 rk_table_flush(rk_domain,
901 rk_domain->dt_dma + dte_index * sizeof(u32), 1);
902 done:
903 pt_phys = rk_ops->pt_address(dte);
904 return (u32 *)phys_to_virt(pt_phys);
905 }
906
rk_iommu_unmap_iova(struct rk_iommu_domain * rk_domain,u32 * pte_addr,dma_addr_t pte_dma,size_t size,struct rk_iommu * iommu)907 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
908 u32 *pte_addr, dma_addr_t pte_dma,
909 size_t size, struct rk_iommu *iommu)
910 {
911 unsigned int pte_count;
912 unsigned int pte_total = size / SPAGE_SIZE;
913 int prot = IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV;
914
915 assert_spin_locked(&rk_domain->dt_lock);
916
917 for (pte_count = 0; pte_count < pte_total; pte_count++) {
918 u32 pte = pte_addr[pte_count];
919 if (!rk_pte_is_page_valid(pte))
920 break;
921
922 if (iommu && iommu->need_res_map)
923 pte_addr[pte_count] = rk_ops->mk_ptentries(res_page,
924 prot);
925 else
926 pte_addr[pte_count] = rk_mk_pte_invalid(pte);
927 }
928
929 rk_table_flush(rk_domain, pte_dma, pte_count);
930
931 return pte_count * SPAGE_SIZE;
932 }
933
rk_iommu_get(struct rk_iommu_domain * rk_domain)934 static struct rk_iommu *rk_iommu_get(struct rk_iommu_domain *rk_domain)
935 {
936 unsigned long flags;
937 struct list_head *pos;
938 struct rk_iommu *iommu = NULL;
939
940 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
941 list_for_each(pos, &rk_domain->iommus) {
942 iommu = list_entry(pos, struct rk_iommu, node);
943 if (iommu->need_res_map)
944 break;
945 }
946 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
947
948 return iommu;
949 }
950
rk_iommu_map_iova(struct rk_iommu_domain * rk_domain,u32 * pte_addr,dma_addr_t pte_dma,dma_addr_t iova,phys_addr_t paddr,size_t size,int prot)951 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
952 dma_addr_t pte_dma, dma_addr_t iova,
953 phys_addr_t paddr, size_t size, int prot)
954 {
955 unsigned int pte_count;
956 unsigned int pte_total = size / SPAGE_SIZE;
957 phys_addr_t page_phys;
958
959 assert_spin_locked(&rk_domain->dt_lock);
960
961 for (pte_count = 0; pte_count < pte_total; pte_count++) {
962 u32 pte = pte_addr[pte_count];
963
964 if (rk_pte_is_page_valid(pte) && !rk_pte_is_page_represent(pte))
965 goto unwind;
966
967 if (prot & IOMMU_PRIV) {
968 pte_addr[pte_count] = rk_ops->mk_ptentries(res_page, prot);
969 } else {
970 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot);
971
972 paddr += SPAGE_SIZE;
973 }
974 }
975
976 rk_table_flush(rk_domain, pte_dma, pte_total);
977
978 /*
979 * Zap the first and last iova to evict from iotlb any previously
980 * mapped cachelines holding stale values for its dte and pte.
981 * We only zap the first and last iova, since only they could have
982 * dte or pte shared with an existing mapping.
983 */
984 rk_iommu_zap_iova_first_last(rk_domain, iova, size);
985
986 return 0;
987 unwind:
988 /* Unmap the range of iovas that we just mapped */
989 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
990 pte_count * SPAGE_SIZE, NULL);
991
992 iova += pte_count * SPAGE_SIZE;
993 page_phys = rk_ops->pt_address(pte_addr[pte_count]);
994 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
995 &iova, &page_phys, &paddr, prot);
996
997 return -EADDRINUSE;
998 }
999
rk_iommu_map(struct iommu_domain * domain,unsigned long _iova,phys_addr_t paddr,size_t size,int prot,gfp_t gfp)1000 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
1001 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
1002 {
1003 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1004 unsigned long flags;
1005 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
1006 u32 *page_table, *pte_addr;
1007 u32 dte, pte_index;
1008 int ret;
1009
1010 spin_lock_irqsave(&rk_domain->dt_lock, flags);
1011
1012 /*
1013 * pgsize_bitmap specifies iova sizes that fit in one page table
1014 * (1024 4-KiB pages = 4 MiB).
1015 * So, size will always be 4096 <= size <= 4194304.
1016 * Since iommu_map() guarantees that both iova and size will be
1017 * aligned, we will always only be mapping from a single dte here.
1018 */
1019 page_table = rk_dte_get_page_table(rk_domain, iova);
1020 if (IS_ERR(page_table)) {
1021 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
1022 return PTR_ERR(page_table);
1023 }
1024
1025 dte = rk_domain->dt[rk_iova_dte_index(iova)];
1026 pte_index = rk_iova_pte_index(iova);
1027 pte_addr = &page_table[pte_index];
1028 pte_dma = rk_ops->pt_address(dte) + pte_index * sizeof(u32);
1029 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
1030 paddr, size, prot);
1031
1032 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
1033
1034 return ret;
1035 }
1036
rk_iommu_unmap(struct iommu_domain * domain,unsigned long _iova,size_t size,struct iommu_iotlb_gather * gather)1037 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
1038 size_t size, struct iommu_iotlb_gather *gather)
1039 {
1040 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1041 unsigned long flags;
1042 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
1043 phys_addr_t pt_phys;
1044 u32 dte;
1045 u32 *pte_addr;
1046 size_t unmap_size;
1047 struct rk_iommu *iommu = rk_iommu_get(rk_domain);
1048
1049 spin_lock_irqsave(&rk_domain->dt_lock, flags);
1050
1051 /*
1052 * pgsize_bitmap specifies iova sizes that fit in one page table
1053 * (1024 4-KiB pages = 4 MiB).
1054 * So, size will always be 4096 <= size <= 4194304.
1055 * Since iommu_unmap() guarantees that both iova and size will be
1056 * aligned, we will always only be unmapping from a single dte here.
1057 */
1058 dte = rk_domain->dt[rk_iova_dte_index(iova)];
1059 /* Just return 0 if iova is unmapped */
1060 if (!rk_dte_is_pt_valid(dte)) {
1061 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
1062 return 0;
1063 }
1064
1065 pt_phys = rk_ops->pt_address(dte);
1066 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
1067 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
1068 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size,
1069 iommu);
1070
1071 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
1072
1073 /* Shootdown iotlb entries for iova range that was just unmapped */
1074 rk_iommu_zap_iova(rk_domain, iova, unmap_size);
1075
1076 return unmap_size;
1077 }
1078
rk_iommu_flush_tlb_all(struct iommu_domain * domain)1079 static void rk_iommu_flush_tlb_all(struct iommu_domain *domain)
1080 {
1081 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1082 struct list_head *pos;
1083 unsigned long flags;
1084 int i;
1085
1086 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1087 list_for_each(pos, &rk_domain->iommus) {
1088 struct rk_iommu *iommu;
1089 int ret;
1090
1091 iommu = list_entry(pos, struct rk_iommu, node);
1092
1093 ret = pm_runtime_get_if_in_use(iommu->dev);
1094 if (WARN_ON_ONCE(ret < 0))
1095 continue;
1096 if (ret) {
1097 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
1098 for (i = 0; i < iommu->num_mmu; i++)
1099 rk_iommu_write(iommu->bases[i], RK_MMU_COMMAND,
1100 RK_MMU_CMD_ZAP_CACHE);
1101 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
1102 pm_runtime_put(iommu->dev);
1103 }
1104 }
1105 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1106 }
1107
rk_iommu_from_dev(struct device * dev)1108 static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
1109 {
1110 struct rk_iommudata *data = dev_iommu_priv_get(dev);
1111
1112 return data ? data->iommu : NULL;
1113 }
1114
1115 /* Must be called with iommu powered on and attached */
rk_iommu_disable(struct rk_iommu * iommu)1116 static void rk_iommu_disable(struct rk_iommu *iommu)
1117 {
1118 int i;
1119
1120 /* Ignore error while disabling, just keep going */
1121 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
1122 rk_iommu_enable_stall(iommu);
1123 rk_iommu_disable_paging(iommu);
1124 for (i = 0; i < iommu->num_mmu; i++) {
1125 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
1126 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
1127 }
1128 rk_iommu_disable_stall(iommu);
1129 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
1130
1131 iommu->iommu_enabled = false;
1132 }
1133
rockchip_iommu_disable(struct device * dev)1134 int rockchip_iommu_disable(struct device *dev)
1135 {
1136 struct rk_iommu *iommu;
1137
1138 iommu = rk_iommu_from_dev(dev);
1139 if (!iommu)
1140 return -ENODEV;
1141
1142 rk_iommu_disable(iommu);
1143
1144 return 0;
1145 }
1146 EXPORT_SYMBOL(rockchip_iommu_disable);
1147
1148 /* Must be called with iommu powered on and attached */
rk_iommu_enable(struct rk_iommu * iommu)1149 static int rk_iommu_enable(struct rk_iommu *iommu)
1150 {
1151 struct iommu_domain *domain = iommu->domain;
1152 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1153 int ret, i;
1154 u32 auto_gate;
1155
1156 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
1157 if (ret)
1158 return ret;
1159
1160 ret = rk_iommu_enable_stall(iommu);
1161 if (ret)
1162 goto out_disable_clocks;
1163
1164 ret = rk_iommu_force_reset(iommu);
1165 if (ret)
1166 goto out_disable_stall;
1167
1168 for (i = 0; i < iommu->num_mmu; i++) {
1169 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
1170 rk_ops->dma_addr_dte(rk_domain->dt_dma));
1171 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
1172 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
1173
1174 /* Workaround for iommu blocked, BIT(31) default to 1 */
1175 auto_gate = rk_iommu_read(iommu->bases[i], RK_MMU_AUTO_GATING);
1176 auto_gate |= DISABLE_FETCH_DTE_TIME_LIMIT;
1177 rk_iommu_write(iommu->bases[i], RK_MMU_AUTO_GATING, auto_gate);
1178 }
1179
1180 ret = rk_iommu_enable_paging(iommu);
1181
1182 out_disable_stall:
1183 rk_iommu_disable_stall(iommu);
1184 out_disable_clocks:
1185 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
1186
1187 if (!ret)
1188 iommu->iommu_enabled = true;
1189
1190 return ret;
1191 }
1192
rockchip_iommu_enable(struct device * dev)1193 int rockchip_iommu_enable(struct device *dev)
1194 {
1195 struct rk_iommu *iommu;
1196
1197 iommu = rk_iommu_from_dev(dev);
1198 if (!iommu)
1199 return -ENODEV;
1200
1201 return rk_iommu_enable(iommu);
1202 }
1203 EXPORT_SYMBOL(rockchip_iommu_enable);
1204
rockchip_iommu_is_enabled(struct device * dev)1205 bool rockchip_iommu_is_enabled(struct device *dev)
1206 {
1207 struct rk_iommu *iommu;
1208
1209 iommu = rk_iommu_from_dev(dev);
1210 if (!iommu)
1211 return false;
1212
1213 return iommu->iommu_enabled;
1214 }
1215 EXPORT_SYMBOL(rockchip_iommu_is_enabled);
1216
rockchip_iommu_force_reset(struct device * dev)1217 int rockchip_iommu_force_reset(struct device *dev)
1218 {
1219 struct rk_iommu *iommu;
1220 int ret;
1221
1222 iommu = rk_iommu_from_dev(dev);
1223 if (!iommu)
1224 return -ENODEV;
1225
1226 ret = rk_iommu_enable_stall(iommu);
1227 if (ret)
1228 return ret;
1229
1230 ret = rk_iommu_force_reset(iommu);
1231
1232 rk_iommu_disable_stall(iommu);
1233
1234 return ret;
1235
1236 }
1237 EXPORT_SYMBOL(rockchip_iommu_force_reset);
1238
rk_iommu_detach_device(struct iommu_domain * domain,struct device * dev)1239 static void rk_iommu_detach_device(struct iommu_domain *domain,
1240 struct device *dev)
1241 {
1242 struct rk_iommu *iommu;
1243 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1244 unsigned long flags;
1245 int ret;
1246
1247 /* Allow 'virtual devices' (eg drm) to detach from domain */
1248 iommu = rk_iommu_from_dev(dev);
1249 if (!iommu)
1250 return;
1251
1252 dev_dbg(dev, "Detaching from iommu domain\n");
1253
1254 if (!iommu->domain)
1255 return;
1256
1257 iommu->domain = NULL;
1258
1259 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1260 list_del_init(&iommu->node);
1261 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1262
1263 ret = pm_runtime_get_if_in_use(iommu->dev);
1264 WARN_ON_ONCE(ret < 0);
1265 if (ret > 0) {
1266 rk_iommu_disable(iommu);
1267 pm_runtime_put(iommu->dev);
1268 }
1269 }
1270
rk_iommu_attach_device(struct iommu_domain * domain,struct device * dev)1271 static int rk_iommu_attach_device(struct iommu_domain *domain,
1272 struct device *dev)
1273 {
1274 struct rk_iommu *iommu;
1275 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1276 unsigned long flags;
1277 int ret;
1278
1279 /*
1280 * Allow 'virtual devices' (e.g., drm) to attach to domain.
1281 * Such a device does not belong to an iommu group.
1282 */
1283 iommu = rk_iommu_from_dev(dev);
1284 if (!iommu)
1285 return 0;
1286
1287 dev_dbg(dev, "Attaching to iommu domain\n");
1288
1289 if (iommu->domain)
1290 rk_iommu_detach_device(iommu->domain, dev);
1291
1292 iommu->domain = domain;
1293
1294 /* Attach NULL for disable iommu */
1295 if (!domain)
1296 return 0;
1297
1298 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1299 list_add_tail(&iommu->node, &rk_domain->iommus);
1300 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1301
1302 rk_domain->shootdown_entire = iommu->shootdown_entire;
1303 ret = pm_runtime_get_if_in_use(iommu->dev);
1304 if (!ret || WARN_ON_ONCE(ret < 0))
1305 return 0;
1306
1307 ret = rk_iommu_enable(iommu);
1308 if (ret)
1309 rk_iommu_detach_device(iommu->domain, dev);
1310
1311 pm_runtime_put(iommu->dev);
1312
1313 return ret;
1314 }
1315
rk_iommu_domain_alloc(unsigned type)1316 static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
1317 {
1318 struct rk_iommu_domain *rk_domain;
1319
1320 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
1321 return NULL;
1322
1323 if (!dma_dev)
1324 return NULL;
1325
1326 rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL);
1327 if (!rk_domain)
1328 return NULL;
1329
1330 if (type == IOMMU_DOMAIN_DMA &&
1331 iommu_get_dma_cookie(&rk_domain->domain))
1332 goto err_free_domain;
1333
1334 /*
1335 * rk32xx iommus use a 2 level pagetable.
1336 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
1337 * Allocate one 4 KiB page for each table.
1338 */
1339 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
1340 if (!rk_domain->dt)
1341 goto err_put_cookie;
1342
1343 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt,
1344 SPAGE_SIZE, DMA_TO_DEVICE);
1345 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) {
1346 dev_err(dma_dev, "DMA map error for DT\n");
1347 goto err_free_dt;
1348 }
1349
1350 spin_lock_init(&rk_domain->iommus_lock);
1351 spin_lock_init(&rk_domain->dt_lock);
1352 INIT_LIST_HEAD(&rk_domain->iommus);
1353
1354 rk_domain->domain.geometry.aperture_start = 0;
1355 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
1356 rk_domain->domain.geometry.force_aperture = true;
1357
1358 return &rk_domain->domain;
1359
1360 err_free_dt:
1361 free_page((unsigned long)rk_domain->dt);
1362 err_put_cookie:
1363 if (type == IOMMU_DOMAIN_DMA)
1364 iommu_put_dma_cookie(&rk_domain->domain);
1365 err_free_domain:
1366 kfree(rk_domain);
1367
1368 return NULL;
1369 }
1370
rk_iommu_domain_free(struct iommu_domain * domain)1371 static void rk_iommu_domain_free(struct iommu_domain *domain)
1372 {
1373 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1374 int i;
1375
1376 WARN_ON(!list_empty(&rk_domain->iommus));
1377
1378 for (i = 0; i < NUM_DT_ENTRIES; i++) {
1379 u32 dte = rk_domain->dt[i];
1380 if (rk_dte_is_pt_valid(dte)) {
1381 phys_addr_t pt_phys = rk_ops->pt_address(dte);
1382 u32 *page_table = phys_to_virt(pt_phys);
1383 dma_unmap_single(dma_dev, pt_phys,
1384 SPAGE_SIZE, DMA_TO_DEVICE);
1385 free_page((unsigned long)page_table);
1386 }
1387 }
1388
1389 dma_unmap_single(dma_dev, rk_domain->dt_dma,
1390 SPAGE_SIZE, DMA_TO_DEVICE);
1391 free_page((unsigned long)rk_domain->dt);
1392
1393 kfree(rk_domain);
1394 }
1395
rk_iommu_probe_device(struct device * dev)1396 static struct iommu_device *rk_iommu_probe_device(struct device *dev)
1397 {
1398 struct rk_iommudata *data;
1399 struct rk_iommu *iommu;
1400
1401 data = dev_iommu_priv_get(dev);
1402 if (!data)
1403 return ERR_PTR(-ENODEV);
1404
1405 iommu = rk_iommu_from_dev(dev);
1406
1407 data->link = device_link_add(dev, iommu->dev,
1408 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1409
1410 data->defer_attach = false;
1411
1412 /* set max segment size for dev, needed for single chunk map */
1413 if (!dev->dma_parms)
1414 dev->dma_parms = kzalloc(sizeof(*dev->dma_parms), GFP_KERNEL);
1415 if (!dev->dma_parms)
1416 return ERR_PTR(-ENOMEM);
1417
1418 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
1419
1420 return &iommu->iommu;
1421 }
1422
rk_iommu_release_device(struct device * dev)1423 static void rk_iommu_release_device(struct device *dev)
1424 {
1425 struct rk_iommudata *data = dev_iommu_priv_get(dev);
1426
1427 device_link_del(data->link);
1428 }
1429
rk_iommu_device_group(struct device * dev)1430 static struct iommu_group *rk_iommu_device_group(struct device *dev)
1431 {
1432 struct rk_iommu *iommu;
1433
1434 iommu = rk_iommu_from_dev(dev);
1435
1436 return iommu_group_ref_get(iommu->group);
1437 }
1438
rk_iommu_is_attach_deferred(struct iommu_domain * domain,struct device * dev)1439 static bool rk_iommu_is_attach_deferred(struct iommu_domain *domain,
1440 struct device *dev)
1441 {
1442 struct rk_iommudata *data = dev_iommu_priv_get(dev);
1443
1444 return data->defer_attach;
1445 }
1446
rk_iommu_of_xlate(struct device * dev,struct of_phandle_args * args)1447 static int rk_iommu_of_xlate(struct device *dev,
1448 struct of_phandle_args *args)
1449 {
1450 struct platform_device *iommu_dev;
1451 struct rk_iommudata *data;
1452
1453 data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL);
1454 if (!data)
1455 return -ENOMEM;
1456
1457 iommu_dev = of_find_device_by_node(args->np);
1458
1459 data->iommu = platform_get_drvdata(iommu_dev);
1460
1461 if (strstr(dev_name(dev), "vop"))
1462 data->defer_attach = true;
1463
1464 dev_iommu_priv_set(dev, data);
1465
1466 platform_device_put(iommu_dev);
1467
1468 return 0;
1469 }
1470
rockchip_iommu_mask_irq(struct device * dev)1471 void rockchip_iommu_mask_irq(struct device *dev)
1472 {
1473 struct rk_iommu *iommu = rk_iommu_from_dev(dev);
1474 int i;
1475
1476 if (!iommu)
1477 return;
1478
1479 for (i = 0; i < iommu->num_mmu; i++)
1480 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
1481 }
1482 EXPORT_SYMBOL(rockchip_iommu_mask_irq);
1483
rockchip_iommu_unmask_irq(struct device * dev)1484 void rockchip_iommu_unmask_irq(struct device *dev)
1485 {
1486 struct rk_iommu *iommu = rk_iommu_from_dev(dev);
1487 int i;
1488
1489 if (!iommu)
1490 return;
1491
1492 for (i = 0; i < iommu->num_mmu; i++) {
1493 /* Need to zap tlb in case of mapping during pagefault */
1494 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
1495 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
1496 /* Leave iommu in pagefault state until mapping finished */
1497 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
1498 }
1499 }
1500 EXPORT_SYMBOL(rockchip_iommu_unmask_irq);
1501
1502 static const struct iommu_ops rk_iommu_ops = {
1503 .domain_alloc = rk_iommu_domain_alloc,
1504 .domain_free = rk_iommu_domain_free,
1505 .attach_dev = rk_iommu_attach_device,
1506 .detach_dev = rk_iommu_detach_device,
1507 .map = rk_iommu_map,
1508 .unmap = rk_iommu_unmap,
1509 .flush_iotlb_all = rk_iommu_flush_tlb_all,
1510 .probe_device = rk_iommu_probe_device,
1511 .release_device = rk_iommu_release_device,
1512 .iova_to_phys = rk_iommu_iova_to_phys,
1513 .is_attach_deferred = rk_iommu_is_attach_deferred,
1514 .device_group = rk_iommu_device_group,
1515 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1516 .of_xlate = rk_iommu_of_xlate,
1517 };
1518
rk_iommu_probe(struct platform_device * pdev)1519 static int rk_iommu_probe(struct platform_device *pdev)
1520 {
1521 struct device *dev = &pdev->dev;
1522 struct rk_iommu *iommu;
1523 struct resource *res;
1524 const struct rk_iommu_ops *ops;
1525 int num_res = pdev->num_resources;
1526 int err, i;
1527
1528 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1529 if (!iommu)
1530 return -ENOMEM;
1531
1532 platform_set_drvdata(pdev, iommu);
1533 iommu->dev = dev;
1534 iommu->num_mmu = 0;
1535
1536 ops = of_device_get_match_data(dev);
1537 if (!rk_ops)
1538 rk_ops = ops;
1539
1540 /*
1541 * That should not happen unless different versions of the
1542 * hardware block are embedded the same SoC
1543 */
1544 if (WARN_ON(rk_ops != ops))
1545 return -EINVAL;
1546
1547 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases),
1548 GFP_KERNEL);
1549 if (!iommu->bases)
1550 return -ENOMEM;
1551
1552 for (i = 0; i < num_res; i++) {
1553 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1554 if (!res)
1555 continue;
1556 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1557 if (IS_ERR(iommu->bases[i]))
1558 continue;
1559 iommu->num_mmu++;
1560 }
1561 if (iommu->num_mmu == 0)
1562 return PTR_ERR(iommu->bases[0]);
1563
1564 iommu->num_irq = platform_irq_count(pdev);
1565 if (iommu->num_irq < 0)
1566 return iommu->num_irq;
1567
1568 iommu->reset_disabled = device_property_read_bool(dev,
1569 "rockchip,disable-mmu-reset");
1570 iommu->skip_read = device_property_read_bool(dev,
1571 "rockchip,skip-mmu-read");
1572 iommu->dlr_disable = device_property_read_bool(dev,
1573 "rockchip,disable-device-link-resume");
1574 iommu->shootdown_entire = device_property_read_bool(dev,
1575 "rockchip,shootdown-entire");
1576 iommu->master_handle_irq = device_property_read_bool(dev,
1577 "rockchip,master-handle-irq");
1578 if (of_machine_is_compatible("rockchip,rv1126") ||
1579 of_machine_is_compatible("rockchip,rv1109"))
1580 iommu->cmd_retry = device_property_read_bool(dev,
1581 "rockchip,enable-cmd-retry");
1582
1583 iommu->need_res_map = device_property_read_bool(dev,
1584 "rockchip,reserve-map");
1585
1586 /*
1587 * iommu clocks should be present for all new devices and devicetrees
1588 * but there are older devicetrees without clocks out in the wild.
1589 * So clocks as optional for the time being.
1590 */
1591 err = devm_clk_bulk_get_all(dev, &iommu->clocks);
1592 if (err == -ENOENT)
1593 iommu->num_clocks = 0;
1594 else if (err < 0)
1595 return err;
1596 else
1597 iommu->num_clocks = err;
1598
1599 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
1600 if (err)
1601 return err;
1602
1603 iommu->group = iommu_group_alloc();
1604 if (IS_ERR(iommu->group)) {
1605 err = PTR_ERR(iommu->group);
1606 goto err_unprepare_clocks;
1607 }
1608
1609 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
1610 if (err)
1611 goto err_put_group;
1612
1613 iommu_device_set_ops(&iommu->iommu, &rk_iommu_ops);
1614
1615 iommu_device_set_fwnode(&iommu->iommu, &dev->of_node->fwnode);
1616
1617 err = iommu_device_register(&iommu->iommu);
1618 if (err)
1619 goto err_remove_sysfs;
1620
1621 /*
1622 * Use the first registered IOMMU device for domain to use with DMA
1623 * API, since a domain might not physically correspond to a single
1624 * IOMMU device..
1625 */
1626 if (!dma_dev)
1627 dma_dev = &pdev->dev;
1628
1629 bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1630
1631 pm_runtime_enable(dev);
1632
1633 if (iommu->skip_read)
1634 goto skip_request_irq;
1635
1636 for (i = 0; i < iommu->num_irq; i++) {
1637 int irq = platform_get_irq(pdev, i);
1638
1639 if (irq < 0)
1640 return irq;
1641
1642 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq,
1643 IRQF_SHARED, dev_name(dev), iommu);
1644 if (err) {
1645 pm_runtime_disable(dev);
1646 goto err_remove_sysfs;
1647 }
1648 }
1649
1650 skip_request_irq:
1651 if (!res_page && iommu->need_res_map) {
1652 res_page = __pa_symbol(reserve_range);
1653
1654 pr_info("%s,%d, res_page = 0x%pa\n", __func__, __LINE__, &res_page);
1655 }
1656
1657 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask);
1658
1659 return 0;
1660 err_remove_sysfs:
1661 iommu_device_sysfs_remove(&iommu->iommu);
1662 err_put_group:
1663 iommu_group_put(iommu->group);
1664 err_unprepare_clocks:
1665 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
1666 return err;
1667 }
1668
rk_iommu_shutdown(struct platform_device * pdev)1669 static void rk_iommu_shutdown(struct platform_device *pdev)
1670 {
1671 struct rk_iommu *iommu = platform_get_drvdata(pdev);
1672 int i;
1673
1674 if (iommu->skip_read)
1675 goto skip_free_irq;
1676
1677 for (i = 0; i < iommu->num_irq; i++) {
1678 int irq = platform_get_irq(pdev, i);
1679
1680 devm_free_irq(iommu->dev, irq, iommu);
1681 }
1682
1683 skip_free_irq:
1684 if (!iommu->dlr_disable)
1685 pm_runtime_force_suspend(&pdev->dev);
1686 }
1687
rk_iommu_suspend(struct device * dev)1688 static int __maybe_unused rk_iommu_suspend(struct device *dev)
1689 {
1690 struct rk_iommu *iommu = dev_get_drvdata(dev);
1691
1692 if (!iommu->domain)
1693 return 0;
1694
1695 if (iommu->dlr_disable)
1696 return 0;
1697
1698 rk_iommu_disable(iommu);
1699 return 0;
1700 }
1701
rk_iommu_resume(struct device * dev)1702 static int __maybe_unused rk_iommu_resume(struct device *dev)
1703 {
1704 struct rk_iommu *iommu = dev_get_drvdata(dev);
1705
1706 if (!iommu->domain)
1707 return 0;
1708
1709 if (iommu->dlr_disable)
1710 return 0;
1711
1712 return rk_iommu_enable(iommu);
1713 }
1714
1715 static const struct dev_pm_ops rk_iommu_pm_ops = {
1716 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL)
1717 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1718 pm_runtime_force_resume)
1719 };
1720
1721 static struct rk_iommu_ops iommu_data_ops_v1 = {
1722 .pt_address = &rk_dte_pt_address,
1723 .mk_dtentries = &rk_mk_dte,
1724 .mk_ptentries = &rk_mk_pte,
1725 .dte_addr_phys = &rk_dte_addr_phys,
1726 .dma_addr_dte = &rk_dma_addr_dte,
1727 .dma_bit_mask = DMA_BIT_MASK(32),
1728 };
1729
1730 static struct rk_iommu_ops iommu_data_ops_v2 = {
1731 .pt_address = &rk_dte_pt_address_v2,
1732 .mk_dtentries = &rk_mk_dte_v2,
1733 .mk_ptentries = &rk_mk_pte_v2,
1734 .dte_addr_phys = &rk_dte_addr_phys_v2,
1735 .dma_addr_dte = &rk_dma_addr_dte_v2,
1736 .dma_bit_mask = DMA_BIT_MASK(40),
1737 };
1738
1739 static const struct of_device_id rk_iommu_dt_ids[] = {
1740 { .compatible = "rockchip,iommu",
1741 .data = &iommu_data_ops_v1,
1742 },
1743 { .compatible = "rockchip,iommu-v2",
1744 .data = &iommu_data_ops_v2,
1745 },
1746 { .compatible = "rockchip,rk3568-iommu",
1747 .data = &iommu_data_ops_v2,
1748 },
1749 { /* sentinel */ }
1750 };
1751
1752 static struct platform_driver rk_iommu_driver = {
1753 .probe = rk_iommu_probe,
1754 .shutdown = rk_iommu_shutdown,
1755 .driver = {
1756 .name = "rk_iommu",
1757 .of_match_table = rk_iommu_dt_ids,
1758 .pm = &rk_iommu_pm_ops,
1759 .suppress_bind_attrs = true,
1760 },
1761 };
1762
rk_iommu_init(void)1763 static int __init rk_iommu_init(void)
1764 {
1765 return platform_driver_register(&rk_iommu_driver);
1766 }
1767 subsys_initcall(rk_iommu_init);
1768
1769 MODULE_DESCRIPTION("IOMMU API for Rockchip");
1770 MODULE_AUTHOR("Simon Xue <xxm@rock-chips.com> and Daniel Kurtz <djkurtz@chromium.org>");
1771 MODULE_ALIAS("platform:rockchip-iommu");
1772 MODULE_LICENSE("GPL v2");
1773