1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2015-2016 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Honghui Zhang <honghui.zhang@mediatek.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef _MTK_IOMMU_H_
8*4882a593Smuzhiyun #define _MTK_IOMMU_H_
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/component.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/io-pgtable.h>
15*4882a593Smuzhiyun #include <linux/iommu.h>
16*4882a593Smuzhiyun #include <linux/list.h>
17*4882a593Smuzhiyun #include <linux/spinlock.h>
18*4882a593Smuzhiyun #include <linux/dma-mapping.h>
19*4882a593Smuzhiyun #include <soc/mediatek/smi.h>
20*4882a593Smuzhiyun #include <dt-bindings/memory/mtk-memory-port.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define MTK_LARB_COM_MAX 8
23*4882a593Smuzhiyun #define MTK_LARB_SUBCOM_MAX 4
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define MTK_IOMMU_GROUP_MAX 8
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct mtk_iommu_suspend_reg {
28*4882a593Smuzhiyun union {
29*4882a593Smuzhiyun u32 standard_axi_mode;/* v1 */
30*4882a593Smuzhiyun u32 misc_ctrl;/* v2 */
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun u32 dcm_dis;
33*4882a593Smuzhiyun u32 ctrl_reg;
34*4882a593Smuzhiyun u32 int_control0;
35*4882a593Smuzhiyun u32 int_main_control;
36*4882a593Smuzhiyun u32 ivrp_paddr;
37*4882a593Smuzhiyun u32 vld_pa_rng;
38*4882a593Smuzhiyun u32 wr_len_ctrl;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun enum mtk_iommu_plat {
42*4882a593Smuzhiyun M4U_MT2701,
43*4882a593Smuzhiyun M4U_MT2712,
44*4882a593Smuzhiyun M4U_MT6779,
45*4882a593Smuzhiyun M4U_MT8167,
46*4882a593Smuzhiyun M4U_MT8173,
47*4882a593Smuzhiyun M4U_MT8183,
48*4882a593Smuzhiyun M4U_MT8192,
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun struct mtk_iommu_iova_region;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct mtk_iommu_plat_data {
54*4882a593Smuzhiyun enum mtk_iommu_plat m4u_plat;
55*4882a593Smuzhiyun u32 flags;
56*4882a593Smuzhiyun u32 inv_sel_reg;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun unsigned int iova_region_nr;
59*4882a593Smuzhiyun const struct mtk_iommu_iova_region *iova_region;
60*4882a593Smuzhiyun unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct mtk_iommu_domain;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct mtk_iommu_data {
66*4882a593Smuzhiyun void __iomem *base;
67*4882a593Smuzhiyun int irq;
68*4882a593Smuzhiyun struct device *dev;
69*4882a593Smuzhiyun struct clk *bclk;
70*4882a593Smuzhiyun phys_addr_t protect_base; /* protect memory base */
71*4882a593Smuzhiyun struct mtk_iommu_suspend_reg reg;
72*4882a593Smuzhiyun struct mtk_iommu_domain *m4u_dom;
73*4882a593Smuzhiyun struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX];
74*4882a593Smuzhiyun bool enable_4GB;
75*4882a593Smuzhiyun spinlock_t tlb_lock; /* lock for tlb range flush */
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct iommu_device iommu;
78*4882a593Smuzhiyun const struct mtk_iommu_plat_data *plat_data;
79*4882a593Smuzhiyun struct device *smicomm_dev;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun struct mutex mutex; /* Protect m4u_group/m4u_dom above */
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun struct list_head list;
86*4882a593Smuzhiyun struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
compare_of(struct device * dev,void * data)89*4882a593Smuzhiyun static inline int compare_of(struct device *dev, void *data)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun return dev->of_node == data;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
release_of(struct device * dev,void * data)94*4882a593Smuzhiyun static inline void release_of(struct device *dev, void *data)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun of_node_put(data);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
mtk_iommu_bind(struct device * dev)99*4882a593Smuzhiyun static inline int mtk_iommu_bind(struct device *dev)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct mtk_iommu_data *data = dev_get_drvdata(dev);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return component_bind_all(dev, &data->larb_imu);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
mtk_iommu_unbind(struct device * dev)106*4882a593Smuzhiyun static inline void mtk_iommu_unbind(struct device *dev)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun struct mtk_iommu_data *data = dev_get_drvdata(dev);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun component_unbind_all(dev, &data->larb_imu);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #endif
114