1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun #ifndef IO_PGTABLE_ARM_H_ 3*4882a593Smuzhiyun #define IO_PGTABLE_ARM_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define ARM_LPAE_TCR_TG0_4K 0 6*4882a593Smuzhiyun #define ARM_LPAE_TCR_TG0_64K 1 7*4882a593Smuzhiyun #define ARM_LPAE_TCR_TG0_16K 2 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define ARM_LPAE_TCR_TG1_16K 1 10*4882a593Smuzhiyun #define ARM_LPAE_TCR_TG1_4K 2 11*4882a593Smuzhiyun #define ARM_LPAE_TCR_TG1_64K 3 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define ARM_LPAE_TCR_SH_NS 0 14*4882a593Smuzhiyun #define ARM_LPAE_TCR_SH_OS 2 15*4882a593Smuzhiyun #define ARM_LPAE_TCR_SH_IS 3 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define ARM_LPAE_TCR_RGN_NC 0 18*4882a593Smuzhiyun #define ARM_LPAE_TCR_RGN_WBWA 1 19*4882a593Smuzhiyun #define ARM_LPAE_TCR_RGN_WT 2 20*4882a593Smuzhiyun #define ARM_LPAE_TCR_RGN_WB 3 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL 23*4882a593Smuzhiyun #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL 24*4882a593Smuzhiyun #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL 25*4882a593Smuzhiyun #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL 26*4882a593Smuzhiyun #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL 27*4882a593Smuzhiyun #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL 28*4882a593Smuzhiyun #define ARM_LPAE_TCR_PS_52_BIT 0x6ULL 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif /* IO_PGTABLE_ARM_H_ */ 31