1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
4*4882a593Smuzhiyun * Author: Joerg Roedel <jroedel@suse.de>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef AMD_IOMMU_H
8*4882a593Smuzhiyun #define AMD_IOMMU_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/iommu.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "amd_iommu_types.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun extern int amd_iommu_get_num_iommus(void);
15*4882a593Smuzhiyun extern int amd_iommu_init_dma_ops(void);
16*4882a593Smuzhiyun extern int amd_iommu_init_passthrough(void);
17*4882a593Smuzhiyun extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
18*4882a593Smuzhiyun extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
19*4882a593Smuzhiyun extern void amd_iommu_apply_erratum_63(u16 devid);
20*4882a593Smuzhiyun extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
21*4882a593Smuzhiyun extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
22*4882a593Smuzhiyun extern int amd_iommu_init_devices(void);
23*4882a593Smuzhiyun extern void amd_iommu_uninit_devices(void);
24*4882a593Smuzhiyun extern void amd_iommu_init_notifier(void);
25*4882a593Smuzhiyun extern int amd_iommu_init_api(void);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #ifdef CONFIG_AMD_IOMMU_DEBUGFS
28*4882a593Smuzhiyun void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
29*4882a593Smuzhiyun #else
amd_iommu_debugfs_setup(struct amd_iommu * iommu)30*4882a593Smuzhiyun static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
31*4882a593Smuzhiyun #endif
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Needed for interrupt remapping */
34*4882a593Smuzhiyun extern int amd_iommu_prepare(void);
35*4882a593Smuzhiyun extern int amd_iommu_enable(void);
36*4882a593Smuzhiyun extern void amd_iommu_disable(void);
37*4882a593Smuzhiyun extern int amd_iommu_reenable(int);
38*4882a593Smuzhiyun extern int amd_iommu_enable_faulting(void);
39*4882a593Smuzhiyun extern int amd_iommu_guest_ir;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* IOMMUv2 specific functions */
42*4882a593Smuzhiyun struct iommu_domain;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun extern bool amd_iommu_v2_supported(void);
45*4882a593Smuzhiyun extern struct amd_iommu *get_amd_iommu(unsigned int idx);
46*4882a593Smuzhiyun extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
47*4882a593Smuzhiyun extern bool amd_iommu_pc_supported(void);
48*4882a593Smuzhiyun extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
49*4882a593Smuzhiyun extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
50*4882a593Smuzhiyun u8 fxn, u64 *value);
51*4882a593Smuzhiyun extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
52*4882a593Smuzhiyun u8 fxn, u64 *value);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
55*4882a593Smuzhiyun extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
56*4882a593Smuzhiyun extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
57*4882a593Smuzhiyun extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
58*4882a593Smuzhiyun extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
59*4882a593Smuzhiyun u64 address);
60*4882a593Smuzhiyun extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
61*4882a593Smuzhiyun extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
62*4882a593Smuzhiyun unsigned long cr3);
63*4882a593Smuzhiyun extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
64*4882a593Smuzhiyun extern struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #ifdef CONFIG_IRQ_REMAP
67*4882a593Smuzhiyun extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
68*4882a593Smuzhiyun #else
amd_iommu_create_irq_domain(struct amd_iommu * iommu)69*4882a593Smuzhiyun static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define PPR_SUCCESS 0x0
76*4882a593Smuzhiyun #define PPR_INVALID 0x1
77*4882a593Smuzhiyun #define PPR_FAILURE 0xf
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
80*4882a593Smuzhiyun int status, int tag);
81*4882a593Smuzhiyun
is_rd890_iommu(struct pci_dev * pdev)82*4882a593Smuzhiyun static inline bool is_rd890_iommu(struct pci_dev *pdev)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
85*4882a593Smuzhiyun (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
iommu_feature(struct amd_iommu * iommu,u64 mask)88*4882a593Smuzhiyun static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun return !!(iommu->features & mask);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
iommu_virt_to_phys(void * vaddr)93*4882a593Smuzhiyun static inline u64 iommu_virt_to_phys(void *vaddr)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun return (u64)__sme_set(virt_to_phys(vaddr));
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
iommu_phys_to_virt(unsigned long paddr)98*4882a593Smuzhiyun static inline void *iommu_phys_to_virt(unsigned long paddr)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun return phys_to_virt(__sme_clr(paddr));
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun extern bool translation_pre_enabled(struct amd_iommu *iommu);
104*4882a593Smuzhiyun extern bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
105*4882a593Smuzhiyun struct device *dev);
106*4882a593Smuzhiyun extern int __init add_special_device(u8 type, u8 id, u16 *devid,
107*4882a593Smuzhiyun bool cmd_line);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #ifdef CONFIG_DMI
110*4882a593Smuzhiyun void amd_iommu_apply_ivrs_quirks(void);
111*4882a593Smuzhiyun #else
amd_iommu_apply_ivrs_quirks(void)112*4882a593Smuzhiyun static inline void amd_iommu_apply_ivrs_quirks(void) { }
113*4882a593Smuzhiyun #endif
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #endif
116