1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Interconnect framework driver for i.MX8MM SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2019, BayLibre
6*4882a593Smuzhiyun * Copyright (c) 2019-2020, NXP
7*4882a593Smuzhiyun * Author: Alexandre Bailon <abailon@baylibre.com>
8*4882a593Smuzhiyun * Author: Leonard Crestez <leonard.crestez@nxp.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <dt-bindings/interconnect/imx8mm.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "imx.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static const struct imx_icc_node_adj_desc imx8mm_dram_adj = {
18*4882a593Smuzhiyun .bw_mul = 1,
19*4882a593Smuzhiyun .bw_div = 16,
20*4882a593Smuzhiyun .phandle_name = "fsl,ddrc",
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static const struct imx_icc_node_adj_desc imx8mm_noc_adj = {
24*4882a593Smuzhiyun .bw_mul = 1,
25*4882a593Smuzhiyun .bw_div = 16,
26*4882a593Smuzhiyun .main_noc = true,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Describe bus masters, slaves and connections between them
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * This is a simplified subset of the bus diagram, there are several other
33*4882a593Smuzhiyun * PL301 nics which are skipped/merged into PL301_MAIN
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun static struct imx_icc_node_desc nodes[] = {
36*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj,
37*4882a593Smuzhiyun IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN),
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj),
40*4882a593Smuzhiyun DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL),
41*4882a593Smuzhiyun DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC),
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* VPUMIX */
44*4882a593Smuzhiyun DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO),
45*4882a593Smuzhiyun DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO),
46*4882a593Smuzhiyun DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO),
47*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC),
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* GPUMIX */
50*4882a593Smuzhiyun DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU),
51*4882a593Smuzhiyun DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU),
52*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC),
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* DISPLAYMIX */
55*4882a593Smuzhiyun DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI),
56*4882a593Smuzhiyun DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI),
57*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC),
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* HSIO */
60*4882a593Smuzhiyun DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO),
61*4882a593Smuzhiyun DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO),
62*4882a593Smuzhiyun DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO),
63*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC),
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Audio */
66*4882a593Smuzhiyun DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO),
67*4882a593Smuzhiyun DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO),
68*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN),
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Ethernet */
71*4882a593Smuzhiyun DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET),
72*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN),
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Other */
75*4882a593Smuzhiyun DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN),
76*4882a593Smuzhiyun DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN),
77*4882a593Smuzhiyun DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN),
78*4882a593Smuzhiyun DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN),
79*4882a593Smuzhiyun DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN),
80*4882a593Smuzhiyun DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL,
81*4882a593Smuzhiyun IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM),
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
imx8mm_icc_probe(struct platform_device * pdev)84*4882a593Smuzhiyun static int imx8mm_icc_probe(struct platform_device *pdev)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes));
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
imx8mm_icc_remove(struct platform_device * pdev)89*4882a593Smuzhiyun static int imx8mm_icc_remove(struct platform_device *pdev)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun return imx_icc_unregister(pdev);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static struct platform_driver imx8mm_icc_driver = {
95*4882a593Smuzhiyun .probe = imx8mm_icc_probe,
96*4882a593Smuzhiyun .remove = imx8mm_icc_remove,
97*4882a593Smuzhiyun .driver = {
98*4882a593Smuzhiyun .name = "imx8mm-interconnect",
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun module_platform_driver(imx8mm_icc_driver);
103*4882a593Smuzhiyun MODULE_AUTHOR("Alexandre Bailon <abailon@baylibre.com>");
104*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
105*4882a593Smuzhiyun MODULE_ALIAS("platform:imx8mm-interconnect");
106