1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Azoteq IQS550/572/525 Trackpad/Touchscreen Controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018
6*4882a593Smuzhiyun * Author: Jeff LaBundy <jeff@labundy.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * These devices require firmware exported from a PC-based configuration tool
9*4882a593Smuzhiyun * made available by the vendor. Firmware files may be pushed to the device's
10*4882a593Smuzhiyun * nonvolatile memory by writing the filename to the 'fw_file' sysfs control.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Link to PC-based configuration tool and data sheet: http://www.azoteq.com/
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/device.h>
17*4882a593Smuzhiyun #include <linux/err.h>
18*4882a593Smuzhiyun #include <linux/firmware.h>
19*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
20*4882a593Smuzhiyun #include <linux/i2c.h>
21*4882a593Smuzhiyun #include <linux/input.h>
22*4882a593Smuzhiyun #include <linux/input/mt.h>
23*4882a593Smuzhiyun #include <linux/input/touchscreen.h>
24*4882a593Smuzhiyun #include <linux/interrupt.h>
25*4882a593Smuzhiyun #include <linux/kernel.h>
26*4882a593Smuzhiyun #include <linux/module.h>
27*4882a593Smuzhiyun #include <linux/of_device.h>
28*4882a593Smuzhiyun #include <linux/slab.h>
29*4882a593Smuzhiyun #include <asm/unaligned.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define IQS5XX_FW_FILE_LEN 64
32*4882a593Smuzhiyun #define IQS5XX_NUM_RETRIES 10
33*4882a593Smuzhiyun #define IQS5XX_NUM_POINTS 256
34*4882a593Smuzhiyun #define IQS5XX_NUM_CONTACTS 5
35*4882a593Smuzhiyun #define IQS5XX_WR_BYTES_MAX 2
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define IQS5XX_PROD_NUM_IQS550 40
38*4882a593Smuzhiyun #define IQS5XX_PROD_NUM_IQS572 58
39*4882a593Smuzhiyun #define IQS5XX_PROD_NUM_IQS525 52
40*4882a593Smuzhiyun #define IQS5XX_PROJ_NUM_A000 0
41*4882a593Smuzhiyun #define IQS5XX_PROJ_NUM_B000 15
42*4882a593Smuzhiyun #define IQS5XX_MAJOR_VER_MIN 2
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define IQS5XX_RESUME 0x00
45*4882a593Smuzhiyun #define IQS5XX_SUSPEND 0x01
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define IQS5XX_SW_INPUT_EVENT 0x10
48*4882a593Smuzhiyun #define IQS5XX_SETUP_COMPLETE 0x40
49*4882a593Smuzhiyun #define IQS5XX_EVENT_MODE 0x01
50*4882a593Smuzhiyun #define IQS5XX_TP_EVENT 0x04
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define IQS5XX_FLIP_X 0x01
53*4882a593Smuzhiyun #define IQS5XX_FLIP_Y 0x02
54*4882a593Smuzhiyun #define IQS5XX_SWITCH_XY_AXIS 0x04
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define IQS5XX_PROD_NUM 0x0000
57*4882a593Smuzhiyun #define IQS5XX_ABS_X 0x0016
58*4882a593Smuzhiyun #define IQS5XX_ABS_Y 0x0018
59*4882a593Smuzhiyun #define IQS5XX_SYS_CTRL0 0x0431
60*4882a593Smuzhiyun #define IQS5XX_SYS_CTRL1 0x0432
61*4882a593Smuzhiyun #define IQS5XX_SYS_CFG0 0x058E
62*4882a593Smuzhiyun #define IQS5XX_SYS_CFG1 0x058F
63*4882a593Smuzhiyun #define IQS5XX_TOTAL_RX 0x063D
64*4882a593Smuzhiyun #define IQS5XX_TOTAL_TX 0x063E
65*4882a593Smuzhiyun #define IQS5XX_XY_CFG0 0x0669
66*4882a593Smuzhiyun #define IQS5XX_X_RES 0x066E
67*4882a593Smuzhiyun #define IQS5XX_Y_RES 0x0670
68*4882a593Smuzhiyun #define IQS5XX_CHKSM 0x83C0
69*4882a593Smuzhiyun #define IQS5XX_APP 0x8400
70*4882a593Smuzhiyun #define IQS5XX_CSTM 0xBE00
71*4882a593Smuzhiyun #define IQS5XX_PMAP_END 0xBFFF
72*4882a593Smuzhiyun #define IQS5XX_END_COMM 0xEEEE
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define IQS5XX_CHKSM_LEN (IQS5XX_APP - IQS5XX_CHKSM)
75*4882a593Smuzhiyun #define IQS5XX_APP_LEN (IQS5XX_CSTM - IQS5XX_APP)
76*4882a593Smuzhiyun #define IQS5XX_CSTM_LEN (IQS5XX_PMAP_END + 1 - IQS5XX_CSTM)
77*4882a593Smuzhiyun #define IQS5XX_PMAP_LEN (IQS5XX_PMAP_END + 1 - IQS5XX_CHKSM)
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define IQS5XX_REC_HDR_LEN 4
80*4882a593Smuzhiyun #define IQS5XX_REC_LEN_MAX 255
81*4882a593Smuzhiyun #define IQS5XX_REC_TYPE_DATA 0x00
82*4882a593Smuzhiyun #define IQS5XX_REC_TYPE_EOF 0x01
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define IQS5XX_BL_ADDR_MASK 0x40
85*4882a593Smuzhiyun #define IQS5XX_BL_CMD_VER 0x00
86*4882a593Smuzhiyun #define IQS5XX_BL_CMD_READ 0x01
87*4882a593Smuzhiyun #define IQS5XX_BL_CMD_EXEC 0x02
88*4882a593Smuzhiyun #define IQS5XX_BL_CMD_CRC 0x03
89*4882a593Smuzhiyun #define IQS5XX_BL_BLK_LEN_MAX 64
90*4882a593Smuzhiyun #define IQS5XX_BL_ID 0x0200
91*4882a593Smuzhiyun #define IQS5XX_BL_STATUS_RESET 0x00
92*4882a593Smuzhiyun #define IQS5XX_BL_STATUS_AVAIL 0xA5
93*4882a593Smuzhiyun #define IQS5XX_BL_STATUS_NONE 0xEE
94*4882a593Smuzhiyun #define IQS5XX_BL_CRC_PASS 0x00
95*4882a593Smuzhiyun #define IQS5XX_BL_CRC_FAIL 0x01
96*4882a593Smuzhiyun #define IQS5XX_BL_ATTEMPTS 3
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun struct iqs5xx_private {
99*4882a593Smuzhiyun struct i2c_client *client;
100*4882a593Smuzhiyun struct input_dev *input;
101*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
102*4882a593Smuzhiyun struct mutex lock;
103*4882a593Smuzhiyun u8 bl_status;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun struct iqs5xx_dev_id_info {
107*4882a593Smuzhiyun __be16 prod_num;
108*4882a593Smuzhiyun __be16 proj_num;
109*4882a593Smuzhiyun u8 major_ver;
110*4882a593Smuzhiyun u8 minor_ver;
111*4882a593Smuzhiyun u8 bl_status;
112*4882a593Smuzhiyun } __packed;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun struct iqs5xx_ihex_rec {
115*4882a593Smuzhiyun char start;
116*4882a593Smuzhiyun char len[2];
117*4882a593Smuzhiyun char addr[4];
118*4882a593Smuzhiyun char type[2];
119*4882a593Smuzhiyun char data[2];
120*4882a593Smuzhiyun } __packed;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun struct iqs5xx_touch_data {
123*4882a593Smuzhiyun __be16 abs_x;
124*4882a593Smuzhiyun __be16 abs_y;
125*4882a593Smuzhiyun __be16 strength;
126*4882a593Smuzhiyun u8 area;
127*4882a593Smuzhiyun } __packed;
128*4882a593Smuzhiyun
iqs5xx_read_burst(struct i2c_client * client,u16 reg,void * val,u16 len)129*4882a593Smuzhiyun static int iqs5xx_read_burst(struct i2c_client *client,
130*4882a593Smuzhiyun u16 reg, void *val, u16 len)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun __be16 reg_buf = cpu_to_be16(reg);
133*4882a593Smuzhiyun int ret, i;
134*4882a593Smuzhiyun struct i2c_msg msg[] = {
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun .addr = client->addr,
137*4882a593Smuzhiyun .flags = 0,
138*4882a593Smuzhiyun .len = sizeof(reg_buf),
139*4882a593Smuzhiyun .buf = (u8 *)®_buf,
140*4882a593Smuzhiyun },
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun .addr = client->addr,
143*4882a593Smuzhiyun .flags = I2C_M_RD,
144*4882a593Smuzhiyun .len = len,
145*4882a593Smuzhiyun .buf = (u8 *)val,
146*4882a593Smuzhiyun },
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /*
150*4882a593Smuzhiyun * The first addressing attempt outside of a communication window fails
151*4882a593Smuzhiyun * and must be retried, after which the device clock stretches until it
152*4882a593Smuzhiyun * is available.
153*4882a593Smuzhiyun */
154*4882a593Smuzhiyun for (i = 0; i < IQS5XX_NUM_RETRIES; i++) {
155*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
156*4882a593Smuzhiyun if (ret == ARRAY_SIZE(msg))
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun usleep_range(200, 300);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun if (ret >= 0)
163*4882a593Smuzhiyun ret = -EIO;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun dev_err(&client->dev, "Failed to read from address 0x%04X: %d\n",
166*4882a593Smuzhiyun reg, ret);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return ret;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
iqs5xx_read_word(struct i2c_client * client,u16 reg,u16 * val)171*4882a593Smuzhiyun static int iqs5xx_read_word(struct i2c_client *client, u16 reg, u16 *val)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun __be16 val_buf;
174*4882a593Smuzhiyun int error;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun error = iqs5xx_read_burst(client, reg, &val_buf, sizeof(val_buf));
177*4882a593Smuzhiyun if (error)
178*4882a593Smuzhiyun return error;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun *val = be16_to_cpu(val_buf);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun return 0;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
iqs5xx_read_byte(struct i2c_client * client,u16 reg,u8 * val)185*4882a593Smuzhiyun static int iqs5xx_read_byte(struct i2c_client *client, u16 reg, u8 *val)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun return iqs5xx_read_burst(client, reg, val, sizeof(*val));
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
iqs5xx_write_burst(struct i2c_client * client,u16 reg,const void * val,u16 len)190*4882a593Smuzhiyun static int iqs5xx_write_burst(struct i2c_client *client,
191*4882a593Smuzhiyun u16 reg, const void *val, u16 len)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun int ret, i;
194*4882a593Smuzhiyun u16 mlen = sizeof(reg) + len;
195*4882a593Smuzhiyun u8 mbuf[sizeof(reg) + IQS5XX_WR_BYTES_MAX];
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun if (len > IQS5XX_WR_BYTES_MAX)
198*4882a593Smuzhiyun return -EINVAL;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun put_unaligned_be16(reg, mbuf);
201*4882a593Smuzhiyun memcpy(mbuf + sizeof(reg), val, len);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /*
204*4882a593Smuzhiyun * The first addressing attempt outside of a communication window fails
205*4882a593Smuzhiyun * and must be retried, after which the device clock stretches until it
206*4882a593Smuzhiyun * is available.
207*4882a593Smuzhiyun */
208*4882a593Smuzhiyun for (i = 0; i < IQS5XX_NUM_RETRIES; i++) {
209*4882a593Smuzhiyun ret = i2c_master_send(client, mbuf, mlen);
210*4882a593Smuzhiyun if (ret == mlen)
211*4882a593Smuzhiyun return 0;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun usleep_range(200, 300);
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun if (ret >= 0)
217*4882a593Smuzhiyun ret = -EIO;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun dev_err(&client->dev, "Failed to write to address 0x%04X: %d\n",
220*4882a593Smuzhiyun reg, ret);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun return ret;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
iqs5xx_write_word(struct i2c_client * client,u16 reg,u16 val)225*4882a593Smuzhiyun static int iqs5xx_write_word(struct i2c_client *client, u16 reg, u16 val)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun __be16 val_buf = cpu_to_be16(val);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun return iqs5xx_write_burst(client, reg, &val_buf, sizeof(val_buf));
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
iqs5xx_write_byte(struct i2c_client * client,u16 reg,u8 val)232*4882a593Smuzhiyun static int iqs5xx_write_byte(struct i2c_client *client, u16 reg, u8 val)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun return iqs5xx_write_burst(client, reg, &val, sizeof(val));
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
iqs5xx_reset(struct i2c_client * client)237*4882a593Smuzhiyun static void iqs5xx_reset(struct i2c_client *client)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = i2c_get_clientdata(client);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun gpiod_set_value_cansleep(iqs5xx->reset_gpio, 1);
242*4882a593Smuzhiyun usleep_range(200, 300);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun gpiod_set_value_cansleep(iqs5xx->reset_gpio, 0);
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
iqs5xx_bl_cmd(struct i2c_client * client,u8 bl_cmd,u16 bl_addr)247*4882a593Smuzhiyun static int iqs5xx_bl_cmd(struct i2c_client *client, u8 bl_cmd, u16 bl_addr)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun struct i2c_msg msg;
250*4882a593Smuzhiyun int ret;
251*4882a593Smuzhiyun u8 mbuf[sizeof(bl_cmd) + sizeof(bl_addr)];
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun msg.addr = client->addr ^ IQS5XX_BL_ADDR_MASK;
254*4882a593Smuzhiyun msg.flags = 0;
255*4882a593Smuzhiyun msg.len = sizeof(bl_cmd);
256*4882a593Smuzhiyun msg.buf = mbuf;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun *mbuf = bl_cmd;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun switch (bl_cmd) {
261*4882a593Smuzhiyun case IQS5XX_BL_CMD_VER:
262*4882a593Smuzhiyun case IQS5XX_BL_CMD_CRC:
263*4882a593Smuzhiyun case IQS5XX_BL_CMD_EXEC:
264*4882a593Smuzhiyun break;
265*4882a593Smuzhiyun case IQS5XX_BL_CMD_READ:
266*4882a593Smuzhiyun msg.len += sizeof(bl_addr);
267*4882a593Smuzhiyun put_unaligned_be16(bl_addr, mbuf + sizeof(bl_cmd));
268*4882a593Smuzhiyun break;
269*4882a593Smuzhiyun default:
270*4882a593Smuzhiyun return -EINVAL;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
274*4882a593Smuzhiyun if (ret != 1)
275*4882a593Smuzhiyun goto msg_fail;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun switch (bl_cmd) {
278*4882a593Smuzhiyun case IQS5XX_BL_CMD_VER:
279*4882a593Smuzhiyun msg.len = sizeof(u16);
280*4882a593Smuzhiyun break;
281*4882a593Smuzhiyun case IQS5XX_BL_CMD_CRC:
282*4882a593Smuzhiyun msg.len = sizeof(u8);
283*4882a593Smuzhiyun /*
284*4882a593Smuzhiyun * This delay saves the bus controller the trouble of having to
285*4882a593Smuzhiyun * tolerate a relatively long clock-stretching period while the
286*4882a593Smuzhiyun * CRC is calculated.
287*4882a593Smuzhiyun */
288*4882a593Smuzhiyun msleep(50);
289*4882a593Smuzhiyun break;
290*4882a593Smuzhiyun case IQS5XX_BL_CMD_EXEC:
291*4882a593Smuzhiyun usleep_range(10000, 10100);
292*4882a593Smuzhiyun fallthrough;
293*4882a593Smuzhiyun default:
294*4882a593Smuzhiyun return 0;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun msg.flags = I2C_M_RD;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
300*4882a593Smuzhiyun if (ret != 1)
301*4882a593Smuzhiyun goto msg_fail;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun if (bl_cmd == IQS5XX_BL_CMD_VER &&
304*4882a593Smuzhiyun get_unaligned_be16(mbuf) != IQS5XX_BL_ID) {
305*4882a593Smuzhiyun dev_err(&client->dev, "Unrecognized bootloader ID: 0x%04X\n",
306*4882a593Smuzhiyun get_unaligned_be16(mbuf));
307*4882a593Smuzhiyun return -EINVAL;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun if (bl_cmd == IQS5XX_BL_CMD_CRC && *mbuf != IQS5XX_BL_CRC_PASS) {
311*4882a593Smuzhiyun dev_err(&client->dev, "Bootloader CRC failed\n");
312*4882a593Smuzhiyun return -EIO;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun return 0;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun msg_fail:
318*4882a593Smuzhiyun if (ret >= 0)
319*4882a593Smuzhiyun ret = -EIO;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun if (bl_cmd != IQS5XX_BL_CMD_VER)
322*4882a593Smuzhiyun dev_err(&client->dev,
323*4882a593Smuzhiyun "Unsuccessful bootloader command 0x%02X: %d\n",
324*4882a593Smuzhiyun bl_cmd, ret);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun return ret;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
iqs5xx_bl_open(struct i2c_client * client)329*4882a593Smuzhiyun static int iqs5xx_bl_open(struct i2c_client *client)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun int error, i, j;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /*
334*4882a593Smuzhiyun * The device opens a bootloader polling window for 2 ms following the
335*4882a593Smuzhiyun * release of reset. If the host cannot establish communication during
336*4882a593Smuzhiyun * this time frame, it must cycle reset again.
337*4882a593Smuzhiyun */
338*4882a593Smuzhiyun for (i = 0; i < IQS5XX_BL_ATTEMPTS; i++) {
339*4882a593Smuzhiyun iqs5xx_reset(client);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun for (j = 0; j < IQS5XX_NUM_RETRIES; j++) {
342*4882a593Smuzhiyun error = iqs5xx_bl_cmd(client, IQS5XX_BL_CMD_VER, 0);
343*4882a593Smuzhiyun if (!error || error == -EINVAL)
344*4882a593Smuzhiyun return error;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun dev_err(&client->dev, "Failed to open bootloader: %d\n", error);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun return error;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
iqs5xx_bl_write(struct i2c_client * client,u16 bl_addr,u8 * pmap_data,u16 pmap_len)353*4882a593Smuzhiyun static int iqs5xx_bl_write(struct i2c_client *client,
354*4882a593Smuzhiyun u16 bl_addr, u8 *pmap_data, u16 pmap_len)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun struct i2c_msg msg;
357*4882a593Smuzhiyun int ret, i;
358*4882a593Smuzhiyun u8 mbuf[sizeof(bl_addr) + IQS5XX_BL_BLK_LEN_MAX];
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun if (pmap_len % IQS5XX_BL_BLK_LEN_MAX)
361*4882a593Smuzhiyun return -EINVAL;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun msg.addr = client->addr ^ IQS5XX_BL_ADDR_MASK;
364*4882a593Smuzhiyun msg.flags = 0;
365*4882a593Smuzhiyun msg.len = sizeof(mbuf);
366*4882a593Smuzhiyun msg.buf = mbuf;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun for (i = 0; i < pmap_len; i += IQS5XX_BL_BLK_LEN_MAX) {
369*4882a593Smuzhiyun put_unaligned_be16(bl_addr + i, mbuf);
370*4882a593Smuzhiyun memcpy(mbuf + sizeof(bl_addr), pmap_data + i,
371*4882a593Smuzhiyun sizeof(mbuf) - sizeof(bl_addr));
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
374*4882a593Smuzhiyun if (ret != 1)
375*4882a593Smuzhiyun goto msg_fail;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun usleep_range(10000, 10100);
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun return 0;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun msg_fail:
383*4882a593Smuzhiyun if (ret >= 0)
384*4882a593Smuzhiyun ret = -EIO;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun dev_err(&client->dev, "Failed to write block at address 0x%04X: %d\n",
387*4882a593Smuzhiyun bl_addr + i, ret);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun return ret;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
iqs5xx_bl_verify(struct i2c_client * client,u16 bl_addr,u8 * pmap_data,u16 pmap_len)392*4882a593Smuzhiyun static int iqs5xx_bl_verify(struct i2c_client *client,
393*4882a593Smuzhiyun u16 bl_addr, u8 *pmap_data, u16 pmap_len)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun struct i2c_msg msg;
396*4882a593Smuzhiyun int ret, i;
397*4882a593Smuzhiyun u8 bl_data[IQS5XX_BL_BLK_LEN_MAX];
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun if (pmap_len % IQS5XX_BL_BLK_LEN_MAX)
400*4882a593Smuzhiyun return -EINVAL;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun msg.addr = client->addr ^ IQS5XX_BL_ADDR_MASK;
403*4882a593Smuzhiyun msg.flags = I2C_M_RD;
404*4882a593Smuzhiyun msg.len = sizeof(bl_data);
405*4882a593Smuzhiyun msg.buf = bl_data;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun for (i = 0; i < pmap_len; i += IQS5XX_BL_BLK_LEN_MAX) {
408*4882a593Smuzhiyun ret = iqs5xx_bl_cmd(client, IQS5XX_BL_CMD_READ, bl_addr + i);
409*4882a593Smuzhiyun if (ret)
410*4882a593Smuzhiyun return ret;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
413*4882a593Smuzhiyun if (ret != 1)
414*4882a593Smuzhiyun goto msg_fail;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun if (memcmp(bl_data, pmap_data + i, sizeof(bl_data))) {
417*4882a593Smuzhiyun dev_err(&client->dev,
418*4882a593Smuzhiyun "Failed to verify block at address 0x%04X\n",
419*4882a593Smuzhiyun bl_addr + i);
420*4882a593Smuzhiyun return -EIO;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun return 0;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun msg_fail:
427*4882a593Smuzhiyun if (ret >= 0)
428*4882a593Smuzhiyun ret = -EIO;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun dev_err(&client->dev, "Failed to read block at address 0x%04X: %d\n",
431*4882a593Smuzhiyun bl_addr + i, ret);
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun return ret;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
iqs5xx_set_state(struct i2c_client * client,u8 state)436*4882a593Smuzhiyun static int iqs5xx_set_state(struct i2c_client *client, u8 state)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = i2c_get_clientdata(client);
439*4882a593Smuzhiyun int error1, error2;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun if (iqs5xx->bl_status == IQS5XX_BL_STATUS_RESET)
442*4882a593Smuzhiyun return 0;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun mutex_lock(&iqs5xx->lock);
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun /*
447*4882a593Smuzhiyun * Addressing the device outside of a communication window prompts it
448*4882a593Smuzhiyun * to assert the RDY output, so disable the interrupt line to prevent
449*4882a593Smuzhiyun * the handler from servicing a false interrupt.
450*4882a593Smuzhiyun */
451*4882a593Smuzhiyun disable_irq(client->irq);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun error1 = iqs5xx_write_byte(client, IQS5XX_SYS_CTRL1, state);
454*4882a593Smuzhiyun error2 = iqs5xx_write_byte(client, IQS5XX_END_COMM, 0);
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun usleep_range(50, 100);
457*4882a593Smuzhiyun enable_irq(client->irq);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun mutex_unlock(&iqs5xx->lock);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun if (error1)
462*4882a593Smuzhiyun return error1;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun return error2;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
iqs5xx_open(struct input_dev * input)467*4882a593Smuzhiyun static int iqs5xx_open(struct input_dev *input)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = input_get_drvdata(input);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun return iqs5xx_set_state(iqs5xx->client, IQS5XX_RESUME);
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
iqs5xx_close(struct input_dev * input)474*4882a593Smuzhiyun static void iqs5xx_close(struct input_dev *input)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = input_get_drvdata(input);
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun iqs5xx_set_state(iqs5xx->client, IQS5XX_SUSPEND);
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
iqs5xx_axis_init(struct i2c_client * client)481*4882a593Smuzhiyun static int iqs5xx_axis_init(struct i2c_client *client)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = i2c_get_clientdata(client);
484*4882a593Smuzhiyun struct touchscreen_properties prop;
485*4882a593Smuzhiyun struct input_dev *input;
486*4882a593Smuzhiyun int error;
487*4882a593Smuzhiyun u16 max_x, max_x_hw;
488*4882a593Smuzhiyun u16 max_y, max_y_hw;
489*4882a593Smuzhiyun u8 val;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun if (!iqs5xx->input) {
492*4882a593Smuzhiyun input = devm_input_allocate_device(&client->dev);
493*4882a593Smuzhiyun if (!input)
494*4882a593Smuzhiyun return -ENOMEM;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun input->name = client->name;
497*4882a593Smuzhiyun input->id.bustype = BUS_I2C;
498*4882a593Smuzhiyun input->open = iqs5xx_open;
499*4882a593Smuzhiyun input->close = iqs5xx_close;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun input_set_capability(input, EV_ABS, ABS_MT_POSITION_X);
502*4882a593Smuzhiyun input_set_capability(input, EV_ABS, ABS_MT_POSITION_Y);
503*4882a593Smuzhiyun input_set_capability(input, EV_ABS, ABS_MT_PRESSURE);
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun input_set_drvdata(input, iqs5xx);
506*4882a593Smuzhiyun iqs5xx->input = input;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun touchscreen_parse_properties(iqs5xx->input, true, &prop);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun error = iqs5xx_read_byte(client, IQS5XX_TOTAL_RX, &val);
512*4882a593Smuzhiyun if (error)
513*4882a593Smuzhiyun return error;
514*4882a593Smuzhiyun max_x_hw = (val - 1) * IQS5XX_NUM_POINTS;
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun error = iqs5xx_read_byte(client, IQS5XX_TOTAL_TX, &val);
517*4882a593Smuzhiyun if (error)
518*4882a593Smuzhiyun return error;
519*4882a593Smuzhiyun max_y_hw = (val - 1) * IQS5XX_NUM_POINTS;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun error = iqs5xx_read_byte(client, IQS5XX_XY_CFG0, &val);
522*4882a593Smuzhiyun if (error)
523*4882a593Smuzhiyun return error;
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun if (val & IQS5XX_SWITCH_XY_AXIS)
526*4882a593Smuzhiyun swap(max_x_hw, max_y_hw);
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun if (prop.swap_x_y)
529*4882a593Smuzhiyun val ^= IQS5XX_SWITCH_XY_AXIS;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun if (prop.invert_x)
532*4882a593Smuzhiyun val ^= prop.swap_x_y ? IQS5XX_FLIP_Y : IQS5XX_FLIP_X;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun if (prop.invert_y)
535*4882a593Smuzhiyun val ^= prop.swap_x_y ? IQS5XX_FLIP_X : IQS5XX_FLIP_Y;
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun error = iqs5xx_write_byte(client, IQS5XX_XY_CFG0, val);
538*4882a593Smuzhiyun if (error)
539*4882a593Smuzhiyun return error;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun if (prop.max_x > max_x_hw) {
542*4882a593Smuzhiyun dev_err(&client->dev, "Invalid maximum x-coordinate: %u > %u\n",
543*4882a593Smuzhiyun prop.max_x, max_x_hw);
544*4882a593Smuzhiyun return -EINVAL;
545*4882a593Smuzhiyun } else if (prop.max_x == 0) {
546*4882a593Smuzhiyun error = iqs5xx_read_word(client, IQS5XX_X_RES, &max_x);
547*4882a593Smuzhiyun if (error)
548*4882a593Smuzhiyun return error;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun input_abs_set_max(iqs5xx->input,
551*4882a593Smuzhiyun prop.swap_x_y ? ABS_MT_POSITION_Y :
552*4882a593Smuzhiyun ABS_MT_POSITION_X,
553*4882a593Smuzhiyun max_x);
554*4882a593Smuzhiyun } else {
555*4882a593Smuzhiyun max_x = (u16)prop.max_x;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun if (prop.max_y > max_y_hw) {
559*4882a593Smuzhiyun dev_err(&client->dev, "Invalid maximum y-coordinate: %u > %u\n",
560*4882a593Smuzhiyun prop.max_y, max_y_hw);
561*4882a593Smuzhiyun return -EINVAL;
562*4882a593Smuzhiyun } else if (prop.max_y == 0) {
563*4882a593Smuzhiyun error = iqs5xx_read_word(client, IQS5XX_Y_RES, &max_y);
564*4882a593Smuzhiyun if (error)
565*4882a593Smuzhiyun return error;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun input_abs_set_max(iqs5xx->input,
568*4882a593Smuzhiyun prop.swap_x_y ? ABS_MT_POSITION_X :
569*4882a593Smuzhiyun ABS_MT_POSITION_Y,
570*4882a593Smuzhiyun max_y);
571*4882a593Smuzhiyun } else {
572*4882a593Smuzhiyun max_y = (u16)prop.max_y;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun /*
576*4882a593Smuzhiyun * Write horizontal and vertical resolution to the device in case its
577*4882a593Smuzhiyun * original defaults were overridden or swapped as per the properties
578*4882a593Smuzhiyun * specified in the device tree.
579*4882a593Smuzhiyun */
580*4882a593Smuzhiyun error = iqs5xx_write_word(client,
581*4882a593Smuzhiyun prop.swap_x_y ? IQS5XX_Y_RES : IQS5XX_X_RES,
582*4882a593Smuzhiyun max_x);
583*4882a593Smuzhiyun if (error)
584*4882a593Smuzhiyun return error;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun error = iqs5xx_write_word(client,
587*4882a593Smuzhiyun prop.swap_x_y ? IQS5XX_X_RES : IQS5XX_Y_RES,
588*4882a593Smuzhiyun max_y);
589*4882a593Smuzhiyun if (error)
590*4882a593Smuzhiyun return error;
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun error = input_mt_init_slots(iqs5xx->input, IQS5XX_NUM_CONTACTS,
593*4882a593Smuzhiyun INPUT_MT_DIRECT);
594*4882a593Smuzhiyun if (error)
595*4882a593Smuzhiyun dev_err(&client->dev, "Failed to initialize slots: %d\n",
596*4882a593Smuzhiyun error);
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun return error;
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
iqs5xx_dev_init(struct i2c_client * client)601*4882a593Smuzhiyun static int iqs5xx_dev_init(struct i2c_client *client)
602*4882a593Smuzhiyun {
603*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = i2c_get_clientdata(client);
604*4882a593Smuzhiyun struct iqs5xx_dev_id_info *dev_id_info;
605*4882a593Smuzhiyun int error;
606*4882a593Smuzhiyun u8 val;
607*4882a593Smuzhiyun u8 buf[sizeof(*dev_id_info) + 1];
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun error = iqs5xx_read_burst(client, IQS5XX_PROD_NUM,
610*4882a593Smuzhiyun &buf[1], sizeof(*dev_id_info));
611*4882a593Smuzhiyun if (error)
612*4882a593Smuzhiyun return iqs5xx_bl_open(client);
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun /*
615*4882a593Smuzhiyun * A000 and B000 devices use 8-bit and 16-bit addressing, respectively.
616*4882a593Smuzhiyun * Querying an A000 device's version information with 16-bit addressing
617*4882a593Smuzhiyun * gives the appearance that the data is shifted by one byte; a nonzero
618*4882a593Smuzhiyun * leading array element suggests this could be the case (in which case
619*4882a593Smuzhiyun * the missing zero is prepended).
620*4882a593Smuzhiyun */
621*4882a593Smuzhiyun buf[0] = 0;
622*4882a593Smuzhiyun dev_id_info = (struct iqs5xx_dev_id_info *)&buf[(buf[1] > 0) ? 0 : 1];
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun switch (be16_to_cpu(dev_id_info->prod_num)) {
625*4882a593Smuzhiyun case IQS5XX_PROD_NUM_IQS550:
626*4882a593Smuzhiyun case IQS5XX_PROD_NUM_IQS572:
627*4882a593Smuzhiyun case IQS5XX_PROD_NUM_IQS525:
628*4882a593Smuzhiyun break;
629*4882a593Smuzhiyun default:
630*4882a593Smuzhiyun dev_err(&client->dev, "Unrecognized product number: %u\n",
631*4882a593Smuzhiyun be16_to_cpu(dev_id_info->prod_num));
632*4882a593Smuzhiyun return -EINVAL;
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun switch (be16_to_cpu(dev_id_info->proj_num)) {
636*4882a593Smuzhiyun case IQS5XX_PROJ_NUM_A000:
637*4882a593Smuzhiyun dev_err(&client->dev, "Unsupported project number: %u\n",
638*4882a593Smuzhiyun be16_to_cpu(dev_id_info->proj_num));
639*4882a593Smuzhiyun return iqs5xx_bl_open(client);
640*4882a593Smuzhiyun case IQS5XX_PROJ_NUM_B000:
641*4882a593Smuzhiyun break;
642*4882a593Smuzhiyun default:
643*4882a593Smuzhiyun dev_err(&client->dev, "Unrecognized project number: %u\n",
644*4882a593Smuzhiyun be16_to_cpu(dev_id_info->proj_num));
645*4882a593Smuzhiyun return -EINVAL;
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun if (dev_id_info->major_ver < IQS5XX_MAJOR_VER_MIN) {
649*4882a593Smuzhiyun dev_err(&client->dev, "Unsupported major version: %u\n",
650*4882a593Smuzhiyun dev_id_info->major_ver);
651*4882a593Smuzhiyun return iqs5xx_bl_open(client);
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun switch (dev_id_info->bl_status) {
655*4882a593Smuzhiyun case IQS5XX_BL_STATUS_AVAIL:
656*4882a593Smuzhiyun case IQS5XX_BL_STATUS_NONE:
657*4882a593Smuzhiyun break;
658*4882a593Smuzhiyun default:
659*4882a593Smuzhiyun dev_err(&client->dev,
660*4882a593Smuzhiyun "Unrecognized bootloader status: 0x%02X\n",
661*4882a593Smuzhiyun dev_id_info->bl_status);
662*4882a593Smuzhiyun return -EINVAL;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun error = iqs5xx_axis_init(client);
666*4882a593Smuzhiyun if (error)
667*4882a593Smuzhiyun return error;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun error = iqs5xx_read_byte(client, IQS5XX_SYS_CFG0, &val);
670*4882a593Smuzhiyun if (error)
671*4882a593Smuzhiyun return error;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun val |= IQS5XX_SETUP_COMPLETE;
674*4882a593Smuzhiyun val &= ~IQS5XX_SW_INPUT_EVENT;
675*4882a593Smuzhiyun error = iqs5xx_write_byte(client, IQS5XX_SYS_CFG0, val);
676*4882a593Smuzhiyun if (error)
677*4882a593Smuzhiyun return error;
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun val = IQS5XX_TP_EVENT | IQS5XX_EVENT_MODE;
680*4882a593Smuzhiyun error = iqs5xx_write_byte(client, IQS5XX_SYS_CFG1, val);
681*4882a593Smuzhiyun if (error)
682*4882a593Smuzhiyun return error;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun error = iqs5xx_write_byte(client, IQS5XX_END_COMM, 0);
685*4882a593Smuzhiyun if (error)
686*4882a593Smuzhiyun return error;
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun iqs5xx->bl_status = dev_id_info->bl_status;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun /*
691*4882a593Smuzhiyun * Closure of the first communication window that appears following the
692*4882a593Smuzhiyun * release of reset appears to kick off an initialization period during
693*4882a593Smuzhiyun * which further communication is met with clock stretching. The return
694*4882a593Smuzhiyun * from this function is delayed so that further communication attempts
695*4882a593Smuzhiyun * avoid this period.
696*4882a593Smuzhiyun */
697*4882a593Smuzhiyun msleep(100);
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun return 0;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
iqs5xx_irq(int irq,void * data)702*4882a593Smuzhiyun static irqreturn_t iqs5xx_irq(int irq, void *data)
703*4882a593Smuzhiyun {
704*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = data;
705*4882a593Smuzhiyun struct iqs5xx_touch_data touch_data[IQS5XX_NUM_CONTACTS];
706*4882a593Smuzhiyun struct i2c_client *client = iqs5xx->client;
707*4882a593Smuzhiyun struct input_dev *input = iqs5xx->input;
708*4882a593Smuzhiyun int error, i;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun /*
711*4882a593Smuzhiyun * This check is purely a precaution, as the device does not assert the
712*4882a593Smuzhiyun * RDY output during bootloader mode. If the device operates outside of
713*4882a593Smuzhiyun * bootloader mode, the input device is guaranteed to be allocated.
714*4882a593Smuzhiyun */
715*4882a593Smuzhiyun if (iqs5xx->bl_status == IQS5XX_BL_STATUS_RESET)
716*4882a593Smuzhiyun return IRQ_NONE;
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun error = iqs5xx_read_burst(client, IQS5XX_ABS_X,
719*4882a593Smuzhiyun touch_data, sizeof(touch_data));
720*4882a593Smuzhiyun if (error)
721*4882a593Smuzhiyun return IRQ_NONE;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(touch_data); i++) {
724*4882a593Smuzhiyun u16 pressure = be16_to_cpu(touch_data[i].strength);
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun input_mt_slot(input, i);
727*4882a593Smuzhiyun if (input_mt_report_slot_state(input, MT_TOOL_FINGER,
728*4882a593Smuzhiyun pressure != 0)) {
729*4882a593Smuzhiyun input_report_abs(input, ABS_MT_POSITION_X,
730*4882a593Smuzhiyun be16_to_cpu(touch_data[i].abs_x));
731*4882a593Smuzhiyun input_report_abs(input, ABS_MT_POSITION_Y,
732*4882a593Smuzhiyun be16_to_cpu(touch_data[i].abs_y));
733*4882a593Smuzhiyun input_report_abs(input, ABS_MT_PRESSURE, pressure);
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun }
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun input_mt_sync_frame(input);
738*4882a593Smuzhiyun input_sync(input);
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun error = iqs5xx_write_byte(client, IQS5XX_END_COMM, 0);
741*4882a593Smuzhiyun if (error)
742*4882a593Smuzhiyun return IRQ_NONE;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun /*
745*4882a593Smuzhiyun * Once the communication window is closed, a small delay is added to
746*4882a593Smuzhiyun * ensure the device's RDY output has been deasserted by the time the
747*4882a593Smuzhiyun * interrupt handler returns.
748*4882a593Smuzhiyun */
749*4882a593Smuzhiyun usleep_range(50, 100);
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun return IRQ_HANDLED;
752*4882a593Smuzhiyun }
753*4882a593Smuzhiyun
iqs5xx_fw_file_parse(struct i2c_client * client,const char * fw_file,u8 * pmap)754*4882a593Smuzhiyun static int iqs5xx_fw_file_parse(struct i2c_client *client,
755*4882a593Smuzhiyun const char *fw_file, u8 *pmap)
756*4882a593Smuzhiyun {
757*4882a593Smuzhiyun const struct firmware *fw;
758*4882a593Smuzhiyun struct iqs5xx_ihex_rec *rec;
759*4882a593Smuzhiyun size_t pos = 0;
760*4882a593Smuzhiyun int error, i;
761*4882a593Smuzhiyun u16 rec_num = 1;
762*4882a593Smuzhiyun u16 rec_addr;
763*4882a593Smuzhiyun u8 rec_len, rec_type, rec_chksm, chksm;
764*4882a593Smuzhiyun u8 rec_hdr[IQS5XX_REC_HDR_LEN];
765*4882a593Smuzhiyun u8 rec_data[IQS5XX_REC_LEN_MAX];
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun /*
768*4882a593Smuzhiyun * Firmware exported from the vendor's configuration tool deviates from
769*4882a593Smuzhiyun * standard ihex as follows: (1) the checksum for records corresponding
770*4882a593Smuzhiyun * to user-exported settings is not recalculated, and (2) an address of
771*4882a593Smuzhiyun * 0xFFFF is used for the EOF record.
772*4882a593Smuzhiyun *
773*4882a593Smuzhiyun * Because the ihex2fw tool tolerates neither (1) nor (2), the slightly
774*4882a593Smuzhiyun * nonstandard ihex firmware is parsed directly by the driver.
775*4882a593Smuzhiyun */
776*4882a593Smuzhiyun error = request_firmware(&fw, fw_file, &client->dev);
777*4882a593Smuzhiyun if (error) {
778*4882a593Smuzhiyun dev_err(&client->dev, "Failed to request firmware %s: %d\n",
779*4882a593Smuzhiyun fw_file, error);
780*4882a593Smuzhiyun return error;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun do {
784*4882a593Smuzhiyun if (pos + sizeof(*rec) > fw->size) {
785*4882a593Smuzhiyun dev_err(&client->dev, "Insufficient firmware size\n");
786*4882a593Smuzhiyun error = -EINVAL;
787*4882a593Smuzhiyun break;
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun rec = (struct iqs5xx_ihex_rec *)(fw->data + pos);
790*4882a593Smuzhiyun pos += sizeof(*rec);
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun if (rec->start != ':') {
793*4882a593Smuzhiyun dev_err(&client->dev, "Invalid start at record %u\n",
794*4882a593Smuzhiyun rec_num);
795*4882a593Smuzhiyun error = -EINVAL;
796*4882a593Smuzhiyun break;
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun error = hex2bin(rec_hdr, rec->len, sizeof(rec_hdr));
800*4882a593Smuzhiyun if (error) {
801*4882a593Smuzhiyun dev_err(&client->dev, "Invalid header at record %u\n",
802*4882a593Smuzhiyun rec_num);
803*4882a593Smuzhiyun break;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun rec_len = *rec_hdr;
807*4882a593Smuzhiyun rec_addr = get_unaligned_be16(rec_hdr + sizeof(rec_len));
808*4882a593Smuzhiyun rec_type = *(rec_hdr + sizeof(rec_len) + sizeof(rec_addr));
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun if (pos + rec_len * 2 > fw->size) {
811*4882a593Smuzhiyun dev_err(&client->dev, "Insufficient firmware size\n");
812*4882a593Smuzhiyun error = -EINVAL;
813*4882a593Smuzhiyun break;
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun pos += (rec_len * 2);
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun error = hex2bin(rec_data, rec->data, rec_len);
818*4882a593Smuzhiyun if (error) {
819*4882a593Smuzhiyun dev_err(&client->dev, "Invalid data at record %u\n",
820*4882a593Smuzhiyun rec_num);
821*4882a593Smuzhiyun break;
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun error = hex2bin(&rec_chksm,
825*4882a593Smuzhiyun rec->data + rec_len * 2, sizeof(rec_chksm));
826*4882a593Smuzhiyun if (error) {
827*4882a593Smuzhiyun dev_err(&client->dev, "Invalid checksum at record %u\n",
828*4882a593Smuzhiyun rec_num);
829*4882a593Smuzhiyun break;
830*4882a593Smuzhiyun }
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun chksm = 0;
833*4882a593Smuzhiyun for (i = 0; i < sizeof(rec_hdr); i++)
834*4882a593Smuzhiyun chksm += rec_hdr[i];
835*4882a593Smuzhiyun for (i = 0; i < rec_len; i++)
836*4882a593Smuzhiyun chksm += rec_data[i];
837*4882a593Smuzhiyun chksm = ~chksm + 1;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun if (chksm != rec_chksm && rec_addr < IQS5XX_CSTM) {
840*4882a593Smuzhiyun dev_err(&client->dev,
841*4882a593Smuzhiyun "Incorrect checksum at record %u\n",
842*4882a593Smuzhiyun rec_num);
843*4882a593Smuzhiyun error = -EINVAL;
844*4882a593Smuzhiyun break;
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun switch (rec_type) {
848*4882a593Smuzhiyun case IQS5XX_REC_TYPE_DATA:
849*4882a593Smuzhiyun if (rec_addr < IQS5XX_CHKSM ||
850*4882a593Smuzhiyun rec_addr > IQS5XX_PMAP_END) {
851*4882a593Smuzhiyun dev_err(&client->dev,
852*4882a593Smuzhiyun "Invalid address at record %u\n",
853*4882a593Smuzhiyun rec_num);
854*4882a593Smuzhiyun error = -EINVAL;
855*4882a593Smuzhiyun } else {
856*4882a593Smuzhiyun memcpy(pmap + rec_addr - IQS5XX_CHKSM,
857*4882a593Smuzhiyun rec_data, rec_len);
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun break;
860*4882a593Smuzhiyun case IQS5XX_REC_TYPE_EOF:
861*4882a593Smuzhiyun break;
862*4882a593Smuzhiyun default:
863*4882a593Smuzhiyun dev_err(&client->dev, "Invalid type at record %u\n",
864*4882a593Smuzhiyun rec_num);
865*4882a593Smuzhiyun error = -EINVAL;
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun if (error)
869*4882a593Smuzhiyun break;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun rec_num++;
872*4882a593Smuzhiyun while (pos < fw->size) {
873*4882a593Smuzhiyun if (*(fw->data + pos) == ':')
874*4882a593Smuzhiyun break;
875*4882a593Smuzhiyun pos++;
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun } while (rec_type != IQS5XX_REC_TYPE_EOF);
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun release_firmware(fw);
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun return error;
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun
iqs5xx_fw_file_write(struct i2c_client * client,const char * fw_file)884*4882a593Smuzhiyun static int iqs5xx_fw_file_write(struct i2c_client *client, const char *fw_file)
885*4882a593Smuzhiyun {
886*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = i2c_get_clientdata(client);
887*4882a593Smuzhiyun int error;
888*4882a593Smuzhiyun u8 *pmap;
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun if (iqs5xx->bl_status == IQS5XX_BL_STATUS_NONE)
891*4882a593Smuzhiyun return -EPERM;
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun pmap = kzalloc(IQS5XX_PMAP_LEN, GFP_KERNEL);
894*4882a593Smuzhiyun if (!pmap)
895*4882a593Smuzhiyun return -ENOMEM;
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun error = iqs5xx_fw_file_parse(client, fw_file, pmap);
898*4882a593Smuzhiyun if (error)
899*4882a593Smuzhiyun goto err_kfree;
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun mutex_lock(&iqs5xx->lock);
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun /*
904*4882a593Smuzhiyun * Disable the interrupt line in case the first attempt(s) to enter the
905*4882a593Smuzhiyun * bootloader don't happen quickly enough, in which case the device may
906*4882a593Smuzhiyun * assert the RDY output until the next attempt.
907*4882a593Smuzhiyun */
908*4882a593Smuzhiyun disable_irq(client->irq);
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun iqs5xx->bl_status = IQS5XX_BL_STATUS_RESET;
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun error = iqs5xx_bl_cmd(client, IQS5XX_BL_CMD_VER, 0);
913*4882a593Smuzhiyun if (error) {
914*4882a593Smuzhiyun error = iqs5xx_bl_open(client);
915*4882a593Smuzhiyun if (error)
916*4882a593Smuzhiyun goto err_reset;
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun error = iqs5xx_bl_write(client, IQS5XX_CHKSM, pmap, IQS5XX_PMAP_LEN);
920*4882a593Smuzhiyun if (error)
921*4882a593Smuzhiyun goto err_reset;
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun error = iqs5xx_bl_cmd(client, IQS5XX_BL_CMD_CRC, 0);
924*4882a593Smuzhiyun if (error)
925*4882a593Smuzhiyun goto err_reset;
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun error = iqs5xx_bl_verify(client, IQS5XX_CSTM,
928*4882a593Smuzhiyun pmap + IQS5XX_CHKSM_LEN + IQS5XX_APP_LEN,
929*4882a593Smuzhiyun IQS5XX_CSTM_LEN);
930*4882a593Smuzhiyun if (error)
931*4882a593Smuzhiyun goto err_reset;
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun error = iqs5xx_bl_cmd(client, IQS5XX_BL_CMD_EXEC, 0);
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun err_reset:
936*4882a593Smuzhiyun if (error) {
937*4882a593Smuzhiyun iqs5xx_reset(client);
938*4882a593Smuzhiyun usleep_range(10000, 10100);
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun error = iqs5xx_dev_init(client);
942*4882a593Smuzhiyun if (!error && iqs5xx->bl_status == IQS5XX_BL_STATUS_RESET)
943*4882a593Smuzhiyun error = -EINVAL;
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun enable_irq(client->irq);
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun mutex_unlock(&iqs5xx->lock);
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun err_kfree:
950*4882a593Smuzhiyun kfree(pmap);
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun return error;
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun
fw_file_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)955*4882a593Smuzhiyun static ssize_t fw_file_store(struct device *dev, struct device_attribute *attr,
956*4882a593Smuzhiyun const char *buf, size_t count)
957*4882a593Smuzhiyun {
958*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = dev_get_drvdata(dev);
959*4882a593Smuzhiyun struct i2c_client *client = iqs5xx->client;
960*4882a593Smuzhiyun size_t len = count;
961*4882a593Smuzhiyun bool input_reg = !iqs5xx->input;
962*4882a593Smuzhiyun char fw_file[IQS5XX_FW_FILE_LEN + 1];
963*4882a593Smuzhiyun int error;
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun if (!len)
966*4882a593Smuzhiyun return -EINVAL;
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun if (buf[len - 1] == '\n')
969*4882a593Smuzhiyun len--;
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun if (len > IQS5XX_FW_FILE_LEN)
972*4882a593Smuzhiyun return -ENAMETOOLONG;
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun memcpy(fw_file, buf, len);
975*4882a593Smuzhiyun fw_file[len] = '\0';
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun error = iqs5xx_fw_file_write(client, fw_file);
978*4882a593Smuzhiyun if (error)
979*4882a593Smuzhiyun return error;
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun /*
982*4882a593Smuzhiyun * If the input device was not allocated already, it is guaranteed to
983*4882a593Smuzhiyun * be allocated by this point and can finally be registered.
984*4882a593Smuzhiyun */
985*4882a593Smuzhiyun if (input_reg) {
986*4882a593Smuzhiyun error = input_register_device(iqs5xx->input);
987*4882a593Smuzhiyun if (error) {
988*4882a593Smuzhiyun dev_err(&client->dev,
989*4882a593Smuzhiyun "Failed to register device: %d\n",
990*4882a593Smuzhiyun error);
991*4882a593Smuzhiyun return error;
992*4882a593Smuzhiyun }
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun return count;
996*4882a593Smuzhiyun }
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun static DEVICE_ATTR_WO(fw_file);
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun static struct attribute *iqs5xx_attrs[] = {
1001*4882a593Smuzhiyun &dev_attr_fw_file.attr,
1002*4882a593Smuzhiyun NULL,
1003*4882a593Smuzhiyun };
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun static const struct attribute_group iqs5xx_attr_group = {
1006*4882a593Smuzhiyun .attrs = iqs5xx_attrs,
1007*4882a593Smuzhiyun };
1008*4882a593Smuzhiyun
iqs5xx_suspend(struct device * dev)1009*4882a593Smuzhiyun static int __maybe_unused iqs5xx_suspend(struct device *dev)
1010*4882a593Smuzhiyun {
1011*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = dev_get_drvdata(dev);
1012*4882a593Smuzhiyun struct input_dev *input = iqs5xx->input;
1013*4882a593Smuzhiyun int error = 0;
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun if (!input)
1016*4882a593Smuzhiyun return error;
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun mutex_lock(&input->mutex);
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun if (input->users)
1021*4882a593Smuzhiyun error = iqs5xx_set_state(iqs5xx->client, IQS5XX_SUSPEND);
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun mutex_unlock(&input->mutex);
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun return error;
1026*4882a593Smuzhiyun }
1027*4882a593Smuzhiyun
iqs5xx_resume(struct device * dev)1028*4882a593Smuzhiyun static int __maybe_unused iqs5xx_resume(struct device *dev)
1029*4882a593Smuzhiyun {
1030*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx = dev_get_drvdata(dev);
1031*4882a593Smuzhiyun struct input_dev *input = iqs5xx->input;
1032*4882a593Smuzhiyun int error = 0;
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun if (!input)
1035*4882a593Smuzhiyun return error;
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun mutex_lock(&input->mutex);
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun if (input->users)
1040*4882a593Smuzhiyun error = iqs5xx_set_state(iqs5xx->client, IQS5XX_RESUME);
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun mutex_unlock(&input->mutex);
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun return error;
1045*4882a593Smuzhiyun }
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(iqs5xx_pm, iqs5xx_suspend, iqs5xx_resume);
1048*4882a593Smuzhiyun
iqs5xx_probe(struct i2c_client * client,const struct i2c_device_id * id)1049*4882a593Smuzhiyun static int iqs5xx_probe(struct i2c_client *client,
1050*4882a593Smuzhiyun const struct i2c_device_id *id)
1051*4882a593Smuzhiyun {
1052*4882a593Smuzhiyun struct iqs5xx_private *iqs5xx;
1053*4882a593Smuzhiyun int error;
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun iqs5xx = devm_kzalloc(&client->dev, sizeof(*iqs5xx), GFP_KERNEL);
1056*4882a593Smuzhiyun if (!iqs5xx)
1057*4882a593Smuzhiyun return -ENOMEM;
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun i2c_set_clientdata(client, iqs5xx);
1060*4882a593Smuzhiyun iqs5xx->client = client;
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun iqs5xx->reset_gpio = devm_gpiod_get(&client->dev,
1063*4882a593Smuzhiyun "reset", GPIOD_OUT_LOW);
1064*4882a593Smuzhiyun if (IS_ERR(iqs5xx->reset_gpio)) {
1065*4882a593Smuzhiyun error = PTR_ERR(iqs5xx->reset_gpio);
1066*4882a593Smuzhiyun dev_err(&client->dev, "Failed to request GPIO: %d\n", error);
1067*4882a593Smuzhiyun return error;
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun mutex_init(&iqs5xx->lock);
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun iqs5xx_reset(client);
1073*4882a593Smuzhiyun usleep_range(10000, 10100);
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun error = iqs5xx_dev_init(client);
1076*4882a593Smuzhiyun if (error)
1077*4882a593Smuzhiyun return error;
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun error = devm_request_threaded_irq(&client->dev, client->irq,
1080*4882a593Smuzhiyun NULL, iqs5xx_irq, IRQF_ONESHOT,
1081*4882a593Smuzhiyun client->name, iqs5xx);
1082*4882a593Smuzhiyun if (error) {
1083*4882a593Smuzhiyun dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
1084*4882a593Smuzhiyun return error;
1085*4882a593Smuzhiyun }
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun error = devm_device_add_group(&client->dev, &iqs5xx_attr_group);
1088*4882a593Smuzhiyun if (error) {
1089*4882a593Smuzhiyun dev_err(&client->dev, "Failed to add attributes: %d\n", error);
1090*4882a593Smuzhiyun return error;
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun if (iqs5xx->input) {
1094*4882a593Smuzhiyun error = input_register_device(iqs5xx->input);
1095*4882a593Smuzhiyun if (error)
1096*4882a593Smuzhiyun dev_err(&client->dev,
1097*4882a593Smuzhiyun "Failed to register device: %d\n",
1098*4882a593Smuzhiyun error);
1099*4882a593Smuzhiyun }
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun return error;
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun static const struct i2c_device_id iqs5xx_id[] = {
1105*4882a593Smuzhiyun { "iqs550", 0 },
1106*4882a593Smuzhiyun { "iqs572", 1 },
1107*4882a593Smuzhiyun { "iqs525", 2 },
1108*4882a593Smuzhiyun { }
1109*4882a593Smuzhiyun };
1110*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, iqs5xx_id);
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun static const struct of_device_id iqs5xx_of_match[] = {
1113*4882a593Smuzhiyun { .compatible = "azoteq,iqs550" },
1114*4882a593Smuzhiyun { .compatible = "azoteq,iqs572" },
1115*4882a593Smuzhiyun { .compatible = "azoteq,iqs525" },
1116*4882a593Smuzhiyun { }
1117*4882a593Smuzhiyun };
1118*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, iqs5xx_of_match);
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun static struct i2c_driver iqs5xx_i2c_driver = {
1121*4882a593Smuzhiyun .driver = {
1122*4882a593Smuzhiyun .name = "iqs5xx",
1123*4882a593Smuzhiyun .of_match_table = iqs5xx_of_match,
1124*4882a593Smuzhiyun .pm = &iqs5xx_pm,
1125*4882a593Smuzhiyun },
1126*4882a593Smuzhiyun .id_table = iqs5xx_id,
1127*4882a593Smuzhiyun .probe = iqs5xx_probe,
1128*4882a593Smuzhiyun };
1129*4882a593Smuzhiyun module_i2c_driver(iqs5xx_i2c_driver);
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
1132*4882a593Smuzhiyun MODULE_DESCRIPTION("Azoteq IQS550/572/525 Trackpad/Touchscreen Controller");
1133*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1134