xref: /OK3568_Linux_fs/kernel/drivers/input/touchscreen/imx6ul_tsc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Freescale i.MX6UL touchscreen controller driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2015 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/errno.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
11*4882a593Smuzhiyun #include <linux/input.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/completion.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/clk.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <linux/log2.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* ADC configuration registers field define */
23*4882a593Smuzhiyun #define ADC_AIEN		(0x1 << 7)
24*4882a593Smuzhiyun #define ADC_CONV_DISABLE	0x1F
25*4882a593Smuzhiyun #define ADC_AVGE		(0x1 << 5)
26*4882a593Smuzhiyun #define ADC_CAL			(0x1 << 7)
27*4882a593Smuzhiyun #define ADC_CALF		0x2
28*4882a593Smuzhiyun #define ADC_12BIT_MODE		(0x2 << 2)
29*4882a593Smuzhiyun #define ADC_CONV_MODE_MASK	(0x3 << 2)
30*4882a593Smuzhiyun #define ADC_IPG_CLK		0x00
31*4882a593Smuzhiyun #define ADC_INPUT_CLK_MASK	0x3
32*4882a593Smuzhiyun #define ADC_CLK_DIV_8		(0x03 << 5)
33*4882a593Smuzhiyun #define ADC_CLK_DIV_MASK	(0x3 << 5)
34*4882a593Smuzhiyun #define ADC_SHORT_SAMPLE_MODE	(0x0 << 4)
35*4882a593Smuzhiyun #define ADC_SAMPLE_MODE_MASK	(0x1 << 4)
36*4882a593Smuzhiyun #define ADC_HARDWARE_TRIGGER	(0x1 << 13)
37*4882a593Smuzhiyun #define ADC_AVGS_SHIFT		14
38*4882a593Smuzhiyun #define ADC_AVGS_MASK		(0x3 << 14)
39*4882a593Smuzhiyun #define SELECT_CHANNEL_4	0x04
40*4882a593Smuzhiyun #define SELECT_CHANNEL_1	0x01
41*4882a593Smuzhiyun #define DISABLE_CONVERSION_INT	(0x0 << 7)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* ADC registers */
44*4882a593Smuzhiyun #define REG_ADC_HC0		0x00
45*4882a593Smuzhiyun #define REG_ADC_HC1		0x04
46*4882a593Smuzhiyun #define REG_ADC_HC2		0x08
47*4882a593Smuzhiyun #define REG_ADC_HC3		0x0C
48*4882a593Smuzhiyun #define REG_ADC_HC4		0x10
49*4882a593Smuzhiyun #define REG_ADC_HS		0x14
50*4882a593Smuzhiyun #define REG_ADC_R0		0x18
51*4882a593Smuzhiyun #define REG_ADC_CFG		0x2C
52*4882a593Smuzhiyun #define REG_ADC_GC		0x30
53*4882a593Smuzhiyun #define REG_ADC_GS		0x34
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define ADC_TIMEOUT		msecs_to_jiffies(100)
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun /* TSC registers */
58*4882a593Smuzhiyun #define REG_TSC_BASIC_SETING	0x00
59*4882a593Smuzhiyun #define REG_TSC_PRE_CHARGE_TIME	0x10
60*4882a593Smuzhiyun #define REG_TSC_FLOW_CONTROL	0x20
61*4882a593Smuzhiyun #define REG_TSC_MEASURE_VALUE	0x30
62*4882a593Smuzhiyun #define REG_TSC_INT_EN		0x40
63*4882a593Smuzhiyun #define REG_TSC_INT_SIG_EN	0x50
64*4882a593Smuzhiyun #define REG_TSC_INT_STATUS	0x60
65*4882a593Smuzhiyun #define REG_TSC_DEBUG_MODE	0x70
66*4882a593Smuzhiyun #define REG_TSC_DEBUG_MODE2	0x80
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /* TSC configuration registers field define */
69*4882a593Smuzhiyun #define DETECT_4_WIRE_MODE	(0x0 << 4)
70*4882a593Smuzhiyun #define AUTO_MEASURE		0x1
71*4882a593Smuzhiyun #define MEASURE_SIGNAL		0x1
72*4882a593Smuzhiyun #define DETECT_SIGNAL		(0x1 << 4)
73*4882a593Smuzhiyun #define VALID_SIGNAL		(0x1 << 8)
74*4882a593Smuzhiyun #define MEASURE_INT_EN		0x1
75*4882a593Smuzhiyun #define MEASURE_SIG_EN		0x1
76*4882a593Smuzhiyun #define VALID_SIG_EN		(0x1 << 8)
77*4882a593Smuzhiyun #define DE_GLITCH_2		(0x2 << 29)
78*4882a593Smuzhiyun #define START_SENSE		(0x1 << 12)
79*4882a593Smuzhiyun #define TSC_DISABLE		(0x1 << 16)
80*4882a593Smuzhiyun #define DETECT_MODE		0x2
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun struct imx6ul_tsc {
83*4882a593Smuzhiyun 	struct device *dev;
84*4882a593Smuzhiyun 	struct input_dev *input;
85*4882a593Smuzhiyun 	void __iomem *tsc_regs;
86*4882a593Smuzhiyun 	void __iomem *adc_regs;
87*4882a593Smuzhiyun 	struct clk *tsc_clk;
88*4882a593Smuzhiyun 	struct clk *adc_clk;
89*4882a593Smuzhiyun 	struct gpio_desc *xnur_gpio;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	u32 measure_delay_time;
92*4882a593Smuzhiyun 	u32 pre_charge_time;
93*4882a593Smuzhiyun 	bool average_enable;
94*4882a593Smuzhiyun 	u32 average_select;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	struct completion completion;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun  * TSC module need ADC to get the measure value. So
101*4882a593Smuzhiyun  * before config TSC, we should initialize ADC module.
102*4882a593Smuzhiyun  */
imx6ul_adc_init(struct imx6ul_tsc * tsc)103*4882a593Smuzhiyun static int imx6ul_adc_init(struct imx6ul_tsc *tsc)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	u32 adc_hc = 0;
106*4882a593Smuzhiyun 	u32 adc_gc;
107*4882a593Smuzhiyun 	u32 adc_gs;
108*4882a593Smuzhiyun 	u32 adc_cfg;
109*4882a593Smuzhiyun 	unsigned long timeout;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	reinit_completion(&tsc->completion);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
114*4882a593Smuzhiyun 	adc_cfg &= ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK);
115*4882a593Smuzhiyun 	adc_cfg |= ADC_12BIT_MODE | ADC_IPG_CLK;
116*4882a593Smuzhiyun 	adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK);
117*4882a593Smuzhiyun 	adc_cfg |= ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE;
118*4882a593Smuzhiyun 	if (tsc->average_enable) {
119*4882a593Smuzhiyun 		adc_cfg &= ~ADC_AVGS_MASK;
120*4882a593Smuzhiyun 		adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT;
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 	adc_cfg &= ~ADC_HARDWARE_TRIGGER;
123*4882a593Smuzhiyun 	writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	/* enable calibration interrupt */
126*4882a593Smuzhiyun 	adc_hc |= ADC_AIEN;
127*4882a593Smuzhiyun 	adc_hc |= ADC_CONV_DISABLE;
128*4882a593Smuzhiyun 	writel(adc_hc, tsc->adc_regs + REG_ADC_HC0);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	/* start ADC calibration */
131*4882a593Smuzhiyun 	adc_gc = readl(tsc->adc_regs + REG_ADC_GC);
132*4882a593Smuzhiyun 	adc_gc |= ADC_CAL;
133*4882a593Smuzhiyun 	if (tsc->average_enable)
134*4882a593Smuzhiyun 		adc_gc |= ADC_AVGE;
135*4882a593Smuzhiyun 	writel(adc_gc, tsc->adc_regs + REG_ADC_GC);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	timeout = wait_for_completion_timeout
138*4882a593Smuzhiyun 			(&tsc->completion, ADC_TIMEOUT);
139*4882a593Smuzhiyun 	if (timeout == 0) {
140*4882a593Smuzhiyun 		dev_err(tsc->dev, "Timeout for adc calibration\n");
141*4882a593Smuzhiyun 		return -ETIMEDOUT;
142*4882a593Smuzhiyun 	}
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	adc_gs = readl(tsc->adc_regs + REG_ADC_GS);
145*4882a593Smuzhiyun 	if (adc_gs & ADC_CALF) {
146*4882a593Smuzhiyun 		dev_err(tsc->dev, "ADC calibration failed\n");
147*4882a593Smuzhiyun 		return -EINVAL;
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	/* TSC need the ADC work in hardware trigger */
151*4882a593Smuzhiyun 	adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
152*4882a593Smuzhiyun 	adc_cfg |= ADC_HARDWARE_TRIGGER;
153*4882a593Smuzhiyun 	writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun /*
159*4882a593Smuzhiyun  * This is a TSC workaround. Currently TSC misconnect two
160*4882a593Smuzhiyun  * ADC channels, this function remap channel configure for
161*4882a593Smuzhiyun  * hardware trigger.
162*4882a593Smuzhiyun  */
imx6ul_tsc_channel_config(struct imx6ul_tsc * tsc)163*4882a593Smuzhiyun static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	adc_hc0 = DISABLE_CONVERSION_INT;
168*4882a593Smuzhiyun 	writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	adc_hc1 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_4;
171*4882a593Smuzhiyun 	writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	adc_hc2 = DISABLE_CONVERSION_INT;
174*4882a593Smuzhiyun 	writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	adc_hc3 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_1;
177*4882a593Smuzhiyun 	writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3);
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	adc_hc4 = DISABLE_CONVERSION_INT;
180*4882a593Smuzhiyun 	writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4);
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /*
184*4882a593Smuzhiyun  * TSC setting, confige the pre-charge time and measure delay time.
185*4882a593Smuzhiyun  * different touch screen may need different pre-charge time and
186*4882a593Smuzhiyun  * measure delay time.
187*4882a593Smuzhiyun  */
imx6ul_tsc_set(struct imx6ul_tsc * tsc)188*4882a593Smuzhiyun static void imx6ul_tsc_set(struct imx6ul_tsc *tsc)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	u32 basic_setting = 0;
191*4882a593Smuzhiyun 	u32 start;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	basic_setting |= tsc->measure_delay_time << 8;
194*4882a593Smuzhiyun 	basic_setting |= DETECT_4_WIRE_MODE | AUTO_MEASURE;
195*4882a593Smuzhiyun 	writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME);
200*4882a593Smuzhiyun 	writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN);
201*4882a593Smuzhiyun 	writel(MEASURE_SIG_EN | VALID_SIG_EN,
202*4882a593Smuzhiyun 		tsc->tsc_regs + REG_TSC_INT_SIG_EN);
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	/* start sense detection */
205*4882a593Smuzhiyun 	start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
206*4882a593Smuzhiyun 	start |= START_SENSE;
207*4882a593Smuzhiyun 	start &= ~TSC_DISABLE;
208*4882a593Smuzhiyun 	writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
imx6ul_tsc_init(struct imx6ul_tsc * tsc)211*4882a593Smuzhiyun static int imx6ul_tsc_init(struct imx6ul_tsc *tsc)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	int err;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	err = imx6ul_adc_init(tsc);
216*4882a593Smuzhiyun 	if (err)
217*4882a593Smuzhiyun 		return err;
218*4882a593Smuzhiyun 	imx6ul_tsc_channel_config(tsc);
219*4882a593Smuzhiyun 	imx6ul_tsc_set(tsc);
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	return 0;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
imx6ul_tsc_disable(struct imx6ul_tsc * tsc)224*4882a593Smuzhiyun static void imx6ul_tsc_disable(struct imx6ul_tsc *tsc)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun 	u32 tsc_flow;
227*4882a593Smuzhiyun 	u32 adc_cfg;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	/* TSC controller enters to idle status */
230*4882a593Smuzhiyun 	tsc_flow = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
231*4882a593Smuzhiyun 	tsc_flow |= TSC_DISABLE;
232*4882a593Smuzhiyun 	writel(tsc_flow, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	/* ADC controller enters to stop mode */
235*4882a593Smuzhiyun 	adc_cfg = readl(tsc->adc_regs + REG_ADC_HC0);
236*4882a593Smuzhiyun 	adc_cfg |= ADC_CONV_DISABLE;
237*4882a593Smuzhiyun 	writel(adc_cfg, tsc->adc_regs + REG_ADC_HC0);
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun /* Delay some time (max 2ms), wait the pre-charge done. */
tsc_wait_detect_mode(struct imx6ul_tsc * tsc)241*4882a593Smuzhiyun static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	unsigned long timeout = jiffies + msecs_to_jiffies(2);
244*4882a593Smuzhiyun 	u32 state_machine;
245*4882a593Smuzhiyun 	u32 debug_mode2;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	do {
248*4882a593Smuzhiyun 		if (time_after(jiffies, timeout))
249*4882a593Smuzhiyun 			return false;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 		usleep_range(200, 400);
252*4882a593Smuzhiyun 		debug_mode2 = readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
253*4882a593Smuzhiyun 		state_machine = (debug_mode2 >> 20) & 0x7;
254*4882a593Smuzhiyun 	} while (state_machine != DETECT_MODE);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	usleep_range(200, 400);
257*4882a593Smuzhiyun 	return true;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun 
tsc_irq_fn(int irq,void * dev_id)260*4882a593Smuzhiyun static irqreturn_t tsc_irq_fn(int irq, void *dev_id)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	struct imx6ul_tsc *tsc = dev_id;
263*4882a593Smuzhiyun 	u32 status;
264*4882a593Smuzhiyun 	u32 value;
265*4882a593Smuzhiyun 	u32 x, y;
266*4882a593Smuzhiyun 	u32 start;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	status = readl(tsc->tsc_regs + REG_TSC_INT_STATUS);
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	/* write 1 to clear the bit measure-signal */
271*4882a593Smuzhiyun 	writel(MEASURE_SIGNAL | DETECT_SIGNAL,
272*4882a593Smuzhiyun 		tsc->tsc_regs + REG_TSC_INT_STATUS);
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	/* It's a HW self-clean bit. Set this bit and start sense detection */
275*4882a593Smuzhiyun 	start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
276*4882a593Smuzhiyun 	start |= START_SENSE;
277*4882a593Smuzhiyun 	writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	if (status & MEASURE_SIGNAL) {
280*4882a593Smuzhiyun 		value = readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE);
281*4882a593Smuzhiyun 		x = (value >> 16) & 0x0fff;
282*4882a593Smuzhiyun 		y = value & 0x0fff;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 		/*
285*4882a593Smuzhiyun 		 * In detect mode, we can get the xnur gpio value,
286*4882a593Smuzhiyun 		 * otherwise assume contact is stiull active.
287*4882a593Smuzhiyun 		 */
288*4882a593Smuzhiyun 		if (!tsc_wait_detect_mode(tsc) ||
289*4882a593Smuzhiyun 		    gpiod_get_value_cansleep(tsc->xnur_gpio)) {
290*4882a593Smuzhiyun 			input_report_key(tsc->input, BTN_TOUCH, 1);
291*4882a593Smuzhiyun 			input_report_abs(tsc->input, ABS_X, x);
292*4882a593Smuzhiyun 			input_report_abs(tsc->input, ABS_Y, y);
293*4882a593Smuzhiyun 		} else {
294*4882a593Smuzhiyun 			input_report_key(tsc->input, BTN_TOUCH, 0);
295*4882a593Smuzhiyun 		}
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 		input_sync(tsc->input);
298*4882a593Smuzhiyun 	}
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	return IRQ_HANDLED;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
adc_irq_fn(int irq,void * dev_id)303*4882a593Smuzhiyun static irqreturn_t adc_irq_fn(int irq, void *dev_id)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun 	struct imx6ul_tsc *tsc = dev_id;
306*4882a593Smuzhiyun 	u32 coco;
307*4882a593Smuzhiyun 	u32 value;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	coco = readl(tsc->adc_regs + REG_ADC_HS);
310*4882a593Smuzhiyun 	if (coco & 0x01) {
311*4882a593Smuzhiyun 		value = readl(tsc->adc_regs + REG_ADC_R0);
312*4882a593Smuzhiyun 		complete(&tsc->completion);
313*4882a593Smuzhiyun 	}
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	return IRQ_HANDLED;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
imx6ul_tsc_start(struct imx6ul_tsc * tsc)318*4882a593Smuzhiyun static int imx6ul_tsc_start(struct imx6ul_tsc *tsc)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun 	int err;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	err = clk_prepare_enable(tsc->adc_clk);
323*4882a593Smuzhiyun 	if (err) {
324*4882a593Smuzhiyun 		dev_err(tsc->dev,
325*4882a593Smuzhiyun 			"Could not prepare or enable the adc clock: %d\n",
326*4882a593Smuzhiyun 			err);
327*4882a593Smuzhiyun 		return err;
328*4882a593Smuzhiyun 	}
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	err = clk_prepare_enable(tsc->tsc_clk);
331*4882a593Smuzhiyun 	if (err) {
332*4882a593Smuzhiyun 		dev_err(tsc->dev,
333*4882a593Smuzhiyun 			"Could not prepare or enable the tsc clock: %d\n",
334*4882a593Smuzhiyun 			err);
335*4882a593Smuzhiyun 		goto disable_adc_clk;
336*4882a593Smuzhiyun 	}
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	err = imx6ul_tsc_init(tsc);
339*4882a593Smuzhiyun 	if (err)
340*4882a593Smuzhiyun 		goto disable_tsc_clk;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	return 0;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun disable_tsc_clk:
345*4882a593Smuzhiyun 	clk_disable_unprepare(tsc->tsc_clk);
346*4882a593Smuzhiyun disable_adc_clk:
347*4882a593Smuzhiyun 	clk_disable_unprepare(tsc->adc_clk);
348*4882a593Smuzhiyun 	return err;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
imx6ul_tsc_stop(struct imx6ul_tsc * tsc)351*4882a593Smuzhiyun static void imx6ul_tsc_stop(struct imx6ul_tsc *tsc)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	imx6ul_tsc_disable(tsc);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	clk_disable_unprepare(tsc->tsc_clk);
356*4882a593Smuzhiyun 	clk_disable_unprepare(tsc->adc_clk);
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 
imx6ul_tsc_open(struct input_dev * input_dev)360*4882a593Smuzhiyun static int imx6ul_tsc_open(struct input_dev *input_dev)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun 	struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	return imx6ul_tsc_start(tsc);
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun 
imx6ul_tsc_close(struct input_dev * input_dev)367*4882a593Smuzhiyun static void imx6ul_tsc_close(struct input_dev *input_dev)
368*4882a593Smuzhiyun {
369*4882a593Smuzhiyun 	struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	imx6ul_tsc_stop(tsc);
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun 
imx6ul_tsc_probe(struct platform_device * pdev)374*4882a593Smuzhiyun static int imx6ul_tsc_probe(struct platform_device *pdev)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun 	struct device_node *np = pdev->dev.of_node;
377*4882a593Smuzhiyun 	struct imx6ul_tsc *tsc;
378*4882a593Smuzhiyun 	struct input_dev *input_dev;
379*4882a593Smuzhiyun 	int err;
380*4882a593Smuzhiyun 	int tsc_irq;
381*4882a593Smuzhiyun 	int adc_irq;
382*4882a593Smuzhiyun 	u32 average_samples;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	tsc = devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL);
385*4882a593Smuzhiyun 	if (!tsc)
386*4882a593Smuzhiyun 		return -ENOMEM;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	input_dev = devm_input_allocate_device(&pdev->dev);
389*4882a593Smuzhiyun 	if (!input_dev)
390*4882a593Smuzhiyun 		return -ENOMEM;
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	input_dev->name = "iMX6UL Touchscreen Controller";
393*4882a593Smuzhiyun 	input_dev->id.bustype = BUS_HOST;
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	input_dev->open = imx6ul_tsc_open;
396*4882a593Smuzhiyun 	input_dev->close = imx6ul_tsc_close;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
399*4882a593Smuzhiyun 	input_set_abs_params(input_dev, ABS_X, 0, 0xFFF, 0, 0);
400*4882a593Smuzhiyun 	input_set_abs_params(input_dev, ABS_Y, 0, 0xFFF, 0, 0);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	input_set_drvdata(input_dev, tsc);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	tsc->dev = &pdev->dev;
405*4882a593Smuzhiyun 	tsc->input = input_dev;
406*4882a593Smuzhiyun 	init_completion(&tsc->completion);
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	tsc->xnur_gpio = devm_gpiod_get(&pdev->dev, "xnur", GPIOD_IN);
409*4882a593Smuzhiyun 	if (IS_ERR(tsc->xnur_gpio)) {
410*4882a593Smuzhiyun 		err = PTR_ERR(tsc->xnur_gpio);
411*4882a593Smuzhiyun 		dev_err(&pdev->dev,
412*4882a593Smuzhiyun 			"failed to request GPIO tsc_X- (xnur): %d\n", err);
413*4882a593Smuzhiyun 		return err;
414*4882a593Smuzhiyun 	}
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	tsc->tsc_regs = devm_platform_ioremap_resource(pdev, 0);
417*4882a593Smuzhiyun 	if (IS_ERR(tsc->tsc_regs)) {
418*4882a593Smuzhiyun 		err = PTR_ERR(tsc->tsc_regs);
419*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to remap tsc memory: %d\n", err);
420*4882a593Smuzhiyun 		return err;
421*4882a593Smuzhiyun 	}
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	tsc->adc_regs = devm_platform_ioremap_resource(pdev, 1);
424*4882a593Smuzhiyun 	if (IS_ERR(tsc->adc_regs)) {
425*4882a593Smuzhiyun 		err = PTR_ERR(tsc->adc_regs);
426*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to remap adc memory: %d\n", err);
427*4882a593Smuzhiyun 		return err;
428*4882a593Smuzhiyun 	}
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	tsc->tsc_clk = devm_clk_get(&pdev->dev, "tsc");
431*4882a593Smuzhiyun 	if (IS_ERR(tsc->tsc_clk)) {
432*4882a593Smuzhiyun 		err = PTR_ERR(tsc->tsc_clk);
433*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed getting tsc clock: %d\n", err);
434*4882a593Smuzhiyun 		return err;
435*4882a593Smuzhiyun 	}
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	tsc->adc_clk = devm_clk_get(&pdev->dev, "adc");
438*4882a593Smuzhiyun 	if (IS_ERR(tsc->adc_clk)) {
439*4882a593Smuzhiyun 		err = PTR_ERR(tsc->adc_clk);
440*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed getting adc clock: %d\n", err);
441*4882a593Smuzhiyun 		return err;
442*4882a593Smuzhiyun 	}
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	tsc_irq = platform_get_irq(pdev, 0);
445*4882a593Smuzhiyun 	if (tsc_irq < 0)
446*4882a593Smuzhiyun 		return tsc_irq;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	adc_irq = platform_get_irq(pdev, 1);
449*4882a593Smuzhiyun 	if (adc_irq < 0)
450*4882a593Smuzhiyun 		return adc_irq;
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	err = devm_request_threaded_irq(tsc->dev, tsc_irq,
453*4882a593Smuzhiyun 					NULL, tsc_irq_fn, IRQF_ONESHOT,
454*4882a593Smuzhiyun 					dev_name(&pdev->dev), tsc);
455*4882a593Smuzhiyun 	if (err) {
456*4882a593Smuzhiyun 		dev_err(&pdev->dev,
457*4882a593Smuzhiyun 			"failed requesting tsc irq %d: %d\n",
458*4882a593Smuzhiyun 			tsc_irq, err);
459*4882a593Smuzhiyun 		return err;
460*4882a593Smuzhiyun 	}
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	err = devm_request_irq(tsc->dev, adc_irq, adc_irq_fn, 0,
463*4882a593Smuzhiyun 				dev_name(&pdev->dev), tsc);
464*4882a593Smuzhiyun 	if (err) {
465*4882a593Smuzhiyun 		dev_err(&pdev->dev,
466*4882a593Smuzhiyun 			"failed requesting adc irq %d: %d\n",
467*4882a593Smuzhiyun 			adc_irq, err);
468*4882a593Smuzhiyun 		return err;
469*4882a593Smuzhiyun 	}
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	err = of_property_read_u32(np, "measure-delay-time",
472*4882a593Smuzhiyun 				   &tsc->measure_delay_time);
473*4882a593Smuzhiyun 	if (err)
474*4882a593Smuzhiyun 		tsc->measure_delay_time = 0xffff;
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	err = of_property_read_u32(np, "pre-charge-time",
477*4882a593Smuzhiyun 				   &tsc->pre_charge_time);
478*4882a593Smuzhiyun 	if (err)
479*4882a593Smuzhiyun 		tsc->pre_charge_time = 0xfff;
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	err = of_property_read_u32(np, "touchscreen-average-samples",
482*4882a593Smuzhiyun 				   &average_samples);
483*4882a593Smuzhiyun 	if (err)
484*4882a593Smuzhiyun 		average_samples = 1;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	switch (average_samples) {
487*4882a593Smuzhiyun 	case 1:
488*4882a593Smuzhiyun 		tsc->average_enable = false;
489*4882a593Smuzhiyun 		tsc->average_select = 0; /* value unused; initialize anyway */
490*4882a593Smuzhiyun 		break;
491*4882a593Smuzhiyun 	case 4:
492*4882a593Smuzhiyun 	case 8:
493*4882a593Smuzhiyun 	case 16:
494*4882a593Smuzhiyun 	case 32:
495*4882a593Smuzhiyun 		tsc->average_enable = true;
496*4882a593Smuzhiyun 		tsc->average_select = ilog2(average_samples) - 2;
497*4882a593Smuzhiyun 		break;
498*4882a593Smuzhiyun 	default:
499*4882a593Smuzhiyun 		dev_err(&pdev->dev,
500*4882a593Smuzhiyun 			"touchscreen-average-samples (%u) must be 1, 4, 8, 16 or 32\n",
501*4882a593Smuzhiyun 			average_samples);
502*4882a593Smuzhiyun 		return -EINVAL;
503*4882a593Smuzhiyun 	}
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	err = input_register_device(tsc->input);
506*4882a593Smuzhiyun 	if (err) {
507*4882a593Smuzhiyun 		dev_err(&pdev->dev,
508*4882a593Smuzhiyun 			"failed to register input device: %d\n", err);
509*4882a593Smuzhiyun 		return err;
510*4882a593Smuzhiyun 	}
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	platform_set_drvdata(pdev, tsc);
513*4882a593Smuzhiyun 	return 0;
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun 
imx6ul_tsc_suspend(struct device * dev)516*4882a593Smuzhiyun static int __maybe_unused imx6ul_tsc_suspend(struct device *dev)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
519*4882a593Smuzhiyun 	struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
520*4882a593Smuzhiyun 	struct input_dev *input_dev = tsc->input;
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	mutex_lock(&input_dev->mutex);
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	if (input_dev->users)
525*4882a593Smuzhiyun 		imx6ul_tsc_stop(tsc);
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	mutex_unlock(&input_dev->mutex);
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	return 0;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun 
imx6ul_tsc_resume(struct device * dev)532*4882a593Smuzhiyun static int __maybe_unused imx6ul_tsc_resume(struct device *dev)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
535*4882a593Smuzhiyun 	struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
536*4882a593Smuzhiyun 	struct input_dev *input_dev = tsc->input;
537*4882a593Smuzhiyun 	int retval = 0;
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	mutex_lock(&input_dev->mutex);
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	if (input_dev->users)
542*4882a593Smuzhiyun 		retval = imx6ul_tsc_start(tsc);
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	mutex_unlock(&input_dev->mutex);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	return retval;
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(imx6ul_tsc_pm_ops,
550*4882a593Smuzhiyun 			 imx6ul_tsc_suspend, imx6ul_tsc_resume);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun static const struct of_device_id imx6ul_tsc_match[] = {
553*4882a593Smuzhiyun 	{ .compatible = "fsl,imx6ul-tsc", },
554*4882a593Smuzhiyun 	{ /* sentinel */ }
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, imx6ul_tsc_match);
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun static struct platform_driver imx6ul_tsc_driver = {
559*4882a593Smuzhiyun 	.driver		= {
560*4882a593Smuzhiyun 		.name	= "imx6ul-tsc",
561*4882a593Smuzhiyun 		.of_match_table	= imx6ul_tsc_match,
562*4882a593Smuzhiyun 		.pm	= &imx6ul_tsc_pm_ops,
563*4882a593Smuzhiyun 	},
564*4882a593Smuzhiyun 	.probe		= imx6ul_tsc_probe,
565*4882a593Smuzhiyun };
566*4882a593Smuzhiyun module_platform_driver(imx6ul_tsc_driver);
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
569*4882a593Smuzhiyun MODULE_DESCRIPTION("Freescale i.MX6UL Touchscreen controller driver");
570*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
571