1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Broadcom Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
6*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
10*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11*4882a593Smuzhiyun * GNU General Public License for more details.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/input.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/keyboard.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/of.h>
22*4882a593Smuzhiyun #include <asm/irq.h>
23*4882a593Smuzhiyun #include <linux/io.h>
24*4882a593Smuzhiyun #include <linux/clk.h>
25*4882a593Smuzhiyun #include <linux/serio.h>
26*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
27*4882a593Smuzhiyun #include <linux/regmap.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define IPROC_TS_NAME "iproc-ts"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define PEN_DOWN_STATUS 1
32*4882a593Smuzhiyun #define PEN_UP_STATUS 0
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define X_MIN 0
35*4882a593Smuzhiyun #define Y_MIN 0
36*4882a593Smuzhiyun #define X_MAX 0xFFF
37*4882a593Smuzhiyun #define Y_MAX 0xFFF
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Value given by controller for invalid coordinate. */
40*4882a593Smuzhiyun #define INVALID_COORD 0xFFFFFFFF
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Register offsets */
43*4882a593Smuzhiyun #define REGCTL1 0x00
44*4882a593Smuzhiyun #define REGCTL2 0x04
45*4882a593Smuzhiyun #define INTERRUPT_THRES 0x08
46*4882a593Smuzhiyun #define INTERRUPT_MASK 0x0c
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define INTERRUPT_STATUS 0x10
49*4882a593Smuzhiyun #define CONTROLLER_STATUS 0x14
50*4882a593Smuzhiyun #define FIFO_DATA 0x18
51*4882a593Smuzhiyun #define FIFO_DATA_X_Y_MASK 0xFFFF
52*4882a593Smuzhiyun #define ANALOG_CONTROL 0x1c
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define AUX_DATA 0x20
55*4882a593Smuzhiyun #define DEBOUNCE_CNTR_STAT 0x24
56*4882a593Smuzhiyun #define SCAN_CNTR_STAT 0x28
57*4882a593Smuzhiyun #define REM_CNTR_STAT 0x2c
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define SETTLING_TIMER_STAT 0x30
60*4882a593Smuzhiyun #define SPARE_REG 0x34
61*4882a593Smuzhiyun #define SOFT_BYPASS_CONTROL 0x38
62*4882a593Smuzhiyun #define SOFT_BYPASS_DATA 0x3c
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Bit values for INTERRUPT_MASK and INTERRUPT_STATUS regs */
66*4882a593Smuzhiyun #define TS_PEN_INTR_MASK BIT(0)
67*4882a593Smuzhiyun #define TS_FIFO_INTR_MASK BIT(2)
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Bit values for CONTROLLER_STATUS reg1 */
70*4882a593Smuzhiyun #define TS_PEN_DOWN BIT(0)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Shift values for control reg1 */
73*4882a593Smuzhiyun #define SCANNING_PERIOD_SHIFT 24
74*4882a593Smuzhiyun #define DEBOUNCE_TIMEOUT_SHIFT 16
75*4882a593Smuzhiyun #define SETTLING_TIMEOUT_SHIFT 8
76*4882a593Smuzhiyun #define TOUCH_TIMEOUT_SHIFT 0
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Shift values for coordinates from fifo */
79*4882a593Smuzhiyun #define X_COORD_SHIFT 0
80*4882a593Smuzhiyun #define Y_COORD_SHIFT 16
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Bit values for REGCTL2 */
83*4882a593Smuzhiyun #define TS_CONTROLLER_EN_BIT BIT(16)
84*4882a593Smuzhiyun #define TS_CONTROLLER_AVGDATA_SHIFT 8
85*4882a593Smuzhiyun #define TS_CONTROLLER_AVGDATA_MASK (0x7 << TS_CONTROLLER_AVGDATA_SHIFT)
86*4882a593Smuzhiyun #define TS_CONTROLLER_PWR_LDO BIT(5)
87*4882a593Smuzhiyun #define TS_CONTROLLER_PWR_ADC BIT(4)
88*4882a593Smuzhiyun #define TS_CONTROLLER_PWR_BGP BIT(3)
89*4882a593Smuzhiyun #define TS_CONTROLLER_PWR_TS BIT(2)
90*4882a593Smuzhiyun #define TS_WIRE_MODE_BIT BIT(1)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define dbg_reg(dev, priv, reg) \
93*4882a593Smuzhiyun do { \
94*4882a593Smuzhiyun u32 val; \
95*4882a593Smuzhiyun regmap_read(priv->regmap, reg, &val); \
96*4882a593Smuzhiyun dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \
97*4882a593Smuzhiyun } while (0)
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct tsc_param {
100*4882a593Smuzhiyun /* Each step is 1024 us. Valid 1-256 */
101*4882a593Smuzhiyun u32 scanning_period;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Each step is 512 us. Valid 0-255 */
104*4882a593Smuzhiyun u32 debounce_timeout;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /*
107*4882a593Smuzhiyun * The settling duration (in ms) is the amount of time the tsc
108*4882a593Smuzhiyun * waits to allow the voltage to settle after turning on the
109*4882a593Smuzhiyun * drivers in detection mode. Valid values: 0-11
110*4882a593Smuzhiyun * 0 = 0.008 ms
111*4882a593Smuzhiyun * 1 = 0.01 ms
112*4882a593Smuzhiyun * 2 = 0.02 ms
113*4882a593Smuzhiyun * 3 = 0.04 ms
114*4882a593Smuzhiyun * 4 = 0.08 ms
115*4882a593Smuzhiyun * 5 = 0.16 ms
116*4882a593Smuzhiyun * 6 = 0.32 ms
117*4882a593Smuzhiyun * 7 = 0.64 ms
118*4882a593Smuzhiyun * 8 = 1.28 ms
119*4882a593Smuzhiyun * 9 = 2.56 ms
120*4882a593Smuzhiyun * 10 = 5.12 ms
121*4882a593Smuzhiyun * 11 = 10.24 ms
122*4882a593Smuzhiyun */
123*4882a593Smuzhiyun u32 settling_timeout;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* touch timeout in sample counts */
126*4882a593Smuzhiyun u32 touch_timeout;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /*
129*4882a593Smuzhiyun * Number of data samples which are averaged before a final data point
130*4882a593Smuzhiyun * is placed into the FIFO
131*4882a593Smuzhiyun */
132*4882a593Smuzhiyun u32 average_data;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* FIFO threshold */
135*4882a593Smuzhiyun u32 fifo_threshold;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Optional standard touchscreen properties. */
138*4882a593Smuzhiyun u32 max_x;
139*4882a593Smuzhiyun u32 max_y;
140*4882a593Smuzhiyun u32 fuzz_x;
141*4882a593Smuzhiyun u32 fuzz_y;
142*4882a593Smuzhiyun bool invert_x;
143*4882a593Smuzhiyun bool invert_y;
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun struct iproc_ts_priv {
147*4882a593Smuzhiyun struct platform_device *pdev;
148*4882a593Smuzhiyun struct input_dev *idev;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun struct regmap *regmap;
151*4882a593Smuzhiyun struct clk *tsc_clk;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun int pen_status;
154*4882a593Smuzhiyun struct tsc_param cfg_params;
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /*
158*4882a593Smuzhiyun * Set default values the same as hardware reset values
159*4882a593Smuzhiyun * except for fifo_threshold with is set to 1.
160*4882a593Smuzhiyun */
161*4882a593Smuzhiyun static const struct tsc_param iproc_default_config = {
162*4882a593Smuzhiyun .scanning_period = 0x5, /* 1 to 256 */
163*4882a593Smuzhiyun .debounce_timeout = 0x28, /* 0 to 255 */
164*4882a593Smuzhiyun .settling_timeout = 0x7, /* 0 to 11 */
165*4882a593Smuzhiyun .touch_timeout = 0xa, /* 0 to 255 */
166*4882a593Smuzhiyun .average_data = 5, /* entry 5 = 32 pts */
167*4882a593Smuzhiyun .fifo_threshold = 1, /* 0 to 31 */
168*4882a593Smuzhiyun .max_x = X_MAX,
169*4882a593Smuzhiyun .max_y = Y_MAX,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun
ts_reg_dump(struct iproc_ts_priv * priv)172*4882a593Smuzhiyun static void ts_reg_dump(struct iproc_ts_priv *priv)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun struct device *dev = &priv->pdev->dev;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun dbg_reg(dev, priv, REGCTL1);
177*4882a593Smuzhiyun dbg_reg(dev, priv, REGCTL2);
178*4882a593Smuzhiyun dbg_reg(dev, priv, INTERRUPT_THRES);
179*4882a593Smuzhiyun dbg_reg(dev, priv, INTERRUPT_MASK);
180*4882a593Smuzhiyun dbg_reg(dev, priv, INTERRUPT_STATUS);
181*4882a593Smuzhiyun dbg_reg(dev, priv, CONTROLLER_STATUS);
182*4882a593Smuzhiyun dbg_reg(dev, priv, FIFO_DATA);
183*4882a593Smuzhiyun dbg_reg(dev, priv, ANALOG_CONTROL);
184*4882a593Smuzhiyun dbg_reg(dev, priv, AUX_DATA);
185*4882a593Smuzhiyun dbg_reg(dev, priv, DEBOUNCE_CNTR_STAT);
186*4882a593Smuzhiyun dbg_reg(dev, priv, SCAN_CNTR_STAT);
187*4882a593Smuzhiyun dbg_reg(dev, priv, REM_CNTR_STAT);
188*4882a593Smuzhiyun dbg_reg(dev, priv, SETTLING_TIMER_STAT);
189*4882a593Smuzhiyun dbg_reg(dev, priv, SPARE_REG);
190*4882a593Smuzhiyun dbg_reg(dev, priv, SOFT_BYPASS_CONTROL);
191*4882a593Smuzhiyun dbg_reg(dev, priv, SOFT_BYPASS_DATA);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
iproc_touchscreen_interrupt(int irq,void * data)194*4882a593Smuzhiyun static irqreturn_t iproc_touchscreen_interrupt(int irq, void *data)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun struct platform_device *pdev = data;
197*4882a593Smuzhiyun struct iproc_ts_priv *priv = platform_get_drvdata(pdev);
198*4882a593Smuzhiyun u32 intr_status;
199*4882a593Smuzhiyun u32 raw_coordinate;
200*4882a593Smuzhiyun u16 x;
201*4882a593Smuzhiyun u16 y;
202*4882a593Smuzhiyun int i;
203*4882a593Smuzhiyun bool needs_sync = false;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun regmap_read(priv->regmap, INTERRUPT_STATUS, &intr_status);
206*4882a593Smuzhiyun intr_status &= TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK;
207*4882a593Smuzhiyun if (intr_status == 0)
208*4882a593Smuzhiyun return IRQ_NONE;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /* Clear all interrupt status bits, write-1-clear */
211*4882a593Smuzhiyun regmap_write(priv->regmap, INTERRUPT_STATUS, intr_status);
212*4882a593Smuzhiyun /* Pen up/down */
213*4882a593Smuzhiyun if (intr_status & TS_PEN_INTR_MASK) {
214*4882a593Smuzhiyun regmap_read(priv->regmap, CONTROLLER_STATUS, &priv->pen_status);
215*4882a593Smuzhiyun if (priv->pen_status & TS_PEN_DOWN)
216*4882a593Smuzhiyun priv->pen_status = PEN_DOWN_STATUS;
217*4882a593Smuzhiyun else
218*4882a593Smuzhiyun priv->pen_status = PEN_UP_STATUS;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun input_report_key(priv->idev, BTN_TOUCH, priv->pen_status);
221*4882a593Smuzhiyun needs_sync = true;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun dev_dbg(&priv->pdev->dev,
224*4882a593Smuzhiyun "pen up-down (%d)\n", priv->pen_status);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun /* coordinates in FIFO exceed the theshold */
228*4882a593Smuzhiyun if (intr_status & TS_FIFO_INTR_MASK) {
229*4882a593Smuzhiyun for (i = 0; i < priv->cfg_params.fifo_threshold; i++) {
230*4882a593Smuzhiyun regmap_read(priv->regmap, FIFO_DATA, &raw_coordinate);
231*4882a593Smuzhiyun if (raw_coordinate == INVALID_COORD)
232*4882a593Smuzhiyun continue;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /*
235*4882a593Smuzhiyun * The x and y coordinate are 16 bits each
236*4882a593Smuzhiyun * with the x in the lower 16 bits and y in the
237*4882a593Smuzhiyun * upper 16 bits.
238*4882a593Smuzhiyun */
239*4882a593Smuzhiyun x = (raw_coordinate >> X_COORD_SHIFT) &
240*4882a593Smuzhiyun FIFO_DATA_X_Y_MASK;
241*4882a593Smuzhiyun y = (raw_coordinate >> Y_COORD_SHIFT) &
242*4882a593Smuzhiyun FIFO_DATA_X_Y_MASK;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* We only want to retain the 12 msb of the 16 */
245*4882a593Smuzhiyun x = (x >> 4) & 0x0FFF;
246*4882a593Smuzhiyun y = (y >> 4) & 0x0FFF;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* Adjust x y according to LCD tsc mount angle. */
249*4882a593Smuzhiyun if (priv->cfg_params.invert_x)
250*4882a593Smuzhiyun x = priv->cfg_params.max_x - x;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun if (priv->cfg_params.invert_y)
253*4882a593Smuzhiyun y = priv->cfg_params.max_y - y;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun input_report_abs(priv->idev, ABS_X, x);
256*4882a593Smuzhiyun input_report_abs(priv->idev, ABS_Y, y);
257*4882a593Smuzhiyun needs_sync = true;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun dev_dbg(&priv->pdev->dev, "xy (0x%x 0x%x)\n", x, y);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun if (needs_sync)
264*4882a593Smuzhiyun input_sync(priv->idev);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun return IRQ_HANDLED;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
iproc_ts_start(struct input_dev * idev)269*4882a593Smuzhiyun static int iproc_ts_start(struct input_dev *idev)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun u32 val;
272*4882a593Smuzhiyun u32 mask;
273*4882a593Smuzhiyun int error;
274*4882a593Smuzhiyun struct iproc_ts_priv *priv = input_get_drvdata(idev);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun /* Enable clock */
277*4882a593Smuzhiyun error = clk_prepare_enable(priv->tsc_clk);
278*4882a593Smuzhiyun if (error) {
279*4882a593Smuzhiyun dev_err(&priv->pdev->dev, "%s clk_prepare_enable failed %d\n",
280*4882a593Smuzhiyun __func__, error);
281*4882a593Smuzhiyun return error;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /*
285*4882a593Smuzhiyun * Interrupt is generated when:
286*4882a593Smuzhiyun * FIFO reaches the int_th value, and pen event(up/down)
287*4882a593Smuzhiyun */
288*4882a593Smuzhiyun val = TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK;
289*4882a593Smuzhiyun regmap_update_bits(priv->regmap, INTERRUPT_MASK, val, val);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun val = priv->cfg_params.fifo_threshold;
292*4882a593Smuzhiyun regmap_write(priv->regmap, INTERRUPT_THRES, val);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* Initialize control reg1 */
295*4882a593Smuzhiyun val = 0;
296*4882a593Smuzhiyun val |= priv->cfg_params.scanning_period << SCANNING_PERIOD_SHIFT;
297*4882a593Smuzhiyun val |= priv->cfg_params.debounce_timeout << DEBOUNCE_TIMEOUT_SHIFT;
298*4882a593Smuzhiyun val |= priv->cfg_params.settling_timeout << SETTLING_TIMEOUT_SHIFT;
299*4882a593Smuzhiyun val |= priv->cfg_params.touch_timeout << TOUCH_TIMEOUT_SHIFT;
300*4882a593Smuzhiyun regmap_write(priv->regmap, REGCTL1, val);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /* Try to clear all interrupt status */
303*4882a593Smuzhiyun val = TS_FIFO_INTR_MASK | TS_PEN_INTR_MASK;
304*4882a593Smuzhiyun regmap_update_bits(priv->regmap, INTERRUPT_STATUS, val, val);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /* Initialize control reg2 */
307*4882a593Smuzhiyun val = TS_CONTROLLER_EN_BIT | TS_WIRE_MODE_BIT;
308*4882a593Smuzhiyun val |= priv->cfg_params.average_data << TS_CONTROLLER_AVGDATA_SHIFT;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun mask = (TS_CONTROLLER_AVGDATA_MASK);
311*4882a593Smuzhiyun mask |= (TS_CONTROLLER_PWR_LDO | /* PWR up LDO */
312*4882a593Smuzhiyun TS_CONTROLLER_PWR_ADC | /* PWR up ADC */
313*4882a593Smuzhiyun TS_CONTROLLER_PWR_BGP | /* PWR up BGP */
314*4882a593Smuzhiyun TS_CONTROLLER_PWR_TS); /* PWR up TS */
315*4882a593Smuzhiyun mask |= val;
316*4882a593Smuzhiyun regmap_update_bits(priv->regmap, REGCTL2, mask, val);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun ts_reg_dump(priv);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun return 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
iproc_ts_stop(struct input_dev * dev)323*4882a593Smuzhiyun static void iproc_ts_stop(struct input_dev *dev)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun u32 val;
326*4882a593Smuzhiyun struct iproc_ts_priv *priv = input_get_drvdata(dev);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun /*
329*4882a593Smuzhiyun * Disable FIFO int_th and pen event(up/down)Interrupts only
330*4882a593Smuzhiyun * as the interrupt mask register is shared between ADC, TS and
331*4882a593Smuzhiyun * flextimer.
332*4882a593Smuzhiyun */
333*4882a593Smuzhiyun val = TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK;
334*4882a593Smuzhiyun regmap_update_bits(priv->regmap, INTERRUPT_MASK, val, 0);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /* Only power down touch screen controller */
337*4882a593Smuzhiyun val = TS_CONTROLLER_PWR_TS;
338*4882a593Smuzhiyun regmap_update_bits(priv->regmap, REGCTL2, val, val);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun clk_disable(priv->tsc_clk);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
iproc_get_tsc_config(struct device * dev,struct iproc_ts_priv * priv)343*4882a593Smuzhiyun static int iproc_get_tsc_config(struct device *dev, struct iproc_ts_priv *priv)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun struct device_node *np = dev->of_node;
346*4882a593Smuzhiyun u32 val;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun priv->cfg_params = iproc_default_config;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun if (!np)
351*4882a593Smuzhiyun return 0;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun if (of_property_read_u32(np, "scanning_period", &val) >= 0) {
354*4882a593Smuzhiyun if (val < 1 || val > 256) {
355*4882a593Smuzhiyun dev_err(dev, "scanning_period (%u) must be [1-256]\n",
356*4882a593Smuzhiyun val);
357*4882a593Smuzhiyun return -EINVAL;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun priv->cfg_params.scanning_period = val;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun if (of_property_read_u32(np, "debounce_timeout", &val) >= 0) {
363*4882a593Smuzhiyun if (val > 255) {
364*4882a593Smuzhiyun dev_err(dev, "debounce_timeout (%u) must be [0-255]\n",
365*4882a593Smuzhiyun val);
366*4882a593Smuzhiyun return -EINVAL;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun priv->cfg_params.debounce_timeout = val;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun if (of_property_read_u32(np, "settling_timeout", &val) >= 0) {
372*4882a593Smuzhiyun if (val > 11) {
373*4882a593Smuzhiyun dev_err(dev, "settling_timeout (%u) must be [0-11]\n",
374*4882a593Smuzhiyun val);
375*4882a593Smuzhiyun return -EINVAL;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun priv->cfg_params.settling_timeout = val;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun if (of_property_read_u32(np, "touch_timeout", &val) >= 0) {
381*4882a593Smuzhiyun if (val > 255) {
382*4882a593Smuzhiyun dev_err(dev, "touch_timeout (%u) must be [0-255]\n",
383*4882a593Smuzhiyun val);
384*4882a593Smuzhiyun return -EINVAL;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun priv->cfg_params.touch_timeout = val;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun if (of_property_read_u32(np, "average_data", &val) >= 0) {
390*4882a593Smuzhiyun if (val > 8) {
391*4882a593Smuzhiyun dev_err(dev, "average_data (%u) must be [0-8]\n", val);
392*4882a593Smuzhiyun return -EINVAL;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun priv->cfg_params.average_data = val;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun if (of_property_read_u32(np, "fifo_threshold", &val) >= 0) {
398*4882a593Smuzhiyun if (val > 31) {
399*4882a593Smuzhiyun dev_err(dev, "fifo_threshold (%u)) must be [0-31]\n",
400*4882a593Smuzhiyun val);
401*4882a593Smuzhiyun return -EINVAL;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun priv->cfg_params.fifo_threshold = val;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun /* Parse optional properties. */
407*4882a593Smuzhiyun of_property_read_u32(np, "touchscreen-size-x", &priv->cfg_params.max_x);
408*4882a593Smuzhiyun of_property_read_u32(np, "touchscreen-size-y", &priv->cfg_params.max_y);
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun of_property_read_u32(np, "touchscreen-fuzz-x",
411*4882a593Smuzhiyun &priv->cfg_params.fuzz_x);
412*4882a593Smuzhiyun of_property_read_u32(np, "touchscreen-fuzz-y",
413*4882a593Smuzhiyun &priv->cfg_params.fuzz_y);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun priv->cfg_params.invert_x =
416*4882a593Smuzhiyun of_property_read_bool(np, "touchscreen-inverted-x");
417*4882a593Smuzhiyun priv->cfg_params.invert_y =
418*4882a593Smuzhiyun of_property_read_bool(np, "touchscreen-inverted-y");
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun return 0;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
iproc_ts_probe(struct platform_device * pdev)423*4882a593Smuzhiyun static int iproc_ts_probe(struct platform_device *pdev)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun struct iproc_ts_priv *priv;
426*4882a593Smuzhiyun struct input_dev *idev;
427*4882a593Smuzhiyun int irq;
428*4882a593Smuzhiyun int error;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
431*4882a593Smuzhiyun if (!priv)
432*4882a593Smuzhiyun return -ENOMEM;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun /* touchscreen controller memory mapped regs via syscon*/
435*4882a593Smuzhiyun priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
436*4882a593Smuzhiyun "ts_syscon");
437*4882a593Smuzhiyun if (IS_ERR(priv->regmap)) {
438*4882a593Smuzhiyun error = PTR_ERR(priv->regmap);
439*4882a593Smuzhiyun dev_err(&pdev->dev, "unable to map I/O memory:%d\n", error);
440*4882a593Smuzhiyun return error;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun priv->tsc_clk = devm_clk_get(&pdev->dev, "tsc_clk");
444*4882a593Smuzhiyun if (IS_ERR(priv->tsc_clk)) {
445*4882a593Smuzhiyun error = PTR_ERR(priv->tsc_clk);
446*4882a593Smuzhiyun dev_err(&pdev->dev,
447*4882a593Smuzhiyun "failed getting clock tsc_clk: %d\n", error);
448*4882a593Smuzhiyun return error;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun priv->pdev = pdev;
452*4882a593Smuzhiyun error = iproc_get_tsc_config(&pdev->dev, priv);
453*4882a593Smuzhiyun if (error) {
454*4882a593Smuzhiyun dev_err(&pdev->dev, "get_tsc_config failed: %d\n", error);
455*4882a593Smuzhiyun return error;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun idev = devm_input_allocate_device(&pdev->dev);
459*4882a593Smuzhiyun if (!idev) {
460*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to allocate input device\n");
461*4882a593Smuzhiyun return -ENOMEM;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun priv->idev = idev;
465*4882a593Smuzhiyun priv->pen_status = PEN_UP_STATUS;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun /* Set input device info */
468*4882a593Smuzhiyun idev->name = IPROC_TS_NAME;
469*4882a593Smuzhiyun idev->dev.parent = &pdev->dev;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun idev->id.bustype = BUS_HOST;
472*4882a593Smuzhiyun idev->id.vendor = SERIO_UNKNOWN;
473*4882a593Smuzhiyun idev->id.product = 0;
474*4882a593Smuzhiyun idev->id.version = 0;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun idev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
477*4882a593Smuzhiyun __set_bit(BTN_TOUCH, idev->keybit);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun input_set_abs_params(idev, ABS_X, X_MIN, priv->cfg_params.max_x,
480*4882a593Smuzhiyun priv->cfg_params.fuzz_x, 0);
481*4882a593Smuzhiyun input_set_abs_params(idev, ABS_Y, Y_MIN, priv->cfg_params.max_y,
482*4882a593Smuzhiyun priv->cfg_params.fuzz_y, 0);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun idev->open = iproc_ts_start;
485*4882a593Smuzhiyun idev->close = iproc_ts_stop;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun input_set_drvdata(idev, priv);
488*4882a593Smuzhiyun platform_set_drvdata(pdev, priv);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun /* get interrupt */
491*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
492*4882a593Smuzhiyun if (irq < 0)
493*4882a593Smuzhiyun return irq;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun error = devm_request_irq(&pdev->dev, irq,
496*4882a593Smuzhiyun iproc_touchscreen_interrupt,
497*4882a593Smuzhiyun IRQF_SHARED, IPROC_TS_NAME, pdev);
498*4882a593Smuzhiyun if (error)
499*4882a593Smuzhiyun return error;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun error = input_register_device(priv->idev);
502*4882a593Smuzhiyun if (error) {
503*4882a593Smuzhiyun dev_err(&pdev->dev,
504*4882a593Smuzhiyun "failed to register input device: %d\n", error);
505*4882a593Smuzhiyun return error;
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun return 0;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun static const struct of_device_id iproc_ts_of_match[] = {
512*4882a593Smuzhiyun {.compatible = "brcm,iproc-touchscreen", },
513*4882a593Smuzhiyun { },
514*4882a593Smuzhiyun };
515*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, iproc_ts_of_match);
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun static struct platform_driver iproc_ts_driver = {
518*4882a593Smuzhiyun .probe = iproc_ts_probe,
519*4882a593Smuzhiyun .driver = {
520*4882a593Smuzhiyun .name = IPROC_TS_NAME,
521*4882a593Smuzhiyun .of_match_table = of_match_ptr(iproc_ts_of_match),
522*4882a593Smuzhiyun },
523*4882a593Smuzhiyun };
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun module_platform_driver(iproc_ts_driver);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun MODULE_DESCRIPTION("IPROC Touchscreen driver");
528*4882a593Smuzhiyun MODULE_AUTHOR("Broadcom");
529*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
530