xref: /OK3568_Linux_fs/kernel/drivers/input/serio/maceps2.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * SGI O2 MACE PS2 controller driver for linux
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2002 Vivien Chappelier
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/serio.h>
10*4882a593Smuzhiyun #include <linux/errno.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/ioport.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/spinlock.h>
17*4882a593Smuzhiyun #include <linux/err.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <asm/io.h>
20*4882a593Smuzhiyun #include <asm/irq.h>
21*4882a593Smuzhiyun #include <asm/ip32/mace.h>
22*4882a593Smuzhiyun #include <asm/ip32/ip32_ints.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun MODULE_AUTHOR("Vivien Chappelier <vivien.chappelier@linux-mips.org");
25*4882a593Smuzhiyun MODULE_DESCRIPTION("SGI O2 MACE PS2 controller driver");
26*4882a593Smuzhiyun MODULE_LICENSE("GPL");
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define MACE_PS2_TIMEOUT 10000 /* in 50us unit */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define PS2_STATUS_CLOCK_SIGNAL  BIT(0) /* external clock signal */
31*4882a593Smuzhiyun #define PS2_STATUS_CLOCK_INHIBIT BIT(1) /* clken output signal */
32*4882a593Smuzhiyun #define PS2_STATUS_TX_INPROGRESS BIT(2) /* transmission in progress */
33*4882a593Smuzhiyun #define PS2_STATUS_TX_EMPTY      BIT(3) /* empty transmit buffer */
34*4882a593Smuzhiyun #define PS2_STATUS_RX_FULL       BIT(4) /* full receive buffer */
35*4882a593Smuzhiyun #define PS2_STATUS_RX_INPROGRESS BIT(5) /* reception in progress */
36*4882a593Smuzhiyun #define PS2_STATUS_ERROR_PARITY  BIT(6) /* parity error */
37*4882a593Smuzhiyun #define PS2_STATUS_ERROR_FRAMING BIT(7) /* framing error */
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define PS2_CONTROL_TX_CLOCK_DISABLE BIT(0) /* inhibit clock signal after TX */
40*4882a593Smuzhiyun #define PS2_CONTROL_TX_ENABLE        BIT(1) /* transmit enable */
41*4882a593Smuzhiyun #define PS2_CONTROL_TX_INT_ENABLE    BIT(2) /* enable transmit interrupt */
42*4882a593Smuzhiyun #define PS2_CONTROL_RX_INT_ENABLE    BIT(3) /* enable receive interrupt */
43*4882a593Smuzhiyun #define PS2_CONTROL_RX_CLOCK_ENABLE  BIT(4) /* pause reception if set to 0 */
44*4882a593Smuzhiyun #define PS2_CONTROL_RESET            BIT(5) /* reset */
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun struct maceps2_data {
47*4882a593Smuzhiyun 	struct mace_ps2port *port;
48*4882a593Smuzhiyun 	int irq;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun static struct maceps2_data port_data[2];
52*4882a593Smuzhiyun static struct serio *maceps2_port[2];
53*4882a593Smuzhiyun static struct platform_device *maceps2_device;
54*4882a593Smuzhiyun 
maceps2_write(struct serio * dev,unsigned char val)55*4882a593Smuzhiyun static int maceps2_write(struct serio *dev, unsigned char val)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	struct mace_ps2port *port = ((struct maceps2_data *)dev->port_data)->port;
58*4882a593Smuzhiyun 	unsigned int timeout = MACE_PS2_TIMEOUT;
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	do {
61*4882a593Smuzhiyun 		if (port->status & PS2_STATUS_TX_EMPTY) {
62*4882a593Smuzhiyun 			port->tx = val;
63*4882a593Smuzhiyun 			return 0;
64*4882a593Smuzhiyun 		}
65*4882a593Smuzhiyun 		udelay(50);
66*4882a593Smuzhiyun 	} while (timeout--);
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	return -1;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
maceps2_interrupt(int irq,void * dev_id)71*4882a593Smuzhiyun static irqreturn_t maceps2_interrupt(int irq, void *dev_id)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	struct serio *dev = dev_id;
74*4882a593Smuzhiyun 	struct mace_ps2port *port = ((struct maceps2_data *)dev->port_data)->port;
75*4882a593Smuzhiyun 	unsigned long byte;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	if (port->status & PS2_STATUS_RX_FULL) {
78*4882a593Smuzhiyun 		byte = port->rx;
79*4882a593Smuzhiyun 		serio_interrupt(dev, byte & 0xff, 0);
80*4882a593Smuzhiyun         }
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	return IRQ_HANDLED;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
maceps2_open(struct serio * dev)85*4882a593Smuzhiyun static int maceps2_open(struct serio *dev)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	struct maceps2_data *data = (struct maceps2_data *)dev->port_data;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	if (request_irq(data->irq, maceps2_interrupt, 0, "PS2 port", dev)) {
90*4882a593Smuzhiyun 		printk(KERN_ERR "Could not allocate PS/2 IRQ\n");
91*4882a593Smuzhiyun 		return -EBUSY;
92*4882a593Smuzhiyun 	}
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	/* Reset port */
95*4882a593Smuzhiyun 	data->port->control = PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET;
96*4882a593Smuzhiyun 	udelay(100);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun         /* Enable interrupts */
99*4882a593Smuzhiyun 	data->port->control = PS2_CONTROL_RX_CLOCK_ENABLE |
100*4882a593Smuzhiyun 			      PS2_CONTROL_TX_ENABLE |
101*4882a593Smuzhiyun 			      PS2_CONTROL_RX_INT_ENABLE;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
maceps2_close(struct serio * dev)106*4882a593Smuzhiyun static void maceps2_close(struct serio *dev)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	struct maceps2_data *data = (struct maceps2_data *)dev->port_data;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	data->port->control = PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET;
111*4882a593Smuzhiyun 	udelay(100);
112*4882a593Smuzhiyun 	free_irq(data->irq, dev);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 
maceps2_allocate_port(int idx)116*4882a593Smuzhiyun static struct serio *maceps2_allocate_port(int idx)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct serio *serio;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
121*4882a593Smuzhiyun 	if (serio) {
122*4882a593Smuzhiyun 		serio->id.type		= SERIO_8042;
123*4882a593Smuzhiyun 		serio->write		= maceps2_write;
124*4882a593Smuzhiyun 		serio->open		= maceps2_open;
125*4882a593Smuzhiyun 		serio->close		= maceps2_close;
126*4882a593Smuzhiyun 		snprintf(serio->name, sizeof(serio->name), "MACE PS/2 port%d", idx);
127*4882a593Smuzhiyun 		snprintf(serio->phys, sizeof(serio->phys), "mace/serio%d", idx);
128*4882a593Smuzhiyun 		serio->port_data	= &port_data[idx];
129*4882a593Smuzhiyun 		serio->dev.parent	= &maceps2_device->dev;
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	return serio;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
maceps2_probe(struct platform_device * dev)135*4882a593Smuzhiyun static int maceps2_probe(struct platform_device *dev)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	maceps2_port[0] = maceps2_allocate_port(0);
138*4882a593Smuzhiyun 	maceps2_port[1] = maceps2_allocate_port(1);
139*4882a593Smuzhiyun 	if (!maceps2_port[0] || !maceps2_port[1]) {
140*4882a593Smuzhiyun 		kfree(maceps2_port[0]);
141*4882a593Smuzhiyun 		kfree(maceps2_port[1]);
142*4882a593Smuzhiyun 		return -ENOMEM;
143*4882a593Smuzhiyun 	}
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	serio_register_port(maceps2_port[0]);
146*4882a593Smuzhiyun 	serio_register_port(maceps2_port[1]);
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
maceps2_remove(struct platform_device * dev)151*4882a593Smuzhiyun static int maceps2_remove(struct platform_device *dev)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	serio_unregister_port(maceps2_port[0]);
154*4882a593Smuzhiyun 	serio_unregister_port(maceps2_port[1]);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static struct platform_driver maceps2_driver = {
160*4882a593Smuzhiyun 	.driver		= {
161*4882a593Smuzhiyun 		.name	= "maceps2",
162*4882a593Smuzhiyun 	},
163*4882a593Smuzhiyun 	.probe		= maceps2_probe,
164*4882a593Smuzhiyun 	.remove		= maceps2_remove,
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
maceps2_init(void)167*4882a593Smuzhiyun static int __init maceps2_init(void)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 	int error;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	error = platform_driver_register(&maceps2_driver);
172*4882a593Smuzhiyun 	if (error)
173*4882a593Smuzhiyun 		return error;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	maceps2_device = platform_device_alloc("maceps2", -1);
176*4882a593Smuzhiyun 	if (!maceps2_device) {
177*4882a593Smuzhiyun 		error = -ENOMEM;
178*4882a593Smuzhiyun 		goto err_unregister_driver;
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	port_data[0].port = &mace->perif.ps2.keyb;
182*4882a593Smuzhiyun 	port_data[0].irq  = MACEISA_KEYB_IRQ;
183*4882a593Smuzhiyun 	port_data[1].port = &mace->perif.ps2.mouse;
184*4882a593Smuzhiyun 	port_data[1].irq  = MACEISA_MOUSE_IRQ;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	error = platform_device_add(maceps2_device);
187*4882a593Smuzhiyun 	if (error)
188*4882a593Smuzhiyun 		goto err_free_device;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	return 0;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun  err_free_device:
193*4882a593Smuzhiyun 	platform_device_put(maceps2_device);
194*4882a593Smuzhiyun  err_unregister_driver:
195*4882a593Smuzhiyun 	platform_driver_unregister(&maceps2_driver);
196*4882a593Smuzhiyun 	return error;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
maceps2_exit(void)199*4882a593Smuzhiyun static void __exit maceps2_exit(void)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun 	platform_device_unregister(maceps2_device);
202*4882a593Smuzhiyun 	platform_driver_unregister(&maceps2_driver);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun module_init(maceps2_init);
206*4882a593Smuzhiyun module_exit(maceps2_exit);
207