1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2012-2015 Synaptics Incorporated
4*4882a593Smuzhiyun * Copyright (C) 2016 Zodiac Inflight Innovations
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/rmi.h>
9*4882a593Smuzhiyun #include <linux/input.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <media/v4l2-device.h>
14*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
15*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
16*4882a593Smuzhiyun #include <media/videobuf2-vmalloc.h>
17*4882a593Smuzhiyun #include "rmi_driver.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define F54_NAME "rmi4_f54"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* F54 data offsets */
22*4882a593Smuzhiyun #define F54_REPORT_DATA_OFFSET 3
23*4882a593Smuzhiyun #define F54_FIFO_OFFSET 1
24*4882a593Smuzhiyun #define F54_NUM_TX_OFFSET 1
25*4882a593Smuzhiyun #define F54_NUM_RX_OFFSET 0
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * The smbus protocol can read only 32 bytes max at a time.
29*4882a593Smuzhiyun * But this should be fine for i2c/spi as well.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #define F54_REPORT_DATA_SIZE 32
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* F54 commands */
34*4882a593Smuzhiyun #define F54_GET_REPORT 1
35*4882a593Smuzhiyun #define F54_FORCE_CAL 2
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* F54 capabilities */
38*4882a593Smuzhiyun #define F54_CAP_BASELINE (1 << 2)
39*4882a593Smuzhiyun #define F54_CAP_IMAGE8 (1 << 3)
40*4882a593Smuzhiyun #define F54_CAP_IMAGE16 (1 << 6)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /**
43*4882a593Smuzhiyun * enum rmi_f54_report_type - RMI4 F54 report types
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * @F54_8BIT_IMAGE: Normalized 8-Bit Image Report. The capacitance variance
46*4882a593Smuzhiyun * from baseline for each pixel.
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * @F54_16BIT_IMAGE: Normalized 16-Bit Image Report. The capacitance variance
49*4882a593Smuzhiyun * from baseline for each pixel.
50*4882a593Smuzhiyun *
51*4882a593Smuzhiyun * @F54_RAW_16BIT_IMAGE:
52*4882a593Smuzhiyun * Raw 16-Bit Image Report. The raw capacitance for each
53*4882a593Smuzhiyun * pixel.
54*4882a593Smuzhiyun *
55*4882a593Smuzhiyun * @F54_TRUE_BASELINE: True Baseline Report. The baseline capacitance for each
56*4882a593Smuzhiyun * pixel.
57*4882a593Smuzhiyun *
58*4882a593Smuzhiyun * @F54_FULL_RAW_CAP: Full Raw Capacitance Report. The raw capacitance with
59*4882a593Smuzhiyun * low reference set to its minimum value and high
60*4882a593Smuzhiyun * reference set to its maximum value.
61*4882a593Smuzhiyun *
62*4882a593Smuzhiyun * @F54_FULL_RAW_CAP_RX_OFFSET_REMOVED:
63*4882a593Smuzhiyun * Full Raw Capacitance with Receiver Offset Removed
64*4882a593Smuzhiyun * Report. Set Low reference to its minimum value and high
65*4882a593Smuzhiyun * references to its maximum value, then report the raw
66*4882a593Smuzhiyun * capacitance for each pixel.
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun enum rmi_f54_report_type {
69*4882a593Smuzhiyun F54_REPORT_NONE = 0,
70*4882a593Smuzhiyun F54_8BIT_IMAGE = 1,
71*4882a593Smuzhiyun F54_16BIT_IMAGE = 2,
72*4882a593Smuzhiyun F54_RAW_16BIT_IMAGE = 3,
73*4882a593Smuzhiyun F54_TRUE_BASELINE = 9,
74*4882a593Smuzhiyun F54_FULL_RAW_CAP = 19,
75*4882a593Smuzhiyun F54_FULL_RAW_CAP_RX_OFFSET_REMOVED = 20,
76*4882a593Smuzhiyun F54_MAX_REPORT_TYPE,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const char * const rmi_f54_report_type_names[] = {
80*4882a593Smuzhiyun [F54_REPORT_NONE] = "Unknown",
81*4882a593Smuzhiyun [F54_8BIT_IMAGE] = "Normalized 8-Bit Image",
82*4882a593Smuzhiyun [F54_16BIT_IMAGE] = "Normalized 16-Bit Image",
83*4882a593Smuzhiyun [F54_RAW_16BIT_IMAGE] = "Raw 16-Bit Image",
84*4882a593Smuzhiyun [F54_TRUE_BASELINE] = "True Baseline",
85*4882a593Smuzhiyun [F54_FULL_RAW_CAP] = "Full Raw Capacitance",
86*4882a593Smuzhiyun [F54_FULL_RAW_CAP_RX_OFFSET_REMOVED]
87*4882a593Smuzhiyun = "Full Raw Capacitance RX Offset Removed",
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct f54_data {
91*4882a593Smuzhiyun struct rmi_function *fn;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun u8 num_rx_electrodes;
94*4882a593Smuzhiyun u8 num_tx_electrodes;
95*4882a593Smuzhiyun u8 capabilities;
96*4882a593Smuzhiyun u16 clock_rate;
97*4882a593Smuzhiyun u8 family;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun enum rmi_f54_report_type report_type;
100*4882a593Smuzhiyun u8 *report_data;
101*4882a593Smuzhiyun int report_size;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun bool is_busy;
104*4882a593Smuzhiyun struct mutex status_mutex;
105*4882a593Smuzhiyun struct mutex data_mutex;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun struct workqueue_struct *workqueue;
108*4882a593Smuzhiyun struct delayed_work work;
109*4882a593Smuzhiyun unsigned long timeout;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun struct completion cmd_done;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* V4L2 support */
114*4882a593Smuzhiyun struct v4l2_device v4l2;
115*4882a593Smuzhiyun struct v4l2_pix_format format;
116*4882a593Smuzhiyun struct video_device vdev;
117*4882a593Smuzhiyun struct vb2_queue queue;
118*4882a593Smuzhiyun struct mutex lock;
119*4882a593Smuzhiyun u32 sequence;
120*4882a593Smuzhiyun int input;
121*4882a593Smuzhiyun enum rmi_f54_report_type inputs[F54_MAX_REPORT_TYPE];
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /*
125*4882a593Smuzhiyun * Basic checks on report_type to ensure we write a valid type
126*4882a593Smuzhiyun * to the sensor.
127*4882a593Smuzhiyun */
is_f54_report_type_valid(struct f54_data * f54,enum rmi_f54_report_type reptype)128*4882a593Smuzhiyun static bool is_f54_report_type_valid(struct f54_data *f54,
129*4882a593Smuzhiyun enum rmi_f54_report_type reptype)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun switch (reptype) {
132*4882a593Smuzhiyun case F54_8BIT_IMAGE:
133*4882a593Smuzhiyun return f54->capabilities & F54_CAP_IMAGE8;
134*4882a593Smuzhiyun case F54_16BIT_IMAGE:
135*4882a593Smuzhiyun case F54_RAW_16BIT_IMAGE:
136*4882a593Smuzhiyun return f54->capabilities & F54_CAP_IMAGE16;
137*4882a593Smuzhiyun case F54_TRUE_BASELINE:
138*4882a593Smuzhiyun return f54->capabilities & F54_CAP_IMAGE16;
139*4882a593Smuzhiyun case F54_FULL_RAW_CAP:
140*4882a593Smuzhiyun case F54_FULL_RAW_CAP_RX_OFFSET_REMOVED:
141*4882a593Smuzhiyun return true;
142*4882a593Smuzhiyun default:
143*4882a593Smuzhiyun return false;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
rmi_f54_get_reptype(struct f54_data * f54,unsigned int i)147*4882a593Smuzhiyun static enum rmi_f54_report_type rmi_f54_get_reptype(struct f54_data *f54,
148*4882a593Smuzhiyun unsigned int i)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun if (i >= F54_MAX_REPORT_TYPE)
151*4882a593Smuzhiyun return F54_REPORT_NONE;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return f54->inputs[i];
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
rmi_f54_create_input_map(struct f54_data * f54)156*4882a593Smuzhiyun static void rmi_f54_create_input_map(struct f54_data *f54)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun int i = 0;
159*4882a593Smuzhiyun enum rmi_f54_report_type reptype;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun for (reptype = 1; reptype < F54_MAX_REPORT_TYPE; reptype++) {
162*4882a593Smuzhiyun if (!is_f54_report_type_valid(f54, reptype))
163*4882a593Smuzhiyun continue;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun f54->inputs[i++] = reptype;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* Remaining values are zero via kzalloc */
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
rmi_f54_request_report(struct rmi_function * fn,u8 report_type)171*4882a593Smuzhiyun static int rmi_f54_request_report(struct rmi_function *fn, u8 report_type)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun struct f54_data *f54 = dev_get_drvdata(&fn->dev);
174*4882a593Smuzhiyun struct rmi_device *rmi_dev = fn->rmi_dev;
175*4882a593Smuzhiyun int error;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* Write Report Type into F54_AD_Data0 */
178*4882a593Smuzhiyun if (f54->report_type != report_type) {
179*4882a593Smuzhiyun error = rmi_write(rmi_dev, f54->fn->fd.data_base_addr,
180*4882a593Smuzhiyun report_type);
181*4882a593Smuzhiyun if (error)
182*4882a593Smuzhiyun return error;
183*4882a593Smuzhiyun f54->report_type = report_type;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /*
187*4882a593Smuzhiyun * Small delay after disabling interrupts to avoid race condition
188*4882a593Smuzhiyun * in firmare. This value is a bit higher than absolutely necessary.
189*4882a593Smuzhiyun * Should be removed once issue is resolved in firmware.
190*4882a593Smuzhiyun */
191*4882a593Smuzhiyun usleep_range(2000, 3000);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun mutex_lock(&f54->data_mutex);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun error = rmi_write(rmi_dev, fn->fd.command_base_addr, F54_GET_REPORT);
196*4882a593Smuzhiyun if (error < 0)
197*4882a593Smuzhiyun goto unlock;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun init_completion(&f54->cmd_done);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun f54->is_busy = 1;
202*4882a593Smuzhiyun f54->timeout = jiffies + msecs_to_jiffies(100);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun queue_delayed_work(f54->workqueue, &f54->work, 0);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun unlock:
207*4882a593Smuzhiyun mutex_unlock(&f54->data_mutex);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun return error;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
rmi_f54_get_report_size(struct f54_data * f54)212*4882a593Smuzhiyun static size_t rmi_f54_get_report_size(struct f54_data *f54)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun struct rmi_device *rmi_dev = f54->fn->rmi_dev;
215*4882a593Smuzhiyun struct rmi_driver_data *drv_data = dev_get_drvdata(&rmi_dev->dev);
216*4882a593Smuzhiyun u8 rx = drv_data->num_rx_electrodes ? : f54->num_rx_electrodes;
217*4882a593Smuzhiyun u8 tx = drv_data->num_tx_electrodes ? : f54->num_tx_electrodes;
218*4882a593Smuzhiyun size_t size;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun switch (rmi_f54_get_reptype(f54, f54->input)) {
221*4882a593Smuzhiyun case F54_8BIT_IMAGE:
222*4882a593Smuzhiyun size = rx * tx;
223*4882a593Smuzhiyun break;
224*4882a593Smuzhiyun case F54_16BIT_IMAGE:
225*4882a593Smuzhiyun case F54_RAW_16BIT_IMAGE:
226*4882a593Smuzhiyun case F54_TRUE_BASELINE:
227*4882a593Smuzhiyun case F54_FULL_RAW_CAP:
228*4882a593Smuzhiyun case F54_FULL_RAW_CAP_RX_OFFSET_REMOVED:
229*4882a593Smuzhiyun size = sizeof(u16) * rx * tx;
230*4882a593Smuzhiyun break;
231*4882a593Smuzhiyun default:
232*4882a593Smuzhiyun size = 0;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun return size;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
rmi_f54_get_pixel_fmt(enum rmi_f54_report_type reptype,u32 * pixfmt)238*4882a593Smuzhiyun static int rmi_f54_get_pixel_fmt(enum rmi_f54_report_type reptype, u32 *pixfmt)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun int ret = 0;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun switch (reptype) {
243*4882a593Smuzhiyun case F54_8BIT_IMAGE:
244*4882a593Smuzhiyun *pixfmt = V4L2_TCH_FMT_DELTA_TD08;
245*4882a593Smuzhiyun break;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun case F54_16BIT_IMAGE:
248*4882a593Smuzhiyun *pixfmt = V4L2_TCH_FMT_DELTA_TD16;
249*4882a593Smuzhiyun break;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun case F54_RAW_16BIT_IMAGE:
252*4882a593Smuzhiyun case F54_TRUE_BASELINE:
253*4882a593Smuzhiyun case F54_FULL_RAW_CAP:
254*4882a593Smuzhiyun case F54_FULL_RAW_CAP_RX_OFFSET_REMOVED:
255*4882a593Smuzhiyun *pixfmt = V4L2_TCH_FMT_TU16;
256*4882a593Smuzhiyun break;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun case F54_REPORT_NONE:
259*4882a593Smuzhiyun case F54_MAX_REPORT_TYPE:
260*4882a593Smuzhiyun ret = -EINVAL;
261*4882a593Smuzhiyun break;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun return ret;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun static const struct v4l2_file_operations rmi_f54_video_fops = {
268*4882a593Smuzhiyun .owner = THIS_MODULE,
269*4882a593Smuzhiyun .open = v4l2_fh_open,
270*4882a593Smuzhiyun .release = vb2_fop_release,
271*4882a593Smuzhiyun .unlocked_ioctl = video_ioctl2,
272*4882a593Smuzhiyun .read = vb2_fop_read,
273*4882a593Smuzhiyun .mmap = vb2_fop_mmap,
274*4882a593Smuzhiyun .poll = vb2_fop_poll,
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun
rmi_f54_queue_setup(struct vb2_queue * q,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])277*4882a593Smuzhiyun static int rmi_f54_queue_setup(struct vb2_queue *q, unsigned int *nbuffers,
278*4882a593Smuzhiyun unsigned int *nplanes, unsigned int sizes[],
279*4882a593Smuzhiyun struct device *alloc_devs[])
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun struct f54_data *f54 = q->drv_priv;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun if (*nplanes)
284*4882a593Smuzhiyun return sizes[0] < rmi_f54_get_report_size(f54) ? -EINVAL : 0;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun *nplanes = 1;
287*4882a593Smuzhiyun sizes[0] = rmi_f54_get_report_size(f54);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun return 0;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
rmi_f54_buffer_queue(struct vb2_buffer * vb)292*4882a593Smuzhiyun static void rmi_f54_buffer_queue(struct vb2_buffer *vb)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
295*4882a593Smuzhiyun struct f54_data *f54 = vb2_get_drv_priv(vb->vb2_queue);
296*4882a593Smuzhiyun u16 *ptr;
297*4882a593Smuzhiyun enum vb2_buffer_state state;
298*4882a593Smuzhiyun enum rmi_f54_report_type reptype;
299*4882a593Smuzhiyun int ret;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun mutex_lock(&f54->status_mutex);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun vb2_set_plane_payload(vb, 0, 0);
304*4882a593Smuzhiyun reptype = rmi_f54_get_reptype(f54, f54->input);
305*4882a593Smuzhiyun if (reptype == F54_REPORT_NONE) {
306*4882a593Smuzhiyun state = VB2_BUF_STATE_ERROR;
307*4882a593Smuzhiyun goto done;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun if (f54->is_busy) {
311*4882a593Smuzhiyun state = VB2_BUF_STATE_ERROR;
312*4882a593Smuzhiyun goto done;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun ret = rmi_f54_request_report(f54->fn, reptype);
316*4882a593Smuzhiyun if (ret) {
317*4882a593Smuzhiyun dev_err(&f54->fn->dev, "Error requesting F54 report\n");
318*4882a593Smuzhiyun state = VB2_BUF_STATE_ERROR;
319*4882a593Smuzhiyun goto done;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* get frame data */
323*4882a593Smuzhiyun mutex_lock(&f54->data_mutex);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun while (f54->is_busy) {
326*4882a593Smuzhiyun mutex_unlock(&f54->data_mutex);
327*4882a593Smuzhiyun if (!wait_for_completion_timeout(&f54->cmd_done,
328*4882a593Smuzhiyun msecs_to_jiffies(1000))) {
329*4882a593Smuzhiyun dev_err(&f54->fn->dev, "Timed out\n");
330*4882a593Smuzhiyun state = VB2_BUF_STATE_ERROR;
331*4882a593Smuzhiyun goto done;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun mutex_lock(&f54->data_mutex);
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun ptr = vb2_plane_vaddr(vb, 0);
337*4882a593Smuzhiyun if (!ptr) {
338*4882a593Smuzhiyun dev_err(&f54->fn->dev, "Error acquiring frame ptr\n");
339*4882a593Smuzhiyun state = VB2_BUF_STATE_ERROR;
340*4882a593Smuzhiyun goto data_done;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun memcpy(ptr, f54->report_data, f54->report_size);
344*4882a593Smuzhiyun vb2_set_plane_payload(vb, 0, rmi_f54_get_report_size(f54));
345*4882a593Smuzhiyun state = VB2_BUF_STATE_DONE;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun data_done:
348*4882a593Smuzhiyun mutex_unlock(&f54->data_mutex);
349*4882a593Smuzhiyun done:
350*4882a593Smuzhiyun vb->timestamp = ktime_get_ns();
351*4882a593Smuzhiyun vbuf->field = V4L2_FIELD_NONE;
352*4882a593Smuzhiyun vbuf->sequence = f54->sequence++;
353*4882a593Smuzhiyun vb2_buffer_done(vb, state);
354*4882a593Smuzhiyun mutex_unlock(&f54->status_mutex);
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
rmi_f54_stop_streaming(struct vb2_queue * q)357*4882a593Smuzhiyun static void rmi_f54_stop_streaming(struct vb2_queue *q)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun struct f54_data *f54 = vb2_get_drv_priv(q);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun f54->sequence = 0;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun /* V4L2 structures */
365*4882a593Smuzhiyun static const struct vb2_ops rmi_f54_queue_ops = {
366*4882a593Smuzhiyun .queue_setup = rmi_f54_queue_setup,
367*4882a593Smuzhiyun .buf_queue = rmi_f54_buffer_queue,
368*4882a593Smuzhiyun .stop_streaming = rmi_f54_stop_streaming,
369*4882a593Smuzhiyun .wait_prepare = vb2_ops_wait_prepare,
370*4882a593Smuzhiyun .wait_finish = vb2_ops_wait_finish,
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun static const struct vb2_queue rmi_f54_queue = {
374*4882a593Smuzhiyun .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
375*4882a593Smuzhiyun .io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ,
376*4882a593Smuzhiyun .buf_struct_size = sizeof(struct vb2_v4l2_buffer),
377*4882a593Smuzhiyun .ops = &rmi_f54_queue_ops,
378*4882a593Smuzhiyun .mem_ops = &vb2_vmalloc_memops,
379*4882a593Smuzhiyun .timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC,
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun
rmi_f54_vidioc_querycap(struct file * file,void * priv,struct v4l2_capability * cap)382*4882a593Smuzhiyun static int rmi_f54_vidioc_querycap(struct file *file, void *priv,
383*4882a593Smuzhiyun struct v4l2_capability *cap)
384*4882a593Smuzhiyun {
385*4882a593Smuzhiyun struct f54_data *f54 = video_drvdata(file);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun strlcpy(cap->driver, F54_NAME, sizeof(cap->driver));
388*4882a593Smuzhiyun strlcpy(cap->card, SYNAPTICS_INPUT_DEVICE_NAME, sizeof(cap->card));
389*4882a593Smuzhiyun snprintf(cap->bus_info, sizeof(cap->bus_info),
390*4882a593Smuzhiyun "rmi4:%s", dev_name(&f54->fn->dev));
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun return 0;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
rmi_f54_vidioc_enum_input(struct file * file,void * priv,struct v4l2_input * i)395*4882a593Smuzhiyun static int rmi_f54_vidioc_enum_input(struct file *file, void *priv,
396*4882a593Smuzhiyun struct v4l2_input *i)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun struct f54_data *f54 = video_drvdata(file);
399*4882a593Smuzhiyun enum rmi_f54_report_type reptype;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun reptype = rmi_f54_get_reptype(f54, i->index);
402*4882a593Smuzhiyun if (reptype == F54_REPORT_NONE)
403*4882a593Smuzhiyun return -EINVAL;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun i->type = V4L2_INPUT_TYPE_TOUCH;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun strlcpy(i->name, rmi_f54_report_type_names[reptype], sizeof(i->name));
408*4882a593Smuzhiyun return 0;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
rmi_f54_set_input(struct f54_data * f54,unsigned int i)411*4882a593Smuzhiyun static int rmi_f54_set_input(struct f54_data *f54, unsigned int i)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun struct rmi_device *rmi_dev = f54->fn->rmi_dev;
414*4882a593Smuzhiyun struct rmi_driver_data *drv_data = dev_get_drvdata(&rmi_dev->dev);
415*4882a593Smuzhiyun u8 rx = drv_data->num_rx_electrodes ? : f54->num_rx_electrodes;
416*4882a593Smuzhiyun u8 tx = drv_data->num_tx_electrodes ? : f54->num_tx_electrodes;
417*4882a593Smuzhiyun struct v4l2_pix_format *f = &f54->format;
418*4882a593Smuzhiyun enum rmi_f54_report_type reptype;
419*4882a593Smuzhiyun int ret;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun reptype = rmi_f54_get_reptype(f54, i);
422*4882a593Smuzhiyun if (reptype == F54_REPORT_NONE)
423*4882a593Smuzhiyun return -EINVAL;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun ret = rmi_f54_get_pixel_fmt(reptype, &f->pixelformat);
426*4882a593Smuzhiyun if (ret)
427*4882a593Smuzhiyun return ret;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun f54->input = i;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun f->width = rx;
432*4882a593Smuzhiyun f->height = tx;
433*4882a593Smuzhiyun f->field = V4L2_FIELD_NONE;
434*4882a593Smuzhiyun f->colorspace = V4L2_COLORSPACE_RAW;
435*4882a593Smuzhiyun f->bytesperline = f->width * sizeof(u16);
436*4882a593Smuzhiyun f->sizeimage = f->width * f->height * sizeof(u16);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun return 0;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
rmi_f54_vidioc_s_input(struct file * file,void * priv,unsigned int i)441*4882a593Smuzhiyun static int rmi_f54_vidioc_s_input(struct file *file, void *priv, unsigned int i)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun return rmi_f54_set_input(video_drvdata(file), i);
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
rmi_f54_vidioc_g_input(struct file * file,void * priv,unsigned int * i)446*4882a593Smuzhiyun static int rmi_f54_vidioc_g_input(struct file *file, void *priv,
447*4882a593Smuzhiyun unsigned int *i)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun struct f54_data *f54 = video_drvdata(file);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun *i = f54->input;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun return 0;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
rmi_f54_vidioc_fmt(struct file * file,void * priv,struct v4l2_format * f)456*4882a593Smuzhiyun static int rmi_f54_vidioc_fmt(struct file *file, void *priv,
457*4882a593Smuzhiyun struct v4l2_format *f)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun struct f54_data *f54 = video_drvdata(file);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun f->fmt.pix = f54->format;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun return 0;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
rmi_f54_vidioc_enum_fmt(struct file * file,void * priv,struct v4l2_fmtdesc * fmt)466*4882a593Smuzhiyun static int rmi_f54_vidioc_enum_fmt(struct file *file, void *priv,
467*4882a593Smuzhiyun struct v4l2_fmtdesc *fmt)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun struct f54_data *f54 = video_drvdata(file);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
472*4882a593Smuzhiyun return -EINVAL;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun if (fmt->index)
475*4882a593Smuzhiyun return -EINVAL;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun fmt->pixelformat = f54->format.pixelformat;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun return 0;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
rmi_f54_vidioc_g_parm(struct file * file,void * fh,struct v4l2_streamparm * a)482*4882a593Smuzhiyun static int rmi_f54_vidioc_g_parm(struct file *file, void *fh,
483*4882a593Smuzhiyun struct v4l2_streamparm *a)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
486*4882a593Smuzhiyun return -EINVAL;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun a->parm.capture.readbuffers = 1;
489*4882a593Smuzhiyun a->parm.capture.timeperframe.numerator = 1;
490*4882a593Smuzhiyun a->parm.capture.timeperframe.denominator = 10;
491*4882a593Smuzhiyun return 0;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun static const struct v4l2_ioctl_ops rmi_f54_video_ioctl_ops = {
495*4882a593Smuzhiyun .vidioc_querycap = rmi_f54_vidioc_querycap,
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun .vidioc_enum_fmt_vid_cap = rmi_f54_vidioc_enum_fmt,
498*4882a593Smuzhiyun .vidioc_s_fmt_vid_cap = rmi_f54_vidioc_fmt,
499*4882a593Smuzhiyun .vidioc_g_fmt_vid_cap = rmi_f54_vidioc_fmt,
500*4882a593Smuzhiyun .vidioc_try_fmt_vid_cap = rmi_f54_vidioc_fmt,
501*4882a593Smuzhiyun .vidioc_g_parm = rmi_f54_vidioc_g_parm,
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun .vidioc_enum_input = rmi_f54_vidioc_enum_input,
504*4882a593Smuzhiyun .vidioc_g_input = rmi_f54_vidioc_g_input,
505*4882a593Smuzhiyun .vidioc_s_input = rmi_f54_vidioc_s_input,
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun .vidioc_reqbufs = vb2_ioctl_reqbufs,
508*4882a593Smuzhiyun .vidioc_create_bufs = vb2_ioctl_create_bufs,
509*4882a593Smuzhiyun .vidioc_querybuf = vb2_ioctl_querybuf,
510*4882a593Smuzhiyun .vidioc_qbuf = vb2_ioctl_qbuf,
511*4882a593Smuzhiyun .vidioc_dqbuf = vb2_ioctl_dqbuf,
512*4882a593Smuzhiyun .vidioc_expbuf = vb2_ioctl_expbuf,
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun .vidioc_streamon = vb2_ioctl_streamon,
515*4882a593Smuzhiyun .vidioc_streamoff = vb2_ioctl_streamoff,
516*4882a593Smuzhiyun };
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun static const struct video_device rmi_f54_video_device = {
519*4882a593Smuzhiyun .name = "Synaptics RMI4",
520*4882a593Smuzhiyun .fops = &rmi_f54_video_fops,
521*4882a593Smuzhiyun .ioctl_ops = &rmi_f54_video_ioctl_ops,
522*4882a593Smuzhiyun .release = video_device_release_empty,
523*4882a593Smuzhiyun .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TOUCH |
524*4882a593Smuzhiyun V4L2_CAP_READWRITE | V4L2_CAP_STREAMING,
525*4882a593Smuzhiyun };
526*4882a593Smuzhiyun
rmi_f54_work(struct work_struct * work)527*4882a593Smuzhiyun static void rmi_f54_work(struct work_struct *work)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun struct f54_data *f54 = container_of(work, struct f54_data, work.work);
530*4882a593Smuzhiyun struct rmi_function *fn = f54->fn;
531*4882a593Smuzhiyun u8 fifo[2];
532*4882a593Smuzhiyun int report_size;
533*4882a593Smuzhiyun u8 command;
534*4882a593Smuzhiyun int error;
535*4882a593Smuzhiyun int i;
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun report_size = rmi_f54_get_report_size(f54);
538*4882a593Smuzhiyun if (report_size == 0) {
539*4882a593Smuzhiyun dev_err(&fn->dev, "Bad report size, report type=%d\n",
540*4882a593Smuzhiyun f54->report_type);
541*4882a593Smuzhiyun error = -EINVAL;
542*4882a593Smuzhiyun goto error; /* retry won't help */
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun mutex_lock(&f54->data_mutex);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun /*
548*4882a593Smuzhiyun * Need to check if command has completed.
549*4882a593Smuzhiyun * If not try again later.
550*4882a593Smuzhiyun */
551*4882a593Smuzhiyun error = rmi_read(fn->rmi_dev, f54->fn->fd.command_base_addr,
552*4882a593Smuzhiyun &command);
553*4882a593Smuzhiyun if (error) {
554*4882a593Smuzhiyun dev_err(&fn->dev, "Failed to read back command\n");
555*4882a593Smuzhiyun goto error;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun if (command & F54_GET_REPORT) {
558*4882a593Smuzhiyun if (time_after(jiffies, f54->timeout)) {
559*4882a593Smuzhiyun dev_err(&fn->dev, "Get report command timed out\n");
560*4882a593Smuzhiyun error = -ETIMEDOUT;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun report_size = 0;
563*4882a593Smuzhiyun goto error;
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun rmi_dbg(RMI_DEBUG_FN, &fn->dev, "Get report command completed, reading data\n");
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun for (i = 0; i < report_size; i += F54_REPORT_DATA_SIZE) {
569*4882a593Smuzhiyun int size = min(F54_REPORT_DATA_SIZE, report_size - i);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun fifo[0] = i & 0xff;
572*4882a593Smuzhiyun fifo[1] = i >> 8;
573*4882a593Smuzhiyun error = rmi_write_block(fn->rmi_dev,
574*4882a593Smuzhiyun fn->fd.data_base_addr + F54_FIFO_OFFSET,
575*4882a593Smuzhiyun fifo, sizeof(fifo));
576*4882a593Smuzhiyun if (error) {
577*4882a593Smuzhiyun dev_err(&fn->dev, "Failed to set fifo start offset\n");
578*4882a593Smuzhiyun goto abort;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun error = rmi_read_block(fn->rmi_dev, fn->fd.data_base_addr +
582*4882a593Smuzhiyun F54_REPORT_DATA_OFFSET,
583*4882a593Smuzhiyun f54->report_data + i, size);
584*4882a593Smuzhiyun if (error) {
585*4882a593Smuzhiyun dev_err(&fn->dev, "%s: read [%d bytes] returned %d\n",
586*4882a593Smuzhiyun __func__, size, error);
587*4882a593Smuzhiyun goto abort;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun abort:
592*4882a593Smuzhiyun f54->report_size = error ? 0 : report_size;
593*4882a593Smuzhiyun error:
594*4882a593Smuzhiyun if (error)
595*4882a593Smuzhiyun report_size = 0;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun if (report_size == 0 && !error) {
598*4882a593Smuzhiyun queue_delayed_work(f54->workqueue, &f54->work,
599*4882a593Smuzhiyun msecs_to_jiffies(1));
600*4882a593Smuzhiyun } else {
601*4882a593Smuzhiyun f54->is_busy = false;
602*4882a593Smuzhiyun complete(&f54->cmd_done);
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun mutex_unlock(&f54->data_mutex);
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
rmi_f54_config(struct rmi_function * fn)608*4882a593Smuzhiyun static int rmi_f54_config(struct rmi_function *fn)
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun struct rmi_driver *drv = fn->rmi_dev->driver;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun drv->clear_irq_bits(fn->rmi_dev, fn->irq_mask);
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun return 0;
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun
rmi_f54_detect(struct rmi_function * fn)617*4882a593Smuzhiyun static int rmi_f54_detect(struct rmi_function *fn)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun int error;
620*4882a593Smuzhiyun struct f54_data *f54;
621*4882a593Smuzhiyun u8 buf[6];
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun f54 = dev_get_drvdata(&fn->dev);
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun error = rmi_read_block(fn->rmi_dev, fn->fd.query_base_addr,
626*4882a593Smuzhiyun buf, sizeof(buf));
627*4882a593Smuzhiyun if (error) {
628*4882a593Smuzhiyun dev_err(&fn->dev, "%s: Failed to query F54 properties\n",
629*4882a593Smuzhiyun __func__);
630*4882a593Smuzhiyun return error;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun f54->num_rx_electrodes = buf[0];
634*4882a593Smuzhiyun f54->num_tx_electrodes = buf[1];
635*4882a593Smuzhiyun f54->capabilities = buf[2];
636*4882a593Smuzhiyun f54->clock_rate = buf[3] | (buf[4] << 8);
637*4882a593Smuzhiyun f54->family = buf[5];
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 num_rx_electrodes: %d\n",
640*4882a593Smuzhiyun f54->num_rx_electrodes);
641*4882a593Smuzhiyun rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 num_tx_electrodes: %d\n",
642*4882a593Smuzhiyun f54->num_tx_electrodes);
643*4882a593Smuzhiyun rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 capabilities: 0x%x\n",
644*4882a593Smuzhiyun f54->capabilities);
645*4882a593Smuzhiyun rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 clock rate: 0x%x\n",
646*4882a593Smuzhiyun f54->clock_rate);
647*4882a593Smuzhiyun rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 family: 0x%x\n",
648*4882a593Smuzhiyun f54->family);
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun f54->is_busy = false;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun return 0;
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun
rmi_f54_probe(struct rmi_function * fn)655*4882a593Smuzhiyun static int rmi_f54_probe(struct rmi_function *fn)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun struct f54_data *f54;
658*4882a593Smuzhiyun int ret;
659*4882a593Smuzhiyun u8 rx, tx;
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun f54 = devm_kzalloc(&fn->dev, sizeof(struct f54_data), GFP_KERNEL);
662*4882a593Smuzhiyun if (!f54)
663*4882a593Smuzhiyun return -ENOMEM;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun f54->fn = fn;
666*4882a593Smuzhiyun dev_set_drvdata(&fn->dev, f54);
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun ret = rmi_f54_detect(fn);
669*4882a593Smuzhiyun if (ret)
670*4882a593Smuzhiyun return ret;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun mutex_init(&f54->data_mutex);
673*4882a593Smuzhiyun mutex_init(&f54->status_mutex);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun rx = f54->num_rx_electrodes;
676*4882a593Smuzhiyun tx = f54->num_tx_electrodes;
677*4882a593Smuzhiyun f54->report_data = devm_kzalloc(&fn->dev,
678*4882a593Smuzhiyun array3_size(tx, rx, sizeof(u16)),
679*4882a593Smuzhiyun GFP_KERNEL);
680*4882a593Smuzhiyun if (f54->report_data == NULL)
681*4882a593Smuzhiyun return -ENOMEM;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun INIT_DELAYED_WORK(&f54->work, rmi_f54_work);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun f54->workqueue = create_singlethread_workqueue("rmi4-poller");
686*4882a593Smuzhiyun if (!f54->workqueue)
687*4882a593Smuzhiyun return -ENOMEM;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun rmi_f54_create_input_map(f54);
690*4882a593Smuzhiyun rmi_f54_set_input(f54, 0);
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun /* register video device */
693*4882a593Smuzhiyun strlcpy(f54->v4l2.name, F54_NAME, sizeof(f54->v4l2.name));
694*4882a593Smuzhiyun ret = v4l2_device_register(&fn->dev, &f54->v4l2);
695*4882a593Smuzhiyun if (ret) {
696*4882a593Smuzhiyun dev_err(&fn->dev, "Unable to register video dev.\n");
697*4882a593Smuzhiyun goto remove_wq;
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun /* initialize the queue */
701*4882a593Smuzhiyun mutex_init(&f54->lock);
702*4882a593Smuzhiyun f54->queue = rmi_f54_queue;
703*4882a593Smuzhiyun f54->queue.drv_priv = f54;
704*4882a593Smuzhiyun f54->queue.lock = &f54->lock;
705*4882a593Smuzhiyun f54->queue.dev = &fn->dev;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun ret = vb2_queue_init(&f54->queue);
708*4882a593Smuzhiyun if (ret)
709*4882a593Smuzhiyun goto remove_v4l2;
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun f54->vdev = rmi_f54_video_device;
712*4882a593Smuzhiyun f54->vdev.v4l2_dev = &f54->v4l2;
713*4882a593Smuzhiyun f54->vdev.lock = &f54->lock;
714*4882a593Smuzhiyun f54->vdev.vfl_dir = VFL_DIR_RX;
715*4882a593Smuzhiyun f54->vdev.queue = &f54->queue;
716*4882a593Smuzhiyun video_set_drvdata(&f54->vdev, f54);
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun ret = video_register_device(&f54->vdev, VFL_TYPE_TOUCH, -1);
719*4882a593Smuzhiyun if (ret) {
720*4882a593Smuzhiyun dev_err(&fn->dev, "Unable to register video subdevice.");
721*4882a593Smuzhiyun goto remove_v4l2;
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun return 0;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun remove_v4l2:
727*4882a593Smuzhiyun v4l2_device_unregister(&f54->v4l2);
728*4882a593Smuzhiyun remove_wq:
729*4882a593Smuzhiyun cancel_delayed_work_sync(&f54->work);
730*4882a593Smuzhiyun flush_workqueue(f54->workqueue);
731*4882a593Smuzhiyun destroy_workqueue(f54->workqueue);
732*4882a593Smuzhiyun return ret;
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun
rmi_f54_remove(struct rmi_function * fn)735*4882a593Smuzhiyun static void rmi_f54_remove(struct rmi_function *fn)
736*4882a593Smuzhiyun {
737*4882a593Smuzhiyun struct f54_data *f54 = dev_get_drvdata(&fn->dev);
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun video_unregister_device(&f54->vdev);
740*4882a593Smuzhiyun v4l2_device_unregister(&f54->v4l2);
741*4882a593Smuzhiyun destroy_workqueue(f54->workqueue);
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun struct rmi_function_handler rmi_f54_handler = {
745*4882a593Smuzhiyun .driver = {
746*4882a593Smuzhiyun .name = F54_NAME,
747*4882a593Smuzhiyun },
748*4882a593Smuzhiyun .func = 0x54,
749*4882a593Smuzhiyun .probe = rmi_f54_probe,
750*4882a593Smuzhiyun .config = rmi_f54_config,
751*4882a593Smuzhiyun .remove = rmi_f54_remove,
752*4882a593Smuzhiyun };
753