1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2011-2016 Synaptics Incorporated
4*4882a593Smuzhiyun * Copyright (c) 2011 Unixphere
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/rmi.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include <linux/uaccess.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <asm/unaligned.h>
13*4882a593Smuzhiyun #include "rmi_driver.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define RMI_PRODUCT_ID_LENGTH 10
16*4882a593Smuzhiyun #define RMI_PRODUCT_INFO_LENGTH 2
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define RMI_DATE_CODE_LENGTH 3
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define PRODUCT_ID_OFFSET 0x10
21*4882a593Smuzhiyun #define PRODUCT_INFO_OFFSET 0x1E
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Force a firmware reset of the sensor */
25*4882a593Smuzhiyun #define RMI_F01_CMD_DEVICE_RESET 1
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Various F01_RMI_QueryX bits */
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define RMI_F01_QRY1_CUSTOM_MAP BIT(0)
30*4882a593Smuzhiyun #define RMI_F01_QRY1_NON_COMPLIANT BIT(1)
31*4882a593Smuzhiyun #define RMI_F01_QRY1_HAS_LTS BIT(2)
32*4882a593Smuzhiyun #define RMI_F01_QRY1_HAS_SENSOR_ID BIT(3)
33*4882a593Smuzhiyun #define RMI_F01_QRY1_HAS_CHARGER_INP BIT(4)
34*4882a593Smuzhiyun #define RMI_F01_QRY1_HAS_ADJ_DOZE BIT(5)
35*4882a593Smuzhiyun #define RMI_F01_QRY1_HAS_ADJ_DOZE_HOFF BIT(6)
36*4882a593Smuzhiyun #define RMI_F01_QRY1_HAS_QUERY42 BIT(7)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define RMI_F01_QRY5_YEAR_MASK 0x1f
39*4882a593Smuzhiyun #define RMI_F01_QRY6_MONTH_MASK 0x0f
40*4882a593Smuzhiyun #define RMI_F01_QRY7_DAY_MASK 0x1f
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define RMI_F01_QRY2_PRODINFO_MASK 0x7f
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define RMI_F01_BASIC_QUERY_LEN 21 /* From Query 00 through 20 */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct f01_basic_properties {
47*4882a593Smuzhiyun u8 manufacturer_id;
48*4882a593Smuzhiyun bool has_lts;
49*4882a593Smuzhiyun bool has_adjustable_doze;
50*4882a593Smuzhiyun bool has_adjustable_doze_holdoff;
51*4882a593Smuzhiyun char dom[11]; /* YYYY/MM/DD + '\0' */
52*4882a593Smuzhiyun u8 product_id[RMI_PRODUCT_ID_LENGTH + 1];
53*4882a593Smuzhiyun u16 productinfo;
54*4882a593Smuzhiyun u32 firmware_id;
55*4882a593Smuzhiyun u32 package_id;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* F01 device status bits */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Most recent device status event */
61*4882a593Smuzhiyun #define RMI_F01_STATUS_CODE(status) ((status) & 0x0f)
62*4882a593Smuzhiyun /* The device has lost its configuration for some reason. */
63*4882a593Smuzhiyun #define RMI_F01_STATUS_UNCONFIGURED(status) (!!((status) & 0x80))
64*4882a593Smuzhiyun /* The device is in bootloader mode */
65*4882a593Smuzhiyun #define RMI_F01_STATUS_BOOTLOADER(status) ((status) & 0x40)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Control register bits */
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * Sleep mode controls power management on the device and affects all
71*4882a593Smuzhiyun * functions of the device.
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun #define RMI_F01_CTRL0_SLEEP_MODE_MASK 0x03
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define RMI_SLEEP_MODE_NORMAL 0x00
76*4882a593Smuzhiyun #define RMI_SLEEP_MODE_SENSOR_SLEEP 0x01
77*4882a593Smuzhiyun #define RMI_SLEEP_MODE_RESERVED0 0x02
78*4882a593Smuzhiyun #define RMI_SLEEP_MODE_RESERVED1 0x03
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * This bit disables whatever sleep mode may be selected by the sleep_mode
82*4882a593Smuzhiyun * field and forces the device to run at full power without sleeping.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun #define RMI_F01_CTRL0_NOSLEEP_BIT BIT(2)
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun * When this bit is set, the touch controller employs a noise-filtering
88*4882a593Smuzhiyun * algorithm designed for use with a connected battery charger.
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun #define RMI_F01_CTRL0_CHARGER_BIT BIT(5)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun * Sets the report rate for the device. The effect of this setting is
94*4882a593Smuzhiyun * highly product dependent. Check the spec sheet for your particular
95*4882a593Smuzhiyun * touch sensor.
96*4882a593Smuzhiyun */
97*4882a593Smuzhiyun #define RMI_F01_CTRL0_REPORTRATE_BIT BIT(6)
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun * Written by the host as an indicator that the device has been
101*4882a593Smuzhiyun * successfully configured.
102*4882a593Smuzhiyun */
103*4882a593Smuzhiyun #define RMI_F01_CTRL0_CONFIGURED_BIT BIT(7)
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /**
106*4882a593Smuzhiyun * @ctrl0 - see the bit definitions above.
107*4882a593Smuzhiyun * @doze_interval - controls the interval between checks for finger presence
108*4882a593Smuzhiyun * when the touch sensor is in doze mode, in units of 10ms.
109*4882a593Smuzhiyun * @wakeup_threshold - controls the capacitance threshold at which the touch
110*4882a593Smuzhiyun * sensor will decide to wake up from that low power state.
111*4882a593Smuzhiyun * @doze_holdoff - controls how long the touch sensor waits after the last
112*4882a593Smuzhiyun * finger lifts before entering the doze state, in units of 100ms.
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun struct f01_device_control {
115*4882a593Smuzhiyun u8 ctrl0;
116*4882a593Smuzhiyun u8 doze_interval;
117*4882a593Smuzhiyun u8 wakeup_threshold;
118*4882a593Smuzhiyun u8 doze_holdoff;
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun struct f01_data {
122*4882a593Smuzhiyun struct f01_basic_properties properties;
123*4882a593Smuzhiyun struct f01_device_control device_control;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun u16 doze_interval_addr;
126*4882a593Smuzhiyun u16 wakeup_threshold_addr;
127*4882a593Smuzhiyun u16 doze_holdoff_addr;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun bool suspended;
130*4882a593Smuzhiyun bool old_nosleep;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun unsigned int num_of_irq_regs;
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
rmi_f01_read_properties(struct rmi_device * rmi_dev,u16 query_base_addr,struct f01_basic_properties * props)135*4882a593Smuzhiyun static int rmi_f01_read_properties(struct rmi_device *rmi_dev,
136*4882a593Smuzhiyun u16 query_base_addr,
137*4882a593Smuzhiyun struct f01_basic_properties *props)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun u8 queries[RMI_F01_BASIC_QUERY_LEN];
140*4882a593Smuzhiyun int ret;
141*4882a593Smuzhiyun int query_offset = query_base_addr;
142*4882a593Smuzhiyun bool has_ds4_queries = false;
143*4882a593Smuzhiyun bool has_query42 = false;
144*4882a593Smuzhiyun bool has_sensor_id = false;
145*4882a593Smuzhiyun bool has_package_id_query = false;
146*4882a593Smuzhiyun bool has_build_id_query = false;
147*4882a593Smuzhiyun u16 prod_info_addr;
148*4882a593Smuzhiyun u8 ds4_query_len;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun ret = rmi_read_block(rmi_dev, query_offset,
151*4882a593Smuzhiyun queries, RMI_F01_BASIC_QUERY_LEN);
152*4882a593Smuzhiyun if (ret) {
153*4882a593Smuzhiyun dev_err(&rmi_dev->dev,
154*4882a593Smuzhiyun "Failed to read device query registers: %d\n", ret);
155*4882a593Smuzhiyun return ret;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun prod_info_addr = query_offset + 17;
159*4882a593Smuzhiyun query_offset += RMI_F01_BASIC_QUERY_LEN;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /* Now parse what we got */
162*4882a593Smuzhiyun props->manufacturer_id = queries[0];
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun props->has_lts = queries[1] & RMI_F01_QRY1_HAS_LTS;
165*4882a593Smuzhiyun props->has_adjustable_doze =
166*4882a593Smuzhiyun queries[1] & RMI_F01_QRY1_HAS_ADJ_DOZE;
167*4882a593Smuzhiyun props->has_adjustable_doze_holdoff =
168*4882a593Smuzhiyun queries[1] & RMI_F01_QRY1_HAS_ADJ_DOZE_HOFF;
169*4882a593Smuzhiyun has_query42 = queries[1] & RMI_F01_QRY1_HAS_QUERY42;
170*4882a593Smuzhiyun has_sensor_id = queries[1] & RMI_F01_QRY1_HAS_SENSOR_ID;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun snprintf(props->dom, sizeof(props->dom), "20%02d/%02d/%02d",
173*4882a593Smuzhiyun queries[5] & RMI_F01_QRY5_YEAR_MASK,
174*4882a593Smuzhiyun queries[6] & RMI_F01_QRY6_MONTH_MASK,
175*4882a593Smuzhiyun queries[7] & RMI_F01_QRY7_DAY_MASK);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun memcpy(props->product_id, &queries[11],
178*4882a593Smuzhiyun RMI_PRODUCT_ID_LENGTH);
179*4882a593Smuzhiyun props->product_id[RMI_PRODUCT_ID_LENGTH] = '\0';
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun props->productinfo =
182*4882a593Smuzhiyun ((queries[2] & RMI_F01_QRY2_PRODINFO_MASK) << 7) |
183*4882a593Smuzhiyun (queries[3] & RMI_F01_QRY2_PRODINFO_MASK);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (has_sensor_id)
186*4882a593Smuzhiyun query_offset++;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun if (has_query42) {
189*4882a593Smuzhiyun ret = rmi_read(rmi_dev, query_offset, queries);
190*4882a593Smuzhiyun if (ret) {
191*4882a593Smuzhiyun dev_err(&rmi_dev->dev,
192*4882a593Smuzhiyun "Failed to read query 42 register: %d\n", ret);
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun has_ds4_queries = !!(queries[0] & BIT(0));
197*4882a593Smuzhiyun query_offset++;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (has_ds4_queries) {
201*4882a593Smuzhiyun ret = rmi_read(rmi_dev, query_offset, &ds4_query_len);
202*4882a593Smuzhiyun if (ret) {
203*4882a593Smuzhiyun dev_err(&rmi_dev->dev,
204*4882a593Smuzhiyun "Failed to read DS4 queries length: %d\n", ret);
205*4882a593Smuzhiyun return ret;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun query_offset++;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun if (ds4_query_len > 0) {
210*4882a593Smuzhiyun ret = rmi_read(rmi_dev, query_offset, queries);
211*4882a593Smuzhiyun if (ret) {
212*4882a593Smuzhiyun dev_err(&rmi_dev->dev,
213*4882a593Smuzhiyun "Failed to read DS4 queries: %d\n",
214*4882a593Smuzhiyun ret);
215*4882a593Smuzhiyun return ret;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun has_package_id_query = !!(queries[0] & BIT(0));
219*4882a593Smuzhiyun has_build_id_query = !!(queries[0] & BIT(1));
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (has_package_id_query) {
223*4882a593Smuzhiyun ret = rmi_read_block(rmi_dev, prod_info_addr,
224*4882a593Smuzhiyun queries, sizeof(__le64));
225*4882a593Smuzhiyun if (ret) {
226*4882a593Smuzhiyun dev_err(&rmi_dev->dev,
227*4882a593Smuzhiyun "Failed to read package info: %d\n",
228*4882a593Smuzhiyun ret);
229*4882a593Smuzhiyun return ret;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun props->package_id = get_unaligned_le64(queries);
233*4882a593Smuzhiyun prod_info_addr++;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun if (has_build_id_query) {
237*4882a593Smuzhiyun ret = rmi_read_block(rmi_dev, prod_info_addr, queries,
238*4882a593Smuzhiyun 3);
239*4882a593Smuzhiyun if (ret) {
240*4882a593Smuzhiyun dev_err(&rmi_dev->dev,
241*4882a593Smuzhiyun "Failed to read product info: %d\n",
242*4882a593Smuzhiyun ret);
243*4882a593Smuzhiyun return ret;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun props->firmware_id = queries[1] << 8 | queries[0];
247*4882a593Smuzhiyun props->firmware_id += queries[2] * 65536;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun return 0;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
rmi_f01_get_product_ID(struct rmi_function * fn)254*4882a593Smuzhiyun const char *rmi_f01_get_product_ID(struct rmi_function *fn)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&fn->dev);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return f01->properties.product_id;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
rmi_driver_manufacturer_id_show(struct device * dev,struct device_attribute * dattr,char * buf)261*4882a593Smuzhiyun static ssize_t rmi_driver_manufacturer_id_show(struct device *dev,
262*4882a593Smuzhiyun struct device_attribute *dattr,
263*4882a593Smuzhiyun char *buf)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct rmi_driver_data *data = dev_get_drvdata(dev);
266*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&data->f01_container->dev);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%d\n",
269*4882a593Smuzhiyun f01->properties.manufacturer_id);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun static DEVICE_ATTR(manufacturer_id, 0444,
273*4882a593Smuzhiyun rmi_driver_manufacturer_id_show, NULL);
274*4882a593Smuzhiyun
rmi_driver_dom_show(struct device * dev,struct device_attribute * dattr,char * buf)275*4882a593Smuzhiyun static ssize_t rmi_driver_dom_show(struct device *dev,
276*4882a593Smuzhiyun struct device_attribute *dattr, char *buf)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun struct rmi_driver_data *data = dev_get_drvdata(dev);
279*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&data->f01_container->dev);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%s\n", f01->properties.dom);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun static DEVICE_ATTR(date_of_manufacture, 0444, rmi_driver_dom_show, NULL);
285*4882a593Smuzhiyun
rmi_driver_product_id_show(struct device * dev,struct device_attribute * dattr,char * buf)286*4882a593Smuzhiyun static ssize_t rmi_driver_product_id_show(struct device *dev,
287*4882a593Smuzhiyun struct device_attribute *dattr,
288*4882a593Smuzhiyun char *buf)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct rmi_driver_data *data = dev_get_drvdata(dev);
291*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&data->f01_container->dev);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%s\n", f01->properties.product_id);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun static DEVICE_ATTR(product_id, 0444, rmi_driver_product_id_show, NULL);
297*4882a593Smuzhiyun
rmi_driver_firmware_id_show(struct device * dev,struct device_attribute * dattr,char * buf)298*4882a593Smuzhiyun static ssize_t rmi_driver_firmware_id_show(struct device *dev,
299*4882a593Smuzhiyun struct device_attribute *dattr,
300*4882a593Smuzhiyun char *buf)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct rmi_driver_data *data = dev_get_drvdata(dev);
303*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&data->f01_container->dev);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%d\n", f01->properties.firmware_id);
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun static DEVICE_ATTR(firmware_id, 0444, rmi_driver_firmware_id_show, NULL);
309*4882a593Smuzhiyun
rmi_driver_package_id_show(struct device * dev,struct device_attribute * dattr,char * buf)310*4882a593Smuzhiyun static ssize_t rmi_driver_package_id_show(struct device *dev,
311*4882a593Smuzhiyun struct device_attribute *dattr,
312*4882a593Smuzhiyun char *buf)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun struct rmi_driver_data *data = dev_get_drvdata(dev);
315*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&data->f01_container->dev);
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun u32 package_id = f01->properties.package_id;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%04x.%04x\n",
320*4882a593Smuzhiyun package_id & 0xffff, (package_id >> 16) & 0xffff);
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun static DEVICE_ATTR(package_id, 0444, rmi_driver_package_id_show, NULL);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun static struct attribute *rmi_f01_attrs[] = {
326*4882a593Smuzhiyun &dev_attr_manufacturer_id.attr,
327*4882a593Smuzhiyun &dev_attr_date_of_manufacture.attr,
328*4882a593Smuzhiyun &dev_attr_product_id.attr,
329*4882a593Smuzhiyun &dev_attr_firmware_id.attr,
330*4882a593Smuzhiyun &dev_attr_package_id.attr,
331*4882a593Smuzhiyun NULL
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun static const struct attribute_group rmi_f01_attr_group = {
335*4882a593Smuzhiyun .attrs = rmi_f01_attrs,
336*4882a593Smuzhiyun };
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun #ifdef CONFIG_OF
rmi_f01_of_probe(struct device * dev,struct rmi_device_platform_data * pdata)339*4882a593Smuzhiyun static int rmi_f01_of_probe(struct device *dev,
340*4882a593Smuzhiyun struct rmi_device_platform_data *pdata)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun int retval;
343*4882a593Smuzhiyun u32 val;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun retval = rmi_of_property_read_u32(dev,
346*4882a593Smuzhiyun (u32 *)&pdata->power_management.nosleep,
347*4882a593Smuzhiyun "syna,nosleep-mode", 1);
348*4882a593Smuzhiyun if (retval)
349*4882a593Smuzhiyun return retval;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun retval = rmi_of_property_read_u32(dev, &val,
352*4882a593Smuzhiyun "syna,wakeup-threshold", 1);
353*4882a593Smuzhiyun if (retval)
354*4882a593Smuzhiyun return retval;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun pdata->power_management.wakeup_threshold = val;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun retval = rmi_of_property_read_u32(dev, &val,
359*4882a593Smuzhiyun "syna,doze-holdoff-ms", 1);
360*4882a593Smuzhiyun if (retval)
361*4882a593Smuzhiyun return retval;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun pdata->power_management.doze_holdoff = val * 100;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun retval = rmi_of_property_read_u32(dev, &val,
366*4882a593Smuzhiyun "syna,doze-interval-ms", 1);
367*4882a593Smuzhiyun if (retval)
368*4882a593Smuzhiyun return retval;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun pdata->power_management.doze_interval = val / 10;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun return 0;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun #else
rmi_f01_of_probe(struct device * dev,struct rmi_device_platform_data * pdata)375*4882a593Smuzhiyun static inline int rmi_f01_of_probe(struct device *dev,
376*4882a593Smuzhiyun struct rmi_device_platform_data *pdata)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun return -ENODEV;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun #endif
381*4882a593Smuzhiyun
rmi_f01_probe(struct rmi_function * fn)382*4882a593Smuzhiyun static int rmi_f01_probe(struct rmi_function *fn)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun struct rmi_device *rmi_dev = fn->rmi_dev;
385*4882a593Smuzhiyun struct rmi_driver_data *driver_data = dev_get_drvdata(&rmi_dev->dev);
386*4882a593Smuzhiyun struct rmi_device_platform_data *pdata = rmi_get_platform_data(rmi_dev);
387*4882a593Smuzhiyun struct f01_data *f01;
388*4882a593Smuzhiyun int error;
389*4882a593Smuzhiyun u16 ctrl_base_addr = fn->fd.control_base_addr;
390*4882a593Smuzhiyun u8 device_status;
391*4882a593Smuzhiyun u8 temp;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun if (fn->dev.of_node) {
394*4882a593Smuzhiyun error = rmi_f01_of_probe(&fn->dev, pdata);
395*4882a593Smuzhiyun if (error)
396*4882a593Smuzhiyun return error;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun f01 = devm_kzalloc(&fn->dev, sizeof(struct f01_data), GFP_KERNEL);
400*4882a593Smuzhiyun if (!f01)
401*4882a593Smuzhiyun return -ENOMEM;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun f01->num_of_irq_regs = driver_data->num_of_irq_regs;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun /*
406*4882a593Smuzhiyun * Set the configured bit and (optionally) other important stuff
407*4882a593Smuzhiyun * in the device control register.
408*4882a593Smuzhiyun */
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun error = rmi_read(rmi_dev, fn->fd.control_base_addr,
411*4882a593Smuzhiyun &f01->device_control.ctrl0);
412*4882a593Smuzhiyun if (error) {
413*4882a593Smuzhiyun dev_err(&fn->dev, "Failed to read F01 control: %d\n", error);
414*4882a593Smuzhiyun return error;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun switch (pdata->power_management.nosleep) {
418*4882a593Smuzhiyun case RMI_REG_STATE_DEFAULT:
419*4882a593Smuzhiyun break;
420*4882a593Smuzhiyun case RMI_REG_STATE_OFF:
421*4882a593Smuzhiyun f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_NOSLEEP_BIT;
422*4882a593Smuzhiyun break;
423*4882a593Smuzhiyun case RMI_REG_STATE_ON:
424*4882a593Smuzhiyun f01->device_control.ctrl0 |= RMI_F01_CTRL0_NOSLEEP_BIT;
425*4882a593Smuzhiyun break;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun /*
429*4882a593Smuzhiyun * Sleep mode might be set as a hangover from a system crash or
430*4882a593Smuzhiyun * reboot without power cycle. If so, clear it so the sensor
431*4882a593Smuzhiyun * is certain to function.
432*4882a593Smuzhiyun */
433*4882a593Smuzhiyun if ((f01->device_control.ctrl0 & RMI_F01_CTRL0_SLEEP_MODE_MASK) !=
434*4882a593Smuzhiyun RMI_SLEEP_MODE_NORMAL) {
435*4882a593Smuzhiyun dev_warn(&fn->dev,
436*4882a593Smuzhiyun "WARNING: Non-zero sleep mode found. Clearing...\n");
437*4882a593Smuzhiyun f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun f01->device_control.ctrl0 |= RMI_F01_CTRL0_CONFIGURED_BIT;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun error = rmi_write(rmi_dev, fn->fd.control_base_addr,
443*4882a593Smuzhiyun f01->device_control.ctrl0);
444*4882a593Smuzhiyun if (error) {
445*4882a593Smuzhiyun dev_err(&fn->dev, "Failed to write F01 control: %d\n", error);
446*4882a593Smuzhiyun return error;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun /* Dummy read in order to clear irqs */
450*4882a593Smuzhiyun error = rmi_read(rmi_dev, fn->fd.data_base_addr + 1, &temp);
451*4882a593Smuzhiyun if (error < 0) {
452*4882a593Smuzhiyun dev_err(&fn->dev, "Failed to read Interrupt Status.\n");
453*4882a593Smuzhiyun return error;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun error = rmi_f01_read_properties(rmi_dev, fn->fd.query_base_addr,
457*4882a593Smuzhiyun &f01->properties);
458*4882a593Smuzhiyun if (error < 0) {
459*4882a593Smuzhiyun dev_err(&fn->dev, "Failed to read F01 properties.\n");
460*4882a593Smuzhiyun return error;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun dev_info(&fn->dev, "found RMI device, manufacturer: %s, product: %s, fw id: %d\n",
464*4882a593Smuzhiyun f01->properties.manufacturer_id == 1 ? "Synaptics" : "unknown",
465*4882a593Smuzhiyun f01->properties.product_id, f01->properties.firmware_id);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun /* Advance to interrupt control registers, then skip over them. */
468*4882a593Smuzhiyun ctrl_base_addr++;
469*4882a593Smuzhiyun ctrl_base_addr += f01->num_of_irq_regs;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* read control register */
472*4882a593Smuzhiyun if (f01->properties.has_adjustable_doze) {
473*4882a593Smuzhiyun f01->doze_interval_addr = ctrl_base_addr;
474*4882a593Smuzhiyun ctrl_base_addr++;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun if (pdata->power_management.doze_interval) {
477*4882a593Smuzhiyun f01->device_control.doze_interval =
478*4882a593Smuzhiyun pdata->power_management.doze_interval;
479*4882a593Smuzhiyun error = rmi_write(rmi_dev, f01->doze_interval_addr,
480*4882a593Smuzhiyun f01->device_control.doze_interval);
481*4882a593Smuzhiyun if (error) {
482*4882a593Smuzhiyun dev_err(&fn->dev,
483*4882a593Smuzhiyun "Failed to configure F01 doze interval register: %d\n",
484*4882a593Smuzhiyun error);
485*4882a593Smuzhiyun return error;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun } else {
488*4882a593Smuzhiyun error = rmi_read(rmi_dev, f01->doze_interval_addr,
489*4882a593Smuzhiyun &f01->device_control.doze_interval);
490*4882a593Smuzhiyun if (error) {
491*4882a593Smuzhiyun dev_err(&fn->dev,
492*4882a593Smuzhiyun "Failed to read F01 doze interval register: %d\n",
493*4882a593Smuzhiyun error);
494*4882a593Smuzhiyun return error;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun f01->wakeup_threshold_addr = ctrl_base_addr;
499*4882a593Smuzhiyun ctrl_base_addr++;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun if (pdata->power_management.wakeup_threshold) {
502*4882a593Smuzhiyun f01->device_control.wakeup_threshold =
503*4882a593Smuzhiyun pdata->power_management.wakeup_threshold;
504*4882a593Smuzhiyun error = rmi_write(rmi_dev, f01->wakeup_threshold_addr,
505*4882a593Smuzhiyun f01->device_control.wakeup_threshold);
506*4882a593Smuzhiyun if (error) {
507*4882a593Smuzhiyun dev_err(&fn->dev,
508*4882a593Smuzhiyun "Failed to configure F01 wakeup threshold register: %d\n",
509*4882a593Smuzhiyun error);
510*4882a593Smuzhiyun return error;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun } else {
513*4882a593Smuzhiyun error = rmi_read(rmi_dev, f01->wakeup_threshold_addr,
514*4882a593Smuzhiyun &f01->device_control.wakeup_threshold);
515*4882a593Smuzhiyun if (error < 0) {
516*4882a593Smuzhiyun dev_err(&fn->dev,
517*4882a593Smuzhiyun "Failed to read F01 wakeup threshold register: %d\n",
518*4882a593Smuzhiyun error);
519*4882a593Smuzhiyun return error;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun if (f01->properties.has_lts)
525*4882a593Smuzhiyun ctrl_base_addr++;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun if (f01->properties.has_adjustable_doze_holdoff) {
528*4882a593Smuzhiyun f01->doze_holdoff_addr = ctrl_base_addr;
529*4882a593Smuzhiyun ctrl_base_addr++;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun if (pdata->power_management.doze_holdoff) {
532*4882a593Smuzhiyun f01->device_control.doze_holdoff =
533*4882a593Smuzhiyun pdata->power_management.doze_holdoff;
534*4882a593Smuzhiyun error = rmi_write(rmi_dev, f01->doze_holdoff_addr,
535*4882a593Smuzhiyun f01->device_control.doze_holdoff);
536*4882a593Smuzhiyun if (error) {
537*4882a593Smuzhiyun dev_err(&fn->dev,
538*4882a593Smuzhiyun "Failed to configure F01 doze holdoff register: %d\n",
539*4882a593Smuzhiyun error);
540*4882a593Smuzhiyun return error;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun } else {
543*4882a593Smuzhiyun error = rmi_read(rmi_dev, f01->doze_holdoff_addr,
544*4882a593Smuzhiyun &f01->device_control.doze_holdoff);
545*4882a593Smuzhiyun if (error) {
546*4882a593Smuzhiyun dev_err(&fn->dev,
547*4882a593Smuzhiyun "Failed to read F01 doze holdoff register: %d\n",
548*4882a593Smuzhiyun error);
549*4882a593Smuzhiyun return error;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun error = rmi_read(rmi_dev, fn->fd.data_base_addr, &device_status);
555*4882a593Smuzhiyun if (error < 0) {
556*4882a593Smuzhiyun dev_err(&fn->dev,
557*4882a593Smuzhiyun "Failed to read device status: %d\n", error);
558*4882a593Smuzhiyun return error;
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun if (RMI_F01_STATUS_UNCONFIGURED(device_status)) {
562*4882a593Smuzhiyun dev_err(&fn->dev,
563*4882a593Smuzhiyun "Device was reset during configuration process, status: %#02x!\n",
564*4882a593Smuzhiyun RMI_F01_STATUS_CODE(device_status));
565*4882a593Smuzhiyun return -EINVAL;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun dev_set_drvdata(&fn->dev, f01);
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun error = sysfs_create_group(&fn->rmi_dev->dev.kobj, &rmi_f01_attr_group);
571*4882a593Smuzhiyun if (error)
572*4882a593Smuzhiyun dev_warn(&fn->dev, "Failed to create sysfs group: %d\n", error);
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun return 0;
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun
rmi_f01_remove(struct rmi_function * fn)577*4882a593Smuzhiyun static void rmi_f01_remove(struct rmi_function *fn)
578*4882a593Smuzhiyun {
579*4882a593Smuzhiyun /* Note that the bus device is used, not the F01 device */
580*4882a593Smuzhiyun sysfs_remove_group(&fn->rmi_dev->dev.kobj, &rmi_f01_attr_group);
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
rmi_f01_config(struct rmi_function * fn)583*4882a593Smuzhiyun static int rmi_f01_config(struct rmi_function *fn)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&fn->dev);
586*4882a593Smuzhiyun int error;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun error = rmi_write(fn->rmi_dev, fn->fd.control_base_addr,
589*4882a593Smuzhiyun f01->device_control.ctrl0);
590*4882a593Smuzhiyun if (error) {
591*4882a593Smuzhiyun dev_err(&fn->dev,
592*4882a593Smuzhiyun "Failed to write device_control register: %d\n", error);
593*4882a593Smuzhiyun return error;
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun if (f01->properties.has_adjustable_doze) {
597*4882a593Smuzhiyun error = rmi_write(fn->rmi_dev, f01->doze_interval_addr,
598*4882a593Smuzhiyun f01->device_control.doze_interval);
599*4882a593Smuzhiyun if (error) {
600*4882a593Smuzhiyun dev_err(&fn->dev,
601*4882a593Smuzhiyun "Failed to write doze interval: %d\n", error);
602*4882a593Smuzhiyun return error;
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun error = rmi_write_block(fn->rmi_dev,
606*4882a593Smuzhiyun f01->wakeup_threshold_addr,
607*4882a593Smuzhiyun &f01->device_control.wakeup_threshold,
608*4882a593Smuzhiyun sizeof(u8));
609*4882a593Smuzhiyun if (error) {
610*4882a593Smuzhiyun dev_err(&fn->dev,
611*4882a593Smuzhiyun "Failed to write wakeup threshold: %d\n",
612*4882a593Smuzhiyun error);
613*4882a593Smuzhiyun return error;
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun if (f01->properties.has_adjustable_doze_holdoff) {
618*4882a593Smuzhiyun error = rmi_write(fn->rmi_dev, f01->doze_holdoff_addr,
619*4882a593Smuzhiyun f01->device_control.doze_holdoff);
620*4882a593Smuzhiyun if (error) {
621*4882a593Smuzhiyun dev_err(&fn->dev,
622*4882a593Smuzhiyun "Failed to write doze holdoff: %d\n", error);
623*4882a593Smuzhiyun return error;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun return 0;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun
rmi_f01_suspend(struct rmi_function * fn)630*4882a593Smuzhiyun static int rmi_f01_suspend(struct rmi_function *fn)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&fn->dev);
633*4882a593Smuzhiyun int error;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun f01->old_nosleep =
636*4882a593Smuzhiyun f01->device_control.ctrl0 & RMI_F01_CTRL0_NOSLEEP_BIT;
637*4882a593Smuzhiyun f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_NOSLEEP_BIT;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK;
640*4882a593Smuzhiyun if (device_may_wakeup(fn->rmi_dev->xport->dev))
641*4882a593Smuzhiyun f01->device_control.ctrl0 |= RMI_SLEEP_MODE_RESERVED1;
642*4882a593Smuzhiyun else
643*4882a593Smuzhiyun f01->device_control.ctrl0 |= RMI_SLEEP_MODE_SENSOR_SLEEP;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun error = rmi_write(fn->rmi_dev, fn->fd.control_base_addr,
646*4882a593Smuzhiyun f01->device_control.ctrl0);
647*4882a593Smuzhiyun if (error) {
648*4882a593Smuzhiyun dev_err(&fn->dev, "Failed to write sleep mode: %d.\n", error);
649*4882a593Smuzhiyun if (f01->old_nosleep)
650*4882a593Smuzhiyun f01->device_control.ctrl0 |= RMI_F01_CTRL0_NOSLEEP_BIT;
651*4882a593Smuzhiyun f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK;
652*4882a593Smuzhiyun f01->device_control.ctrl0 |= RMI_SLEEP_MODE_NORMAL;
653*4882a593Smuzhiyun return error;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun return 0;
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun
rmi_f01_resume(struct rmi_function * fn)659*4882a593Smuzhiyun static int rmi_f01_resume(struct rmi_function *fn)
660*4882a593Smuzhiyun {
661*4882a593Smuzhiyun struct f01_data *f01 = dev_get_drvdata(&fn->dev);
662*4882a593Smuzhiyun int error;
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun if (f01->old_nosleep)
665*4882a593Smuzhiyun f01->device_control.ctrl0 |= RMI_F01_CTRL0_NOSLEEP_BIT;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK;
668*4882a593Smuzhiyun f01->device_control.ctrl0 |= RMI_SLEEP_MODE_NORMAL;
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun error = rmi_write(fn->rmi_dev, fn->fd.control_base_addr,
671*4882a593Smuzhiyun f01->device_control.ctrl0);
672*4882a593Smuzhiyun if (error) {
673*4882a593Smuzhiyun dev_err(&fn->dev,
674*4882a593Smuzhiyun "Failed to restore normal operation: %d.\n", error);
675*4882a593Smuzhiyun return error;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun return 0;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun
rmi_f01_attention(int irq,void * ctx)681*4882a593Smuzhiyun static irqreturn_t rmi_f01_attention(int irq, void *ctx)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun struct rmi_function *fn = ctx;
684*4882a593Smuzhiyun struct rmi_device *rmi_dev = fn->rmi_dev;
685*4882a593Smuzhiyun int error;
686*4882a593Smuzhiyun u8 device_status;
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun error = rmi_read(rmi_dev, fn->fd.data_base_addr, &device_status);
689*4882a593Smuzhiyun if (error) {
690*4882a593Smuzhiyun dev_err(&fn->dev,
691*4882a593Smuzhiyun "Failed to read device status: %d.\n", error);
692*4882a593Smuzhiyun return IRQ_RETVAL(error);
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun if (RMI_F01_STATUS_BOOTLOADER(device_status))
696*4882a593Smuzhiyun dev_warn(&fn->dev,
697*4882a593Smuzhiyun "Device in bootloader mode, please update firmware\n");
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun if (RMI_F01_STATUS_UNCONFIGURED(device_status)) {
700*4882a593Smuzhiyun dev_warn(&fn->dev, "Device reset detected.\n");
701*4882a593Smuzhiyun error = rmi_dev->driver->reset_handler(rmi_dev);
702*4882a593Smuzhiyun if (error) {
703*4882a593Smuzhiyun dev_err(&fn->dev, "Device reset failed: %d\n", error);
704*4882a593Smuzhiyun return IRQ_RETVAL(error);
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun return IRQ_HANDLED;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun struct rmi_function_handler rmi_f01_handler = {
712*4882a593Smuzhiyun .driver = {
713*4882a593Smuzhiyun .name = "rmi4_f01",
714*4882a593Smuzhiyun /*
715*4882a593Smuzhiyun * Do not allow user unbinding F01 as it is critical
716*4882a593Smuzhiyun * function.
717*4882a593Smuzhiyun */
718*4882a593Smuzhiyun .suppress_bind_attrs = true,
719*4882a593Smuzhiyun },
720*4882a593Smuzhiyun .func = 0x01,
721*4882a593Smuzhiyun .probe = rmi_f01_probe,
722*4882a593Smuzhiyun .remove = rmi_f01_remove,
723*4882a593Smuzhiyun .config = rmi_f01_config,
724*4882a593Smuzhiyun .attention = rmi_f01_attention,
725*4882a593Smuzhiyun .suspend = rmi_f01_suspend,
726*4882a593Smuzhiyun .resume = rmi_f01_resume,
727*4882a593Smuzhiyun };
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