xref: /OK3568_Linux_fs/kernel/drivers/input/mouse/pxa930_trkball.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * PXA930 track ball mouse driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2007 Marvell International Ltd.
6*4882a593Smuzhiyun  * 2008-02-28: Yong Yao <yaoyong@marvell.com>
7*4882a593Smuzhiyun  *             initial version
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/input.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <mach/hardware.h>
19*4882a593Smuzhiyun #include <linux/platform_data/mouse-pxa930_trkball.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* Trackball Controller Register Definitions */
22*4882a593Smuzhiyun #define TBCR		(0x000C)
23*4882a593Smuzhiyun #define TBCNTR		(0x0010)
24*4882a593Smuzhiyun #define TBSBC		(0x0014)
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define TBCR_TBRST	(1 << 1)
27*4882a593Smuzhiyun #define TBCR_TBSB	(1 << 10)
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define TBCR_Y_FLT(n)	(((n) & 0xf) << 6)
30*4882a593Smuzhiyun #define TBCR_X_FLT(n)	(((n) & 0xf) << 2)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define TBCNTR_YM(n)	(((n) >> 24) & 0xff)
33*4882a593Smuzhiyun #define TBCNTR_YP(n)	(((n) >> 16) & 0xff)
34*4882a593Smuzhiyun #define TBCNTR_XM(n)	(((n) >> 8) & 0xff)
35*4882a593Smuzhiyun #define TBCNTR_XP(n)	((n) & 0xff)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define TBSBC_TBSBC	(0x1)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun struct pxa930_trkball {
40*4882a593Smuzhiyun 	struct pxa930_trkball_platform_data *pdata;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	/* Memory Mapped Register */
43*4882a593Smuzhiyun 	struct resource *mem;
44*4882a593Smuzhiyun 	void __iomem *mmio_base;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	struct input_dev *input;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
pxa930_trkball_interrupt(int irq,void * dev_id)49*4882a593Smuzhiyun static irqreturn_t pxa930_trkball_interrupt(int irq, void *dev_id)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	struct pxa930_trkball *trkball = dev_id;
52*4882a593Smuzhiyun 	struct input_dev *input = trkball->input;
53*4882a593Smuzhiyun 	int tbcntr, x, y;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	/* According to the spec software must read TBCNTR twice:
56*4882a593Smuzhiyun 	 * if the read value is the same, the reading is valid
57*4882a593Smuzhiyun 	 */
58*4882a593Smuzhiyun 	tbcntr = __raw_readl(trkball->mmio_base + TBCNTR);
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	if (tbcntr == __raw_readl(trkball->mmio_base + TBCNTR)) {
61*4882a593Smuzhiyun 		x = (TBCNTR_XP(tbcntr) - TBCNTR_XM(tbcntr)) / 2;
62*4882a593Smuzhiyun 		y = (TBCNTR_YP(tbcntr) - TBCNTR_YM(tbcntr)) / 2;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 		input_report_rel(input, REL_X, x);
65*4882a593Smuzhiyun 		input_report_rel(input, REL_Y, y);
66*4882a593Smuzhiyun 		input_sync(input);
67*4882a593Smuzhiyun 	}
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	__raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC);
70*4882a593Smuzhiyun 	__raw_writel(0, trkball->mmio_base + TBSBC);
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	return IRQ_HANDLED;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* For TBCR, we need to wait for a while to make sure it has been modified. */
write_tbcr(struct pxa930_trkball * trkball,int v)76*4882a593Smuzhiyun static int write_tbcr(struct pxa930_trkball *trkball, int v)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	int i = 100;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	__raw_writel(v, trkball->mmio_base + TBCR);
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	while (--i) {
83*4882a593Smuzhiyun 		if (__raw_readl(trkball->mmio_base + TBCR) == v)
84*4882a593Smuzhiyun 			break;
85*4882a593Smuzhiyun 		msleep(1);
86*4882a593Smuzhiyun 	}
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	if (i == 0) {
89*4882a593Smuzhiyun 		pr_err("%s: timed out writing TBCR(%x)!\n", __func__, v);
90*4882a593Smuzhiyun 		return -ETIMEDOUT;
91*4882a593Smuzhiyun 	}
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	return 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
pxa930_trkball_config(struct pxa930_trkball * trkball)96*4882a593Smuzhiyun static void pxa930_trkball_config(struct pxa930_trkball *trkball)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	uint32_t tbcr;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	/* According to spec, need to write the filters of x,y to 0xf first! */
101*4882a593Smuzhiyun 	tbcr = __raw_readl(trkball->mmio_base + TBCR);
102*4882a593Smuzhiyun 	write_tbcr(trkball, tbcr | TBCR_X_FLT(0xf) | TBCR_Y_FLT(0xf));
103*4882a593Smuzhiyun 	write_tbcr(trkball, TBCR_X_FLT(trkball->pdata->x_filter) |
104*4882a593Smuzhiyun 			    TBCR_Y_FLT(trkball->pdata->y_filter));
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	/* According to spec, set TBCR_TBRST first, before clearing it! */
107*4882a593Smuzhiyun 	tbcr = __raw_readl(trkball->mmio_base + TBCR);
108*4882a593Smuzhiyun 	write_tbcr(trkball, tbcr | TBCR_TBRST);
109*4882a593Smuzhiyun 	write_tbcr(trkball, tbcr & ~TBCR_TBRST);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	__raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC);
112*4882a593Smuzhiyun 	__raw_writel(0, trkball->mmio_base + TBSBC);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	pr_debug("%s: final TBCR=%x!\n", __func__,
115*4882a593Smuzhiyun 		 __raw_readl(trkball->mmio_base + TBCR));
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
pxa930_trkball_open(struct input_dev * dev)118*4882a593Smuzhiyun static int pxa930_trkball_open(struct input_dev *dev)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun 	struct pxa930_trkball *trkball = input_get_drvdata(dev);
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	pxa930_trkball_config(trkball);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun 
pxa930_trkball_disable(struct pxa930_trkball * trkball)127*4882a593Smuzhiyun static void pxa930_trkball_disable(struct pxa930_trkball *trkball)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	uint32_t tbcr = __raw_readl(trkball->mmio_base + TBCR);
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	/* Held in reset, gate the 32-KHz input clock off */
132*4882a593Smuzhiyun 	write_tbcr(trkball, tbcr | TBCR_TBRST);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
pxa930_trkball_close(struct input_dev * dev)135*4882a593Smuzhiyun static void pxa930_trkball_close(struct input_dev *dev)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct pxa930_trkball *trkball = input_get_drvdata(dev);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	pxa930_trkball_disable(trkball);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
pxa930_trkball_probe(struct platform_device * pdev)142*4882a593Smuzhiyun static int pxa930_trkball_probe(struct platform_device *pdev)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	struct pxa930_trkball *trkball;
145*4882a593Smuzhiyun 	struct input_dev *input;
146*4882a593Smuzhiyun 	struct resource *res;
147*4882a593Smuzhiyun 	int irq, error;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
150*4882a593Smuzhiyun 	if (irq < 0)
151*4882a593Smuzhiyun 		return -ENXIO;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
154*4882a593Smuzhiyun 	if (!res) {
155*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to get register memory\n");
156*4882a593Smuzhiyun 		return -ENXIO;
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	trkball = kzalloc(sizeof(struct pxa930_trkball), GFP_KERNEL);
160*4882a593Smuzhiyun 	if (!trkball)
161*4882a593Smuzhiyun 		return -ENOMEM;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	trkball->pdata = dev_get_platdata(&pdev->dev);
164*4882a593Smuzhiyun 	if (!trkball->pdata) {
165*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no platform data defined\n");
166*4882a593Smuzhiyun 		error = -EINVAL;
167*4882a593Smuzhiyun 		goto failed;
168*4882a593Smuzhiyun 	}
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	trkball->mmio_base = ioremap(res->start, resource_size(res));
171*4882a593Smuzhiyun 	if (!trkball->mmio_base) {
172*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to ioremap registers\n");
173*4882a593Smuzhiyun 		error = -ENXIO;
174*4882a593Smuzhiyun 		goto failed;
175*4882a593Smuzhiyun 	}
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	/* held the module in reset, will be enabled in open() */
178*4882a593Smuzhiyun 	pxa930_trkball_disable(trkball);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	error = request_irq(irq, pxa930_trkball_interrupt, 0,
181*4882a593Smuzhiyun 			    pdev->name, trkball);
182*4882a593Smuzhiyun 	if (error) {
183*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to request irq: %d\n", error);
184*4882a593Smuzhiyun 		goto failed_free_io;
185*4882a593Smuzhiyun 	}
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	platform_set_drvdata(pdev, trkball);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	input = input_allocate_device();
190*4882a593Smuzhiyun 	if (!input) {
191*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to allocate input device\n");
192*4882a593Smuzhiyun 		error = -ENOMEM;
193*4882a593Smuzhiyun 		goto failed_free_irq;
194*4882a593Smuzhiyun 	}
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	input->name = pdev->name;
197*4882a593Smuzhiyun 	input->id.bustype = BUS_HOST;
198*4882a593Smuzhiyun 	input->open = pxa930_trkball_open;
199*4882a593Smuzhiyun 	input->close = pxa930_trkball_close;
200*4882a593Smuzhiyun 	input->dev.parent = &pdev->dev;
201*4882a593Smuzhiyun 	input_set_drvdata(input, trkball);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	trkball->input = input;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	input_set_capability(input, EV_REL, REL_X);
206*4882a593Smuzhiyun 	input_set_capability(input, EV_REL, REL_Y);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	error = input_register_device(input);
209*4882a593Smuzhiyun 	if (error) {
210*4882a593Smuzhiyun 		dev_err(&pdev->dev, "unable to register input device\n");
211*4882a593Smuzhiyun 		goto failed_free_input;
212*4882a593Smuzhiyun 	}
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	return 0;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun failed_free_input:
217*4882a593Smuzhiyun 	input_free_device(input);
218*4882a593Smuzhiyun failed_free_irq:
219*4882a593Smuzhiyun 	free_irq(irq, trkball);
220*4882a593Smuzhiyun failed_free_io:
221*4882a593Smuzhiyun 	iounmap(trkball->mmio_base);
222*4882a593Smuzhiyun failed:
223*4882a593Smuzhiyun 	kfree(trkball);
224*4882a593Smuzhiyun 	return error;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun 
pxa930_trkball_remove(struct platform_device * pdev)227*4882a593Smuzhiyun static int pxa930_trkball_remove(struct platform_device *pdev)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun 	struct pxa930_trkball *trkball = platform_get_drvdata(pdev);
230*4882a593Smuzhiyun 	int irq = platform_get_irq(pdev, 0);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	input_unregister_device(trkball->input);
233*4882a593Smuzhiyun 	free_irq(irq, trkball);
234*4882a593Smuzhiyun 	iounmap(trkball->mmio_base);
235*4882a593Smuzhiyun 	kfree(trkball);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	return 0;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun static struct platform_driver pxa930_trkball_driver = {
241*4882a593Smuzhiyun 	.driver		= {
242*4882a593Smuzhiyun 		.name	= "pxa930-trkball",
243*4882a593Smuzhiyun 	},
244*4882a593Smuzhiyun 	.probe		= pxa930_trkball_probe,
245*4882a593Smuzhiyun 	.remove		= pxa930_trkball_remove,
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun module_platform_driver(pxa930_trkball_driver);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun MODULE_AUTHOR("Yong Yao <yaoyong@marvell.com>");
250*4882a593Smuzhiyun MODULE_DESCRIPTION("PXA930 Trackball Mouse Driver");
251*4882a593Smuzhiyun MODULE_LICENSE("GPL");
252