1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for Freescale's 3-Axis Accelerometer MMA8450
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/input.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define MMA8450_DRV_NAME "mma8450"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define MODE_CHANGE_DELAY_MS 100
19*4882a593Smuzhiyun #define POLL_INTERVAL 100
20*4882a593Smuzhiyun #define POLL_INTERVAL_MAX 500
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* register definitions */
23*4882a593Smuzhiyun #define MMA8450_STATUS 0x00
24*4882a593Smuzhiyun #define MMA8450_STATUS_ZXYDR 0x08
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define MMA8450_OUT_X8 0x01
27*4882a593Smuzhiyun #define MMA8450_OUT_Y8 0x02
28*4882a593Smuzhiyun #define MMA8450_OUT_Z8 0x03
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define MMA8450_OUT_X_LSB 0x05
31*4882a593Smuzhiyun #define MMA8450_OUT_X_MSB 0x06
32*4882a593Smuzhiyun #define MMA8450_OUT_Y_LSB 0x07
33*4882a593Smuzhiyun #define MMA8450_OUT_Y_MSB 0x08
34*4882a593Smuzhiyun #define MMA8450_OUT_Z_LSB 0x09
35*4882a593Smuzhiyun #define MMA8450_OUT_Z_MSB 0x0a
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define MMA8450_XYZ_DATA_CFG 0x16
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define MMA8450_CTRL_REG1 0x38
40*4882a593Smuzhiyun #define MMA8450_CTRL_REG2 0x39
41*4882a593Smuzhiyun
mma8450_read(struct i2c_client * c,unsigned int off)42*4882a593Smuzhiyun static int mma8450_read(struct i2c_client *c, unsigned int off)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun int ret;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(c, off);
47*4882a593Smuzhiyun if (ret < 0)
48*4882a593Smuzhiyun dev_err(&c->dev,
49*4882a593Smuzhiyun "failed to read register 0x%02x, error %d\n",
50*4882a593Smuzhiyun off, ret);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return ret;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
mma8450_write(struct i2c_client * c,unsigned int off,u8 v)55*4882a593Smuzhiyun static int mma8450_write(struct i2c_client *c, unsigned int off, u8 v)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun int error;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun error = i2c_smbus_write_byte_data(c, off, v);
60*4882a593Smuzhiyun if (error < 0) {
61*4882a593Smuzhiyun dev_err(&c->dev,
62*4882a593Smuzhiyun "failed to write to register 0x%02x, error %d\n",
63*4882a593Smuzhiyun off, error);
64*4882a593Smuzhiyun return error;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
mma8450_read_block(struct i2c_client * c,unsigned int off,u8 * buf,size_t size)70*4882a593Smuzhiyun static int mma8450_read_block(struct i2c_client *c, unsigned int off,
71*4882a593Smuzhiyun u8 *buf, size_t size)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun int err;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun err = i2c_smbus_read_i2c_block_data(c, off, size, buf);
76*4882a593Smuzhiyun if (err < 0) {
77*4882a593Smuzhiyun dev_err(&c->dev,
78*4882a593Smuzhiyun "failed to read block data at 0x%02x, error %d\n",
79*4882a593Smuzhiyun MMA8450_OUT_X_LSB, err);
80*4882a593Smuzhiyun return err;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
mma8450_poll(struct input_dev * input)86*4882a593Smuzhiyun static void mma8450_poll(struct input_dev *input)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct i2c_client *c = input_get_drvdata(input);
89*4882a593Smuzhiyun int x, y, z;
90*4882a593Smuzhiyun int ret;
91*4882a593Smuzhiyun u8 buf[6];
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun ret = mma8450_read(c, MMA8450_STATUS);
94*4882a593Smuzhiyun if (ret < 0)
95*4882a593Smuzhiyun return;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (!(ret & MMA8450_STATUS_ZXYDR))
98*4882a593Smuzhiyun return;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun ret = mma8450_read_block(c, MMA8450_OUT_X_LSB, buf, sizeof(buf));
101*4882a593Smuzhiyun if (ret < 0)
102*4882a593Smuzhiyun return;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun x = ((int)(s8)buf[1] << 4) | (buf[0] & 0xf);
105*4882a593Smuzhiyun y = ((int)(s8)buf[3] << 4) | (buf[2] & 0xf);
106*4882a593Smuzhiyun z = ((int)(s8)buf[5] << 4) | (buf[4] & 0xf);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun input_report_abs(input, ABS_X, x);
109*4882a593Smuzhiyun input_report_abs(input, ABS_Y, y);
110*4882a593Smuzhiyun input_report_abs(input, ABS_Z, z);
111*4882a593Smuzhiyun input_sync(input);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Initialize the MMA8450 chip */
mma8450_open(struct input_dev * input)115*4882a593Smuzhiyun static int mma8450_open(struct input_dev *input)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun struct i2c_client *c = input_get_drvdata(input);
118*4882a593Smuzhiyun int err;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* enable all events from X/Y/Z, no FIFO */
121*4882a593Smuzhiyun err = mma8450_write(c, MMA8450_XYZ_DATA_CFG, 0x07);
122*4882a593Smuzhiyun if (err)
123*4882a593Smuzhiyun return err;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /*
126*4882a593Smuzhiyun * Sleep mode poll rate - 50Hz
127*4882a593Smuzhiyun * System output data rate - 400Hz
128*4882a593Smuzhiyun * Full scale selection - Active, +/- 2G
129*4882a593Smuzhiyun */
130*4882a593Smuzhiyun err = mma8450_write(c, MMA8450_CTRL_REG1, 0x01);
131*4882a593Smuzhiyun if (err)
132*4882a593Smuzhiyun return err;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun msleep(MODE_CHANGE_DELAY_MS);
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
mma8450_close(struct input_dev * input)138*4882a593Smuzhiyun static void mma8450_close(struct input_dev *input)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun struct i2c_client *c = input_get_drvdata(input);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun mma8450_write(c, MMA8450_CTRL_REG1, 0x00);
143*4882a593Smuzhiyun mma8450_write(c, MMA8450_CTRL_REG2, 0x01);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * I2C init/probing/exit functions
148*4882a593Smuzhiyun */
mma8450_probe(struct i2c_client * c,const struct i2c_device_id * id)149*4882a593Smuzhiyun static int mma8450_probe(struct i2c_client *c,
150*4882a593Smuzhiyun const struct i2c_device_id *id)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct input_dev *input;
153*4882a593Smuzhiyun int err;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun input = devm_input_allocate_device(&c->dev);
156*4882a593Smuzhiyun if (!input)
157*4882a593Smuzhiyun return -ENOMEM;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun input_set_drvdata(input, c);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun input->name = MMA8450_DRV_NAME;
162*4882a593Smuzhiyun input->id.bustype = BUS_I2C;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun input->open = mma8450_open;
165*4882a593Smuzhiyun input->close = mma8450_close;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun input_set_abs_params(input, ABS_X, -2048, 2047, 32, 32);
168*4882a593Smuzhiyun input_set_abs_params(input, ABS_Y, -2048, 2047, 32, 32);
169*4882a593Smuzhiyun input_set_abs_params(input, ABS_Z, -2048, 2047, 32, 32);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun err = input_setup_polling(input, mma8450_poll);
172*4882a593Smuzhiyun if (err) {
173*4882a593Smuzhiyun dev_err(&c->dev, "failed to set up polling\n");
174*4882a593Smuzhiyun return err;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun input_set_poll_interval(input, POLL_INTERVAL);
178*4882a593Smuzhiyun input_set_max_poll_interval(input, POLL_INTERVAL_MAX);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun err = input_register_device(input);
181*4882a593Smuzhiyun if (err) {
182*4882a593Smuzhiyun dev_err(&c->dev, "failed to register input device\n");
183*4882a593Smuzhiyun return err;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun return 0;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun static const struct i2c_device_id mma8450_id[] = {
190*4882a593Smuzhiyun { MMA8450_DRV_NAME, 0 },
191*4882a593Smuzhiyun { },
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mma8450_id);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static const struct of_device_id mma8450_dt_ids[] = {
196*4882a593Smuzhiyun { .compatible = "fsl,mma8450", },
197*4882a593Smuzhiyun { /* sentinel */ }
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mma8450_dt_ids);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun static struct i2c_driver mma8450_driver = {
202*4882a593Smuzhiyun .driver = {
203*4882a593Smuzhiyun .name = MMA8450_DRV_NAME,
204*4882a593Smuzhiyun .of_match_table = mma8450_dt_ids,
205*4882a593Smuzhiyun },
206*4882a593Smuzhiyun .probe = mma8450_probe,
207*4882a593Smuzhiyun .id_table = mma8450_id,
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun module_i2c_driver(mma8450_driver);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun MODULE_AUTHOR("Freescale Semiconductor, Inc.");
213*4882a593Smuzhiyun MODULE_DESCRIPTION("MMA8450 3-Axis Accelerometer Driver");
214*4882a593Smuzhiyun MODULE_LICENSE("GPL");
215