1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Azoteq IQS269A Capacitive Touch Controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2020 Jeff LaBundy <jeff@labundy.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This driver registers up to 3 input devices: one representing capacitive or
8*4882a593Smuzhiyun * inductive keys as well as Hall-effect switches, and one for each of the two
9*4882a593Smuzhiyun * axial sliders presented by the device.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/input.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/mutex.h>
21*4882a593Smuzhiyun #include <linux/of_device.h>
22*4882a593Smuzhiyun #include <linux/property.h>
23*4882a593Smuzhiyun #include <linux/regmap.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define IQS269_VER_INFO 0x00
27*4882a593Smuzhiyun #define IQS269_VER_INFO_PROD_NUM 0x4F
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define IQS269_SYS_FLAGS 0x02
30*4882a593Smuzhiyun #define IQS269_SYS_FLAGS_SHOW_RESET BIT(15)
31*4882a593Smuzhiyun #define IQS269_SYS_FLAGS_PWR_MODE_MASK GENMASK(12, 11)
32*4882a593Smuzhiyun #define IQS269_SYS_FLAGS_PWR_MODE_SHIFT 11
33*4882a593Smuzhiyun #define IQS269_SYS_FLAGS_IN_ATI BIT(10)
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define IQS269_CHx_COUNTS 0x08
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define IQS269_SLIDER_X 0x30
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define IQS269_CAL_DATA_A 0x35
40*4882a593Smuzhiyun #define IQS269_CAL_DATA_A_HALL_BIN_L_MASK GENMASK(15, 12)
41*4882a593Smuzhiyun #define IQS269_CAL_DATA_A_HALL_BIN_L_SHIFT 12
42*4882a593Smuzhiyun #define IQS269_CAL_DATA_A_HALL_BIN_R_MASK GENMASK(11, 8)
43*4882a593Smuzhiyun #define IQS269_CAL_DATA_A_HALL_BIN_R_SHIFT 8
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS 0x80
46*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_CLK_DIV BIT(15)
47*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_ULP_AUTO BIT(14)
48*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_DIS_AUTO BIT(13)
49*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_PWR_MODE_MASK GENMASK(12, 11)
50*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_PWR_MODE_SHIFT 11
51*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_PWR_MODE_MAX 3
52*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_ULP_UPDATE_MASK GENMASK(10, 8)
53*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_ULP_UPDATE_SHIFT 8
54*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_ULP_UPDATE_MAX 7
55*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_RESEED_OFFSET BIT(6)
56*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_EVENT_MODE BIT(5)
57*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_EVENT_MODE_LP BIT(4)
58*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_REDO_ATI BIT(2)
59*4882a593Smuzhiyun #define IQS269_SYS_SETTINGS_ACK_RESET BIT(0)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define IQS269_FILT_STR_LP_LTA_MASK GENMASK(7, 6)
62*4882a593Smuzhiyun #define IQS269_FILT_STR_LP_LTA_SHIFT 6
63*4882a593Smuzhiyun #define IQS269_FILT_STR_LP_CNT_MASK GENMASK(5, 4)
64*4882a593Smuzhiyun #define IQS269_FILT_STR_LP_CNT_SHIFT 4
65*4882a593Smuzhiyun #define IQS269_FILT_STR_NP_LTA_MASK GENMASK(3, 2)
66*4882a593Smuzhiyun #define IQS269_FILT_STR_NP_LTA_SHIFT 2
67*4882a593Smuzhiyun #define IQS269_FILT_STR_NP_CNT_MASK GENMASK(1, 0)
68*4882a593Smuzhiyun #define IQS269_FILT_STR_MAX 3
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define IQS269_EVENT_MASK_SYS BIT(6)
71*4882a593Smuzhiyun #define IQS269_EVENT_MASK_DEEP BIT(2)
72*4882a593Smuzhiyun #define IQS269_EVENT_MASK_TOUCH BIT(1)
73*4882a593Smuzhiyun #define IQS269_EVENT_MASK_PROX BIT(0)
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define IQS269_RATE_NP_MS_MAX 255
76*4882a593Smuzhiyun #define IQS269_RATE_LP_MS_MAX 255
77*4882a593Smuzhiyun #define IQS269_RATE_ULP_MS_MAX 4080
78*4882a593Smuzhiyun #define IQS269_TIMEOUT_PWR_MS_MAX 130560
79*4882a593Smuzhiyun #define IQS269_TIMEOUT_LTA_MS_MAX 130560
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define IQS269_MISC_A_ATI_BAND_DISABLE BIT(15)
82*4882a593Smuzhiyun #define IQS269_MISC_A_ATI_LP_ONLY BIT(14)
83*4882a593Smuzhiyun #define IQS269_MISC_A_ATI_BAND_TIGHTEN BIT(13)
84*4882a593Smuzhiyun #define IQS269_MISC_A_FILT_DISABLE BIT(12)
85*4882a593Smuzhiyun #define IQS269_MISC_A_GPIO3_SELECT_MASK GENMASK(10, 8)
86*4882a593Smuzhiyun #define IQS269_MISC_A_GPIO3_SELECT_SHIFT 8
87*4882a593Smuzhiyun #define IQS269_MISC_A_DUAL_DIR BIT(6)
88*4882a593Smuzhiyun #define IQS269_MISC_A_TX_FREQ_MASK GENMASK(5, 4)
89*4882a593Smuzhiyun #define IQS269_MISC_A_TX_FREQ_SHIFT 4
90*4882a593Smuzhiyun #define IQS269_MISC_A_TX_FREQ_MAX 3
91*4882a593Smuzhiyun #define IQS269_MISC_A_GLOBAL_CAP_SIZE BIT(0)
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define IQS269_MISC_B_RESEED_UI_SEL_MASK GENMASK(7, 6)
94*4882a593Smuzhiyun #define IQS269_MISC_B_RESEED_UI_SEL_SHIFT 6
95*4882a593Smuzhiyun #define IQS269_MISC_B_RESEED_UI_SEL_MAX 3
96*4882a593Smuzhiyun #define IQS269_MISC_B_TRACKING_UI_ENABLE BIT(4)
97*4882a593Smuzhiyun #define IQS269_MISC_B_FILT_STR_SLIDER GENMASK(1, 0)
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #define IQS269_CHx_SETTINGS 0x8C
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_MEAS_CAP_SIZE BIT(15)
102*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_RX_GND_INACTIVE BIT(13)
103*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_LOCAL_CAP_SIZE BIT(12)
104*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_ATI_MODE_MASK GENMASK(9, 8)
105*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_ATI_MODE_SHIFT 8
106*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_ATI_MODE_MAX 3
107*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_INV_LOGIC BIT(7)
108*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_PROJ_BIAS_MASK GENMASK(6, 5)
109*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_PROJ_BIAS_SHIFT 5
110*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_PROJ_BIAS_MAX 3
111*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_SENSE_MODE_MASK GENMASK(3, 0)
112*4882a593Smuzhiyun #define IQS269_CHx_ENG_A_SENSE_MODE_MAX 15
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_LOCAL_CAP_ENABLE BIT(13)
115*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_SENSE_FREQ_MASK GENMASK(10, 9)
116*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_SENSE_FREQ_SHIFT 9
117*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_SENSE_FREQ_MAX 3
118*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_STATIC_ENABLE BIT(8)
119*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_ATI_BASE_MASK GENMASK(7, 6)
120*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_ATI_BASE_75 0x00
121*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_ATI_BASE_100 0x40
122*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_ATI_BASE_150 0x80
123*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_ATI_BASE_200 0xC0
124*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_ATI_TARGET_MASK GENMASK(5, 0)
125*4882a593Smuzhiyun #define IQS269_CHx_ENG_B_ATI_TARGET_MAX 2016
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #define IQS269_CHx_WEIGHT_MAX 255
128*4882a593Smuzhiyun #define IQS269_CHx_THRESH_MAX 255
129*4882a593Smuzhiyun #define IQS269_CHx_HYST_DEEP_MASK GENMASK(7, 4)
130*4882a593Smuzhiyun #define IQS269_CHx_HYST_DEEP_SHIFT 4
131*4882a593Smuzhiyun #define IQS269_CHx_HYST_TOUCH_MASK GENMASK(3, 0)
132*4882a593Smuzhiyun #define IQS269_CHx_HYST_MAX 15
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun #define IQS269_CHx_HALL_INACTIVE 6
135*4882a593Smuzhiyun #define IQS269_CHx_HALL_ACTIVE 7
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun #define IQS269_HALL_PAD_R BIT(0)
138*4882a593Smuzhiyun #define IQS269_HALL_PAD_L BIT(1)
139*4882a593Smuzhiyun #define IQS269_HALL_PAD_INV BIT(6)
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #define IQS269_HALL_UI 0xF5
142*4882a593Smuzhiyun #define IQS269_HALL_UI_ENABLE BIT(15)
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #define IQS269_MAX_REG 0xFF
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun #define IQS269_NUM_CH 8
147*4882a593Smuzhiyun #define IQS269_NUM_SL 2
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun #define IQS269_ATI_POLL_SLEEP_US (iqs269->delay_mult * 10000)
150*4882a593Smuzhiyun #define IQS269_ATI_POLL_TIMEOUT_US (iqs269->delay_mult * 500000)
151*4882a593Smuzhiyun #define IQS269_ATI_STABLE_DELAY_MS (iqs269->delay_mult * 150)
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun #define IQS269_PWR_MODE_POLL_SLEEP_US IQS269_ATI_POLL_SLEEP_US
154*4882a593Smuzhiyun #define IQS269_PWR_MODE_POLL_TIMEOUT_US IQS269_ATI_POLL_TIMEOUT_US
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun #define iqs269_irq_wait() usleep_range(100, 150)
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun enum iqs269_local_cap_size {
159*4882a593Smuzhiyun IQS269_LOCAL_CAP_SIZE_0,
160*4882a593Smuzhiyun IQS269_LOCAL_CAP_SIZE_GLOBAL_ONLY,
161*4882a593Smuzhiyun IQS269_LOCAL_CAP_SIZE_GLOBAL_0pF5,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun enum iqs269_st_offs {
165*4882a593Smuzhiyun IQS269_ST_OFFS_PROX,
166*4882a593Smuzhiyun IQS269_ST_OFFS_DIR,
167*4882a593Smuzhiyun IQS269_ST_OFFS_TOUCH,
168*4882a593Smuzhiyun IQS269_ST_OFFS_DEEP,
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun enum iqs269_th_offs {
172*4882a593Smuzhiyun IQS269_TH_OFFS_PROX,
173*4882a593Smuzhiyun IQS269_TH_OFFS_TOUCH,
174*4882a593Smuzhiyun IQS269_TH_OFFS_DEEP,
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun enum iqs269_event_id {
178*4882a593Smuzhiyun IQS269_EVENT_PROX_DN,
179*4882a593Smuzhiyun IQS269_EVENT_PROX_UP,
180*4882a593Smuzhiyun IQS269_EVENT_TOUCH_DN,
181*4882a593Smuzhiyun IQS269_EVENT_TOUCH_UP,
182*4882a593Smuzhiyun IQS269_EVENT_DEEP_DN,
183*4882a593Smuzhiyun IQS269_EVENT_DEEP_UP,
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun struct iqs269_switch_desc {
187*4882a593Smuzhiyun unsigned int code;
188*4882a593Smuzhiyun bool enabled;
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun struct iqs269_event_desc {
192*4882a593Smuzhiyun const char *name;
193*4882a593Smuzhiyun enum iqs269_st_offs st_offs;
194*4882a593Smuzhiyun enum iqs269_th_offs th_offs;
195*4882a593Smuzhiyun bool dir_up;
196*4882a593Smuzhiyun u8 mask;
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun static const struct iqs269_event_desc iqs269_events[] = {
200*4882a593Smuzhiyun [IQS269_EVENT_PROX_DN] = {
201*4882a593Smuzhiyun .name = "event-prox",
202*4882a593Smuzhiyun .st_offs = IQS269_ST_OFFS_PROX,
203*4882a593Smuzhiyun .th_offs = IQS269_TH_OFFS_PROX,
204*4882a593Smuzhiyun .mask = IQS269_EVENT_MASK_PROX,
205*4882a593Smuzhiyun },
206*4882a593Smuzhiyun [IQS269_EVENT_PROX_UP] = {
207*4882a593Smuzhiyun .name = "event-prox-alt",
208*4882a593Smuzhiyun .st_offs = IQS269_ST_OFFS_PROX,
209*4882a593Smuzhiyun .th_offs = IQS269_TH_OFFS_PROX,
210*4882a593Smuzhiyun .dir_up = true,
211*4882a593Smuzhiyun .mask = IQS269_EVENT_MASK_PROX,
212*4882a593Smuzhiyun },
213*4882a593Smuzhiyun [IQS269_EVENT_TOUCH_DN] = {
214*4882a593Smuzhiyun .name = "event-touch",
215*4882a593Smuzhiyun .st_offs = IQS269_ST_OFFS_TOUCH,
216*4882a593Smuzhiyun .th_offs = IQS269_TH_OFFS_TOUCH,
217*4882a593Smuzhiyun .mask = IQS269_EVENT_MASK_TOUCH,
218*4882a593Smuzhiyun },
219*4882a593Smuzhiyun [IQS269_EVENT_TOUCH_UP] = {
220*4882a593Smuzhiyun .name = "event-touch-alt",
221*4882a593Smuzhiyun .st_offs = IQS269_ST_OFFS_TOUCH,
222*4882a593Smuzhiyun .th_offs = IQS269_TH_OFFS_TOUCH,
223*4882a593Smuzhiyun .dir_up = true,
224*4882a593Smuzhiyun .mask = IQS269_EVENT_MASK_TOUCH,
225*4882a593Smuzhiyun },
226*4882a593Smuzhiyun [IQS269_EVENT_DEEP_DN] = {
227*4882a593Smuzhiyun .name = "event-deep",
228*4882a593Smuzhiyun .st_offs = IQS269_ST_OFFS_DEEP,
229*4882a593Smuzhiyun .th_offs = IQS269_TH_OFFS_DEEP,
230*4882a593Smuzhiyun .mask = IQS269_EVENT_MASK_DEEP,
231*4882a593Smuzhiyun },
232*4882a593Smuzhiyun [IQS269_EVENT_DEEP_UP] = {
233*4882a593Smuzhiyun .name = "event-deep-alt",
234*4882a593Smuzhiyun .st_offs = IQS269_ST_OFFS_DEEP,
235*4882a593Smuzhiyun .th_offs = IQS269_TH_OFFS_DEEP,
236*4882a593Smuzhiyun .dir_up = true,
237*4882a593Smuzhiyun .mask = IQS269_EVENT_MASK_DEEP,
238*4882a593Smuzhiyun },
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun struct iqs269_ver_info {
242*4882a593Smuzhiyun u8 prod_num;
243*4882a593Smuzhiyun u8 sw_num;
244*4882a593Smuzhiyun u8 hw_num;
245*4882a593Smuzhiyun u8 padding;
246*4882a593Smuzhiyun } __packed;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun struct iqs269_sys_reg {
249*4882a593Smuzhiyun __be16 general;
250*4882a593Smuzhiyun u8 active;
251*4882a593Smuzhiyun u8 filter;
252*4882a593Smuzhiyun u8 reseed;
253*4882a593Smuzhiyun u8 event_mask;
254*4882a593Smuzhiyun u8 rate_np;
255*4882a593Smuzhiyun u8 rate_lp;
256*4882a593Smuzhiyun u8 rate_ulp;
257*4882a593Smuzhiyun u8 timeout_pwr;
258*4882a593Smuzhiyun u8 timeout_rdy;
259*4882a593Smuzhiyun u8 timeout_lta;
260*4882a593Smuzhiyun __be16 misc_a;
261*4882a593Smuzhiyun __be16 misc_b;
262*4882a593Smuzhiyun u8 blocking;
263*4882a593Smuzhiyun u8 padding;
264*4882a593Smuzhiyun u8 slider_select[IQS269_NUM_SL];
265*4882a593Smuzhiyun u8 timeout_tap;
266*4882a593Smuzhiyun u8 timeout_swipe;
267*4882a593Smuzhiyun u8 thresh_swipe;
268*4882a593Smuzhiyun u8 redo_ati;
269*4882a593Smuzhiyun } __packed;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun struct iqs269_ch_reg {
272*4882a593Smuzhiyun u8 rx_enable;
273*4882a593Smuzhiyun u8 tx_enable;
274*4882a593Smuzhiyun __be16 engine_a;
275*4882a593Smuzhiyun __be16 engine_b;
276*4882a593Smuzhiyun __be16 ati_comp;
277*4882a593Smuzhiyun u8 thresh[3];
278*4882a593Smuzhiyun u8 hyst;
279*4882a593Smuzhiyun u8 assoc_select;
280*4882a593Smuzhiyun u8 assoc_weight;
281*4882a593Smuzhiyun } __packed;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun struct iqs269_flags {
284*4882a593Smuzhiyun __be16 system;
285*4882a593Smuzhiyun u8 gesture;
286*4882a593Smuzhiyun u8 padding;
287*4882a593Smuzhiyun u8 states[4];
288*4882a593Smuzhiyun } __packed;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun struct iqs269_private {
291*4882a593Smuzhiyun struct i2c_client *client;
292*4882a593Smuzhiyun struct regmap *regmap;
293*4882a593Smuzhiyun struct mutex lock;
294*4882a593Smuzhiyun struct iqs269_switch_desc switches[ARRAY_SIZE(iqs269_events)];
295*4882a593Smuzhiyun struct iqs269_ch_reg ch_reg[IQS269_NUM_CH];
296*4882a593Smuzhiyun struct iqs269_sys_reg sys_reg;
297*4882a593Smuzhiyun struct input_dev *keypad;
298*4882a593Smuzhiyun struct input_dev *slider[IQS269_NUM_SL];
299*4882a593Smuzhiyun unsigned int keycode[ARRAY_SIZE(iqs269_events) * IQS269_NUM_CH];
300*4882a593Smuzhiyun unsigned int suspend_mode;
301*4882a593Smuzhiyun unsigned int delay_mult;
302*4882a593Smuzhiyun unsigned int ch_num;
303*4882a593Smuzhiyun bool hall_enable;
304*4882a593Smuzhiyun bool ati_current;
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun
iqs269_ati_mode_set(struct iqs269_private * iqs269,unsigned int ch_num,unsigned int mode)307*4882a593Smuzhiyun static int iqs269_ati_mode_set(struct iqs269_private *iqs269,
308*4882a593Smuzhiyun unsigned int ch_num, unsigned int mode)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun u16 engine_a;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun if (ch_num >= IQS269_NUM_CH)
313*4882a593Smuzhiyun return -EINVAL;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun if (mode > IQS269_CHx_ENG_A_ATI_MODE_MAX)
316*4882a593Smuzhiyun return -EINVAL;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun engine_a = be16_to_cpu(iqs269->ch_reg[ch_num].engine_a);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun engine_a &= ~IQS269_CHx_ENG_A_ATI_MODE_MASK;
323*4882a593Smuzhiyun engine_a |= (mode << IQS269_CHx_ENG_A_ATI_MODE_SHIFT);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun iqs269->ch_reg[ch_num].engine_a = cpu_to_be16(engine_a);
326*4882a593Smuzhiyun iqs269->ati_current = false;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return 0;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
iqs269_ati_mode_get(struct iqs269_private * iqs269,unsigned int ch_num,unsigned int * mode)333*4882a593Smuzhiyun static int iqs269_ati_mode_get(struct iqs269_private *iqs269,
334*4882a593Smuzhiyun unsigned int ch_num, unsigned int *mode)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun u16 engine_a;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun if (ch_num >= IQS269_NUM_CH)
339*4882a593Smuzhiyun return -EINVAL;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
342*4882a593Smuzhiyun engine_a = be16_to_cpu(iqs269->ch_reg[ch_num].engine_a);
343*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun engine_a &= IQS269_CHx_ENG_A_ATI_MODE_MASK;
346*4882a593Smuzhiyun *mode = (engine_a >> IQS269_CHx_ENG_A_ATI_MODE_SHIFT);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun return 0;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
iqs269_ati_base_set(struct iqs269_private * iqs269,unsigned int ch_num,unsigned int base)351*4882a593Smuzhiyun static int iqs269_ati_base_set(struct iqs269_private *iqs269,
352*4882a593Smuzhiyun unsigned int ch_num, unsigned int base)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun u16 engine_b;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun if (ch_num >= IQS269_NUM_CH)
357*4882a593Smuzhiyun return -EINVAL;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun switch (base) {
360*4882a593Smuzhiyun case 75:
361*4882a593Smuzhiyun base = IQS269_CHx_ENG_B_ATI_BASE_75;
362*4882a593Smuzhiyun break;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun case 100:
365*4882a593Smuzhiyun base = IQS269_CHx_ENG_B_ATI_BASE_100;
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun case 150:
369*4882a593Smuzhiyun base = IQS269_CHx_ENG_B_ATI_BASE_150;
370*4882a593Smuzhiyun break;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun case 200:
373*4882a593Smuzhiyun base = IQS269_CHx_ENG_B_ATI_BASE_200;
374*4882a593Smuzhiyun break;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun default:
377*4882a593Smuzhiyun return -EINVAL;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun engine_b = be16_to_cpu(iqs269->ch_reg[ch_num].engine_b);
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun engine_b &= ~IQS269_CHx_ENG_B_ATI_BASE_MASK;
385*4882a593Smuzhiyun engine_b |= base;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun iqs269->ch_reg[ch_num].engine_b = cpu_to_be16(engine_b);
388*4882a593Smuzhiyun iqs269->ati_current = false;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun return 0;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
iqs269_ati_base_get(struct iqs269_private * iqs269,unsigned int ch_num,unsigned int * base)395*4882a593Smuzhiyun static int iqs269_ati_base_get(struct iqs269_private *iqs269,
396*4882a593Smuzhiyun unsigned int ch_num, unsigned int *base)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun u16 engine_b;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun if (ch_num >= IQS269_NUM_CH)
401*4882a593Smuzhiyun return -EINVAL;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
404*4882a593Smuzhiyun engine_b = be16_to_cpu(iqs269->ch_reg[ch_num].engine_b);
405*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun switch (engine_b & IQS269_CHx_ENG_B_ATI_BASE_MASK) {
408*4882a593Smuzhiyun case IQS269_CHx_ENG_B_ATI_BASE_75:
409*4882a593Smuzhiyun *base = 75;
410*4882a593Smuzhiyun return 0;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun case IQS269_CHx_ENG_B_ATI_BASE_100:
413*4882a593Smuzhiyun *base = 100;
414*4882a593Smuzhiyun return 0;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun case IQS269_CHx_ENG_B_ATI_BASE_150:
417*4882a593Smuzhiyun *base = 150;
418*4882a593Smuzhiyun return 0;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun case IQS269_CHx_ENG_B_ATI_BASE_200:
421*4882a593Smuzhiyun *base = 200;
422*4882a593Smuzhiyun return 0;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun default:
425*4882a593Smuzhiyun return -EINVAL;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
iqs269_ati_target_set(struct iqs269_private * iqs269,unsigned int ch_num,unsigned int target)429*4882a593Smuzhiyun static int iqs269_ati_target_set(struct iqs269_private *iqs269,
430*4882a593Smuzhiyun unsigned int ch_num, unsigned int target)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun u16 engine_b;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun if (ch_num >= IQS269_NUM_CH)
435*4882a593Smuzhiyun return -EINVAL;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if (target > IQS269_CHx_ENG_B_ATI_TARGET_MAX)
438*4882a593Smuzhiyun return -EINVAL;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun engine_b = be16_to_cpu(iqs269->ch_reg[ch_num].engine_b);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun engine_b &= ~IQS269_CHx_ENG_B_ATI_TARGET_MASK;
445*4882a593Smuzhiyun engine_b |= target / 32;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun iqs269->ch_reg[ch_num].engine_b = cpu_to_be16(engine_b);
448*4882a593Smuzhiyun iqs269->ati_current = false;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun return 0;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
iqs269_ati_target_get(struct iqs269_private * iqs269,unsigned int ch_num,unsigned int * target)455*4882a593Smuzhiyun static int iqs269_ati_target_get(struct iqs269_private *iqs269,
456*4882a593Smuzhiyun unsigned int ch_num, unsigned int *target)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun u16 engine_b;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun if (ch_num >= IQS269_NUM_CH)
461*4882a593Smuzhiyun return -EINVAL;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
464*4882a593Smuzhiyun engine_b = be16_to_cpu(iqs269->ch_reg[ch_num].engine_b);
465*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun *target = (engine_b & IQS269_CHx_ENG_B_ATI_TARGET_MASK) * 32;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun return 0;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
iqs269_parse_mask(const struct fwnode_handle * fwnode,const char * propname,u8 * mask)472*4882a593Smuzhiyun static int iqs269_parse_mask(const struct fwnode_handle *fwnode,
473*4882a593Smuzhiyun const char *propname, u8 *mask)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun unsigned int val[IQS269_NUM_CH];
476*4882a593Smuzhiyun int count, error, i;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun count = fwnode_property_count_u32(fwnode, propname);
479*4882a593Smuzhiyun if (count < 0)
480*4882a593Smuzhiyun return 0;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun if (count > IQS269_NUM_CH)
483*4882a593Smuzhiyun return -EINVAL;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun error = fwnode_property_read_u32_array(fwnode, propname, val, count);
486*4882a593Smuzhiyun if (error)
487*4882a593Smuzhiyun return error;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun *mask = 0;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun for (i = 0; i < count; i++) {
492*4882a593Smuzhiyun if (val[i] >= IQS269_NUM_CH)
493*4882a593Smuzhiyun return -EINVAL;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun *mask |= BIT(val[i]);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun return 0;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
iqs269_parse_chan(struct iqs269_private * iqs269,const struct fwnode_handle * ch_node)501*4882a593Smuzhiyun static int iqs269_parse_chan(struct iqs269_private *iqs269,
502*4882a593Smuzhiyun const struct fwnode_handle *ch_node)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
505*4882a593Smuzhiyun struct fwnode_handle *ev_node;
506*4882a593Smuzhiyun struct iqs269_ch_reg *ch_reg;
507*4882a593Smuzhiyun u16 engine_a, engine_b;
508*4882a593Smuzhiyun unsigned int reg, val;
509*4882a593Smuzhiyun int error, i;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun error = fwnode_property_read_u32(ch_node, "reg", ®);
512*4882a593Smuzhiyun if (error) {
513*4882a593Smuzhiyun dev_err(&client->dev, "Failed to read channel number: %d\n",
514*4882a593Smuzhiyun error);
515*4882a593Smuzhiyun return error;
516*4882a593Smuzhiyun } else if (reg >= IQS269_NUM_CH) {
517*4882a593Smuzhiyun dev_err(&client->dev, "Invalid channel number: %u\n", reg);
518*4882a593Smuzhiyun return -EINVAL;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun iqs269->sys_reg.active |= BIT(reg);
522*4882a593Smuzhiyun if (!fwnode_property_present(ch_node, "azoteq,reseed-disable"))
523*4882a593Smuzhiyun iqs269->sys_reg.reseed |= BIT(reg);
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun if (fwnode_property_present(ch_node, "azoteq,blocking-enable"))
526*4882a593Smuzhiyun iqs269->sys_reg.blocking |= BIT(reg);
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun if (fwnode_property_present(ch_node, "azoteq,slider0-select"))
529*4882a593Smuzhiyun iqs269->sys_reg.slider_select[0] |= BIT(reg);
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun if (fwnode_property_present(ch_node, "azoteq,slider1-select"))
532*4882a593Smuzhiyun iqs269->sys_reg.slider_select[1] |= BIT(reg);
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun ch_reg = &iqs269->ch_reg[reg];
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun error = regmap_raw_read(iqs269->regmap,
537*4882a593Smuzhiyun IQS269_CHx_SETTINGS + reg * sizeof(*ch_reg) / 2,
538*4882a593Smuzhiyun ch_reg, sizeof(*ch_reg));
539*4882a593Smuzhiyun if (error)
540*4882a593Smuzhiyun return error;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun error = iqs269_parse_mask(ch_node, "azoteq,rx-enable",
543*4882a593Smuzhiyun &ch_reg->rx_enable);
544*4882a593Smuzhiyun if (error) {
545*4882a593Smuzhiyun dev_err(&client->dev, "Invalid channel %u RX enable mask: %d\n",
546*4882a593Smuzhiyun reg, error);
547*4882a593Smuzhiyun return error;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun error = iqs269_parse_mask(ch_node, "azoteq,tx-enable",
551*4882a593Smuzhiyun &ch_reg->tx_enable);
552*4882a593Smuzhiyun if (error) {
553*4882a593Smuzhiyun dev_err(&client->dev, "Invalid channel %u TX enable mask: %d\n",
554*4882a593Smuzhiyun reg, error);
555*4882a593Smuzhiyun return error;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun engine_a = be16_to_cpu(ch_reg->engine_a);
559*4882a593Smuzhiyun engine_b = be16_to_cpu(ch_reg->engine_b);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun engine_a |= IQS269_CHx_ENG_A_MEAS_CAP_SIZE;
562*4882a593Smuzhiyun if (fwnode_property_present(ch_node, "azoteq,meas-cap-decrease"))
563*4882a593Smuzhiyun engine_a &= ~IQS269_CHx_ENG_A_MEAS_CAP_SIZE;
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun engine_a |= IQS269_CHx_ENG_A_RX_GND_INACTIVE;
566*4882a593Smuzhiyun if (fwnode_property_present(ch_node, "azoteq,rx-float-inactive"))
567*4882a593Smuzhiyun engine_a &= ~IQS269_CHx_ENG_A_RX_GND_INACTIVE;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun engine_a &= ~IQS269_CHx_ENG_A_LOCAL_CAP_SIZE;
570*4882a593Smuzhiyun engine_b &= ~IQS269_CHx_ENG_B_LOCAL_CAP_ENABLE;
571*4882a593Smuzhiyun if (!fwnode_property_read_u32(ch_node, "azoteq,local-cap-size", &val)) {
572*4882a593Smuzhiyun switch (val) {
573*4882a593Smuzhiyun case IQS269_LOCAL_CAP_SIZE_0:
574*4882a593Smuzhiyun break;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun case IQS269_LOCAL_CAP_SIZE_GLOBAL_0pF5:
577*4882a593Smuzhiyun engine_a |= IQS269_CHx_ENG_A_LOCAL_CAP_SIZE;
578*4882a593Smuzhiyun fallthrough;
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun case IQS269_LOCAL_CAP_SIZE_GLOBAL_ONLY:
581*4882a593Smuzhiyun engine_b |= IQS269_CHx_ENG_B_LOCAL_CAP_ENABLE;
582*4882a593Smuzhiyun break;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun default:
585*4882a593Smuzhiyun dev_err(&client->dev,
586*4882a593Smuzhiyun "Invalid channel %u local cap. size: %u\n", reg,
587*4882a593Smuzhiyun val);
588*4882a593Smuzhiyun return -EINVAL;
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun engine_a &= ~IQS269_CHx_ENG_A_INV_LOGIC;
593*4882a593Smuzhiyun if (fwnode_property_present(ch_node, "azoteq,invert-enable"))
594*4882a593Smuzhiyun engine_a |= IQS269_CHx_ENG_A_INV_LOGIC;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun if (!fwnode_property_read_u32(ch_node, "azoteq,proj-bias", &val)) {
597*4882a593Smuzhiyun if (val > IQS269_CHx_ENG_A_PROJ_BIAS_MAX) {
598*4882a593Smuzhiyun dev_err(&client->dev,
599*4882a593Smuzhiyun "Invalid channel %u bias current: %u\n", reg,
600*4882a593Smuzhiyun val);
601*4882a593Smuzhiyun return -EINVAL;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun engine_a &= ~IQS269_CHx_ENG_A_PROJ_BIAS_MASK;
605*4882a593Smuzhiyun engine_a |= (val << IQS269_CHx_ENG_A_PROJ_BIAS_SHIFT);
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun if (!fwnode_property_read_u32(ch_node, "azoteq,sense-mode", &val)) {
609*4882a593Smuzhiyun if (val > IQS269_CHx_ENG_A_SENSE_MODE_MAX) {
610*4882a593Smuzhiyun dev_err(&client->dev,
611*4882a593Smuzhiyun "Invalid channel %u sensing mode: %u\n", reg,
612*4882a593Smuzhiyun val);
613*4882a593Smuzhiyun return -EINVAL;
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun engine_a &= ~IQS269_CHx_ENG_A_SENSE_MODE_MASK;
617*4882a593Smuzhiyun engine_a |= val;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun if (!fwnode_property_read_u32(ch_node, "azoteq,sense-freq", &val)) {
621*4882a593Smuzhiyun if (val > IQS269_CHx_ENG_B_SENSE_FREQ_MAX) {
622*4882a593Smuzhiyun dev_err(&client->dev,
623*4882a593Smuzhiyun "Invalid channel %u sensing frequency: %u\n",
624*4882a593Smuzhiyun reg, val);
625*4882a593Smuzhiyun return -EINVAL;
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun engine_b &= ~IQS269_CHx_ENG_B_SENSE_FREQ_MASK;
629*4882a593Smuzhiyun engine_b |= (val << IQS269_CHx_ENG_B_SENSE_FREQ_SHIFT);
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun engine_b &= ~IQS269_CHx_ENG_B_STATIC_ENABLE;
633*4882a593Smuzhiyun if (fwnode_property_present(ch_node, "azoteq,static-enable"))
634*4882a593Smuzhiyun engine_b |= IQS269_CHx_ENG_B_STATIC_ENABLE;
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun ch_reg->engine_a = cpu_to_be16(engine_a);
637*4882a593Smuzhiyun ch_reg->engine_b = cpu_to_be16(engine_b);
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun if (!fwnode_property_read_u32(ch_node, "azoteq,ati-mode", &val)) {
640*4882a593Smuzhiyun error = iqs269_ati_mode_set(iqs269, reg, val);
641*4882a593Smuzhiyun if (error) {
642*4882a593Smuzhiyun dev_err(&client->dev,
643*4882a593Smuzhiyun "Invalid channel %u ATI mode: %u\n", reg, val);
644*4882a593Smuzhiyun return error;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun if (!fwnode_property_read_u32(ch_node, "azoteq,ati-base", &val)) {
649*4882a593Smuzhiyun error = iqs269_ati_base_set(iqs269, reg, val);
650*4882a593Smuzhiyun if (error) {
651*4882a593Smuzhiyun dev_err(&client->dev,
652*4882a593Smuzhiyun "Invalid channel %u ATI base: %u\n", reg, val);
653*4882a593Smuzhiyun return error;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun if (!fwnode_property_read_u32(ch_node, "azoteq,ati-target", &val)) {
658*4882a593Smuzhiyun error = iqs269_ati_target_set(iqs269, reg, val);
659*4882a593Smuzhiyun if (error) {
660*4882a593Smuzhiyun dev_err(&client->dev,
661*4882a593Smuzhiyun "Invalid channel %u ATI target: %u\n", reg,
662*4882a593Smuzhiyun val);
663*4882a593Smuzhiyun return error;
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun error = iqs269_parse_mask(ch_node, "azoteq,assoc-select",
668*4882a593Smuzhiyun &ch_reg->assoc_select);
669*4882a593Smuzhiyun if (error) {
670*4882a593Smuzhiyun dev_err(&client->dev, "Invalid channel %u association: %d\n",
671*4882a593Smuzhiyun reg, error);
672*4882a593Smuzhiyun return error;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun if (!fwnode_property_read_u32(ch_node, "azoteq,assoc-weight", &val)) {
676*4882a593Smuzhiyun if (val > IQS269_CHx_WEIGHT_MAX) {
677*4882a593Smuzhiyun dev_err(&client->dev,
678*4882a593Smuzhiyun "Invalid channel %u associated weight: %u\n",
679*4882a593Smuzhiyun reg, val);
680*4882a593Smuzhiyun return -EINVAL;
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun ch_reg->assoc_weight = val;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(iqs269_events); i++) {
687*4882a593Smuzhiyun ev_node = fwnode_get_named_child_node(ch_node,
688*4882a593Smuzhiyun iqs269_events[i].name);
689*4882a593Smuzhiyun if (!ev_node)
690*4882a593Smuzhiyun continue;
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun if (!fwnode_property_read_u32(ev_node, "azoteq,thresh", &val)) {
693*4882a593Smuzhiyun if (val > IQS269_CHx_THRESH_MAX) {
694*4882a593Smuzhiyun dev_err(&client->dev,
695*4882a593Smuzhiyun "Invalid channel %u threshold: %u\n",
696*4882a593Smuzhiyun reg, val);
697*4882a593Smuzhiyun return -EINVAL;
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun ch_reg->thresh[iqs269_events[i].th_offs] = val;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun if (!fwnode_property_read_u32(ev_node, "azoteq,hyst", &val)) {
704*4882a593Smuzhiyun u8 *hyst = &ch_reg->hyst;
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun if (val > IQS269_CHx_HYST_MAX) {
707*4882a593Smuzhiyun dev_err(&client->dev,
708*4882a593Smuzhiyun "Invalid channel %u hysteresis: %u\n",
709*4882a593Smuzhiyun reg, val);
710*4882a593Smuzhiyun return -EINVAL;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun if (i == IQS269_EVENT_DEEP_DN ||
714*4882a593Smuzhiyun i == IQS269_EVENT_DEEP_UP) {
715*4882a593Smuzhiyun *hyst &= ~IQS269_CHx_HYST_DEEP_MASK;
716*4882a593Smuzhiyun *hyst |= (val << IQS269_CHx_HYST_DEEP_SHIFT);
717*4882a593Smuzhiyun } else if (i == IQS269_EVENT_TOUCH_DN ||
718*4882a593Smuzhiyun i == IQS269_EVENT_TOUCH_UP) {
719*4882a593Smuzhiyun *hyst &= ~IQS269_CHx_HYST_TOUCH_MASK;
720*4882a593Smuzhiyun *hyst |= val;
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun if (fwnode_property_read_u32(ev_node, "linux,code", &val))
725*4882a593Smuzhiyun continue;
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun switch (reg) {
728*4882a593Smuzhiyun case IQS269_CHx_HALL_ACTIVE:
729*4882a593Smuzhiyun if (iqs269->hall_enable) {
730*4882a593Smuzhiyun iqs269->switches[i].code = val;
731*4882a593Smuzhiyun iqs269->switches[i].enabled = true;
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun fallthrough;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun case IQS269_CHx_HALL_INACTIVE:
736*4882a593Smuzhiyun if (iqs269->hall_enable)
737*4882a593Smuzhiyun break;
738*4882a593Smuzhiyun fallthrough;
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun default:
741*4882a593Smuzhiyun iqs269->keycode[i * IQS269_NUM_CH + reg] = val;
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun iqs269->sys_reg.event_mask &= ~iqs269_events[i].mask;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun return 0;
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun
iqs269_parse_prop(struct iqs269_private * iqs269)750*4882a593Smuzhiyun static int iqs269_parse_prop(struct iqs269_private *iqs269)
751*4882a593Smuzhiyun {
752*4882a593Smuzhiyun struct iqs269_sys_reg *sys_reg = &iqs269->sys_reg;
753*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
754*4882a593Smuzhiyun struct fwnode_handle *ch_node;
755*4882a593Smuzhiyun u16 general, misc_a, misc_b;
756*4882a593Smuzhiyun unsigned int val;
757*4882a593Smuzhiyun int error;
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun iqs269->hall_enable = device_property_present(&client->dev,
760*4882a593Smuzhiyun "azoteq,hall-enable");
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,suspend-mode",
763*4882a593Smuzhiyun &val)) {
764*4882a593Smuzhiyun if (val > IQS269_SYS_SETTINGS_PWR_MODE_MAX) {
765*4882a593Smuzhiyun dev_err(&client->dev, "Invalid suspend mode: %u\n",
766*4882a593Smuzhiyun val);
767*4882a593Smuzhiyun return -EINVAL;
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun iqs269->suspend_mode = val;
771*4882a593Smuzhiyun }
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun error = regmap_raw_read(iqs269->regmap, IQS269_SYS_SETTINGS, sys_reg,
774*4882a593Smuzhiyun sizeof(*sys_reg));
775*4882a593Smuzhiyun if (error)
776*4882a593Smuzhiyun return error;
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,filt-str-lp-lta",
779*4882a593Smuzhiyun &val)) {
780*4882a593Smuzhiyun if (val > IQS269_FILT_STR_MAX) {
781*4882a593Smuzhiyun dev_err(&client->dev, "Invalid filter strength: %u\n",
782*4882a593Smuzhiyun val);
783*4882a593Smuzhiyun return -EINVAL;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun sys_reg->filter &= ~IQS269_FILT_STR_LP_LTA_MASK;
787*4882a593Smuzhiyun sys_reg->filter |= (val << IQS269_FILT_STR_LP_LTA_SHIFT);
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,filt-str-lp-cnt",
791*4882a593Smuzhiyun &val)) {
792*4882a593Smuzhiyun if (val > IQS269_FILT_STR_MAX) {
793*4882a593Smuzhiyun dev_err(&client->dev, "Invalid filter strength: %u\n",
794*4882a593Smuzhiyun val);
795*4882a593Smuzhiyun return -EINVAL;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun sys_reg->filter &= ~IQS269_FILT_STR_LP_CNT_MASK;
799*4882a593Smuzhiyun sys_reg->filter |= (val << IQS269_FILT_STR_LP_CNT_SHIFT);
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,filt-str-np-lta",
803*4882a593Smuzhiyun &val)) {
804*4882a593Smuzhiyun if (val > IQS269_FILT_STR_MAX) {
805*4882a593Smuzhiyun dev_err(&client->dev, "Invalid filter strength: %u\n",
806*4882a593Smuzhiyun val);
807*4882a593Smuzhiyun return -EINVAL;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun sys_reg->filter &= ~IQS269_FILT_STR_NP_LTA_MASK;
811*4882a593Smuzhiyun sys_reg->filter |= (val << IQS269_FILT_STR_NP_LTA_SHIFT);
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,filt-str-np-cnt",
815*4882a593Smuzhiyun &val)) {
816*4882a593Smuzhiyun if (val > IQS269_FILT_STR_MAX) {
817*4882a593Smuzhiyun dev_err(&client->dev, "Invalid filter strength: %u\n",
818*4882a593Smuzhiyun val);
819*4882a593Smuzhiyun return -EINVAL;
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun sys_reg->filter &= ~IQS269_FILT_STR_NP_CNT_MASK;
823*4882a593Smuzhiyun sys_reg->filter |= val;
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,rate-np-ms",
827*4882a593Smuzhiyun &val)) {
828*4882a593Smuzhiyun if (val > IQS269_RATE_NP_MS_MAX) {
829*4882a593Smuzhiyun dev_err(&client->dev, "Invalid report rate: %u\n", val);
830*4882a593Smuzhiyun return -EINVAL;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun sys_reg->rate_np = val;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,rate-lp-ms",
837*4882a593Smuzhiyun &val)) {
838*4882a593Smuzhiyun if (val > IQS269_RATE_LP_MS_MAX) {
839*4882a593Smuzhiyun dev_err(&client->dev, "Invalid report rate: %u\n", val);
840*4882a593Smuzhiyun return -EINVAL;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun sys_reg->rate_lp = val;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,rate-ulp-ms",
847*4882a593Smuzhiyun &val)) {
848*4882a593Smuzhiyun if (val > IQS269_RATE_ULP_MS_MAX) {
849*4882a593Smuzhiyun dev_err(&client->dev, "Invalid report rate: %u\n", val);
850*4882a593Smuzhiyun return -EINVAL;
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun sys_reg->rate_ulp = val / 16;
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,timeout-pwr-ms",
857*4882a593Smuzhiyun &val)) {
858*4882a593Smuzhiyun if (val > IQS269_TIMEOUT_PWR_MS_MAX) {
859*4882a593Smuzhiyun dev_err(&client->dev, "Invalid timeout: %u\n", val);
860*4882a593Smuzhiyun return -EINVAL;
861*4882a593Smuzhiyun }
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun sys_reg->timeout_pwr = val / 512;
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,timeout-lta-ms",
867*4882a593Smuzhiyun &val)) {
868*4882a593Smuzhiyun if (val > IQS269_TIMEOUT_LTA_MS_MAX) {
869*4882a593Smuzhiyun dev_err(&client->dev, "Invalid timeout: %u\n", val);
870*4882a593Smuzhiyun return -EINVAL;
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun sys_reg->timeout_lta = val / 512;
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun misc_a = be16_to_cpu(sys_reg->misc_a);
877*4882a593Smuzhiyun misc_b = be16_to_cpu(sys_reg->misc_b);
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun misc_a &= ~IQS269_MISC_A_ATI_BAND_DISABLE;
880*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,ati-band-disable"))
881*4882a593Smuzhiyun misc_a |= IQS269_MISC_A_ATI_BAND_DISABLE;
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun misc_a &= ~IQS269_MISC_A_ATI_LP_ONLY;
884*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,ati-lp-only"))
885*4882a593Smuzhiyun misc_a |= IQS269_MISC_A_ATI_LP_ONLY;
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun misc_a &= ~IQS269_MISC_A_ATI_BAND_TIGHTEN;
888*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,ati-band-tighten"))
889*4882a593Smuzhiyun misc_a |= IQS269_MISC_A_ATI_BAND_TIGHTEN;
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun misc_a &= ~IQS269_MISC_A_FILT_DISABLE;
892*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,filt-disable"))
893*4882a593Smuzhiyun misc_a |= IQS269_MISC_A_FILT_DISABLE;
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,gpio3-select",
896*4882a593Smuzhiyun &val)) {
897*4882a593Smuzhiyun if (val >= IQS269_NUM_CH) {
898*4882a593Smuzhiyun dev_err(&client->dev, "Invalid GPIO3 selection: %u\n",
899*4882a593Smuzhiyun val);
900*4882a593Smuzhiyun return -EINVAL;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun misc_a &= ~IQS269_MISC_A_GPIO3_SELECT_MASK;
904*4882a593Smuzhiyun misc_a |= (val << IQS269_MISC_A_GPIO3_SELECT_SHIFT);
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun misc_a &= ~IQS269_MISC_A_DUAL_DIR;
908*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,dual-direction"))
909*4882a593Smuzhiyun misc_a |= IQS269_MISC_A_DUAL_DIR;
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,tx-freq", &val)) {
912*4882a593Smuzhiyun if (val > IQS269_MISC_A_TX_FREQ_MAX) {
913*4882a593Smuzhiyun dev_err(&client->dev,
914*4882a593Smuzhiyun "Invalid excitation frequency: %u\n", val);
915*4882a593Smuzhiyun return -EINVAL;
916*4882a593Smuzhiyun }
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun misc_a &= ~IQS269_MISC_A_TX_FREQ_MASK;
919*4882a593Smuzhiyun misc_a |= (val << IQS269_MISC_A_TX_FREQ_SHIFT);
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun misc_a &= ~IQS269_MISC_A_GLOBAL_CAP_SIZE;
923*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,global-cap-increase"))
924*4882a593Smuzhiyun misc_a |= IQS269_MISC_A_GLOBAL_CAP_SIZE;
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,reseed-select",
927*4882a593Smuzhiyun &val)) {
928*4882a593Smuzhiyun if (val > IQS269_MISC_B_RESEED_UI_SEL_MAX) {
929*4882a593Smuzhiyun dev_err(&client->dev, "Invalid reseed selection: %u\n",
930*4882a593Smuzhiyun val);
931*4882a593Smuzhiyun return -EINVAL;
932*4882a593Smuzhiyun }
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun misc_b &= ~IQS269_MISC_B_RESEED_UI_SEL_MASK;
935*4882a593Smuzhiyun misc_b |= (val << IQS269_MISC_B_RESEED_UI_SEL_SHIFT);
936*4882a593Smuzhiyun }
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun misc_b &= ~IQS269_MISC_B_TRACKING_UI_ENABLE;
939*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,tracking-enable"))
940*4882a593Smuzhiyun misc_b |= IQS269_MISC_B_TRACKING_UI_ENABLE;
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,filt-str-slider",
943*4882a593Smuzhiyun &val)) {
944*4882a593Smuzhiyun if (val > IQS269_FILT_STR_MAX) {
945*4882a593Smuzhiyun dev_err(&client->dev, "Invalid filter strength: %u\n",
946*4882a593Smuzhiyun val);
947*4882a593Smuzhiyun return -EINVAL;
948*4882a593Smuzhiyun }
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun misc_b &= ~IQS269_MISC_B_FILT_STR_SLIDER;
951*4882a593Smuzhiyun misc_b |= val;
952*4882a593Smuzhiyun }
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun sys_reg->misc_a = cpu_to_be16(misc_a);
955*4882a593Smuzhiyun sys_reg->misc_b = cpu_to_be16(misc_b);
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun sys_reg->active = 0;
958*4882a593Smuzhiyun sys_reg->reseed = 0;
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun sys_reg->blocking = 0;
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun sys_reg->slider_select[0] = 0;
963*4882a593Smuzhiyun sys_reg->slider_select[1] = 0;
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun sys_reg->event_mask = ~((u8)IQS269_EVENT_MASK_SYS);
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun device_for_each_child_node(&client->dev, ch_node) {
968*4882a593Smuzhiyun error = iqs269_parse_chan(iqs269, ch_node);
969*4882a593Smuzhiyun if (error) {
970*4882a593Smuzhiyun fwnode_handle_put(ch_node);
971*4882a593Smuzhiyun return error;
972*4882a593Smuzhiyun }
973*4882a593Smuzhiyun }
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun /*
976*4882a593Smuzhiyun * Volunteer all active channels to participate in ATI when REDO-ATI is
977*4882a593Smuzhiyun * manually triggered.
978*4882a593Smuzhiyun */
979*4882a593Smuzhiyun sys_reg->redo_ati = sys_reg->active;
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun general = be16_to_cpu(sys_reg->general);
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,clk-div")) {
984*4882a593Smuzhiyun general |= IQS269_SYS_SETTINGS_CLK_DIV;
985*4882a593Smuzhiyun iqs269->delay_mult = 4;
986*4882a593Smuzhiyun } else {
987*4882a593Smuzhiyun general &= ~IQS269_SYS_SETTINGS_CLK_DIV;
988*4882a593Smuzhiyun iqs269->delay_mult = 1;
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun /*
992*4882a593Smuzhiyun * Configure the device to automatically switch between normal and low-
993*4882a593Smuzhiyun * power modes as a function of sensing activity. Ultra-low-power mode,
994*4882a593Smuzhiyun * if enabled, is reserved for suspend.
995*4882a593Smuzhiyun */
996*4882a593Smuzhiyun general &= ~IQS269_SYS_SETTINGS_ULP_AUTO;
997*4882a593Smuzhiyun general &= ~IQS269_SYS_SETTINGS_DIS_AUTO;
998*4882a593Smuzhiyun general &= ~IQS269_SYS_SETTINGS_PWR_MODE_MASK;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun if (!device_property_read_u32(&client->dev, "azoteq,ulp-update",
1001*4882a593Smuzhiyun &val)) {
1002*4882a593Smuzhiyun if (val > IQS269_SYS_SETTINGS_ULP_UPDATE_MAX) {
1003*4882a593Smuzhiyun dev_err(&client->dev, "Invalid update rate: %u\n", val);
1004*4882a593Smuzhiyun return -EINVAL;
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun general &= ~IQS269_SYS_SETTINGS_ULP_UPDATE_MASK;
1008*4882a593Smuzhiyun general |= (val << IQS269_SYS_SETTINGS_ULP_UPDATE_SHIFT);
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun general &= ~IQS269_SYS_SETTINGS_RESEED_OFFSET;
1012*4882a593Smuzhiyun if (device_property_present(&client->dev, "azoteq,reseed-offset"))
1013*4882a593Smuzhiyun general |= IQS269_SYS_SETTINGS_RESEED_OFFSET;
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun general |= IQS269_SYS_SETTINGS_EVENT_MODE;
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun /*
1018*4882a593Smuzhiyun * As per the datasheet, enable streaming during normal-power mode if
1019*4882a593Smuzhiyun * either slider is in use. In that case, the device returns to event
1020*4882a593Smuzhiyun * mode during low-power mode.
1021*4882a593Smuzhiyun */
1022*4882a593Smuzhiyun if (sys_reg->slider_select[0] || sys_reg->slider_select[1])
1023*4882a593Smuzhiyun general |= IQS269_SYS_SETTINGS_EVENT_MODE_LP;
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun general |= IQS269_SYS_SETTINGS_REDO_ATI;
1026*4882a593Smuzhiyun general |= IQS269_SYS_SETTINGS_ACK_RESET;
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun sys_reg->general = cpu_to_be16(general);
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun return 0;
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun
iqs269_dev_init(struct iqs269_private * iqs269)1033*4882a593Smuzhiyun static int iqs269_dev_init(struct iqs269_private *iqs269)
1034*4882a593Smuzhiyun {
1035*4882a593Smuzhiyun struct iqs269_sys_reg *sys_reg = &iqs269->sys_reg;
1036*4882a593Smuzhiyun struct iqs269_ch_reg *ch_reg;
1037*4882a593Smuzhiyun unsigned int val;
1038*4882a593Smuzhiyun int error, i;
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun error = regmap_update_bits(iqs269->regmap, IQS269_HALL_UI,
1043*4882a593Smuzhiyun IQS269_HALL_UI_ENABLE,
1044*4882a593Smuzhiyun iqs269->hall_enable ? ~0 : 0);
1045*4882a593Smuzhiyun if (error)
1046*4882a593Smuzhiyun goto err_mutex;
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun for (i = 0; i < IQS269_NUM_CH; i++) {
1049*4882a593Smuzhiyun if (!(sys_reg->active & BIT(i)))
1050*4882a593Smuzhiyun continue;
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun ch_reg = &iqs269->ch_reg[i];
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun error = regmap_raw_write(iqs269->regmap,
1055*4882a593Smuzhiyun IQS269_CHx_SETTINGS + i *
1056*4882a593Smuzhiyun sizeof(*ch_reg) / 2, ch_reg,
1057*4882a593Smuzhiyun sizeof(*ch_reg));
1058*4882a593Smuzhiyun if (error)
1059*4882a593Smuzhiyun goto err_mutex;
1060*4882a593Smuzhiyun }
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun /*
1063*4882a593Smuzhiyun * The REDO-ATI and ATI channel selection fields must be written in the
1064*4882a593Smuzhiyun * same block write, so every field between registers 0x80 through 0x8B
1065*4882a593Smuzhiyun * (inclusive) must be written as well.
1066*4882a593Smuzhiyun */
1067*4882a593Smuzhiyun error = regmap_raw_write(iqs269->regmap, IQS269_SYS_SETTINGS, sys_reg,
1068*4882a593Smuzhiyun sizeof(*sys_reg));
1069*4882a593Smuzhiyun if (error)
1070*4882a593Smuzhiyun goto err_mutex;
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun error = regmap_read_poll_timeout(iqs269->regmap, IQS269_SYS_FLAGS, val,
1073*4882a593Smuzhiyun !(val & IQS269_SYS_FLAGS_IN_ATI),
1074*4882a593Smuzhiyun IQS269_ATI_POLL_SLEEP_US,
1075*4882a593Smuzhiyun IQS269_ATI_POLL_TIMEOUT_US);
1076*4882a593Smuzhiyun if (error)
1077*4882a593Smuzhiyun goto err_mutex;
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun msleep(IQS269_ATI_STABLE_DELAY_MS);
1080*4882a593Smuzhiyun iqs269->ati_current = true;
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun err_mutex:
1083*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun return error;
1086*4882a593Smuzhiyun }
1087*4882a593Smuzhiyun
iqs269_input_init(struct iqs269_private * iqs269)1088*4882a593Smuzhiyun static int iqs269_input_init(struct iqs269_private *iqs269)
1089*4882a593Smuzhiyun {
1090*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
1091*4882a593Smuzhiyun struct iqs269_flags flags;
1092*4882a593Smuzhiyun unsigned int sw_code, keycode;
1093*4882a593Smuzhiyun int error, i, j;
1094*4882a593Smuzhiyun u8 dir_mask, state;
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun iqs269->keypad = devm_input_allocate_device(&client->dev);
1097*4882a593Smuzhiyun if (!iqs269->keypad)
1098*4882a593Smuzhiyun return -ENOMEM;
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun iqs269->keypad->keycodemax = ARRAY_SIZE(iqs269->keycode);
1101*4882a593Smuzhiyun iqs269->keypad->keycode = iqs269->keycode;
1102*4882a593Smuzhiyun iqs269->keypad->keycodesize = sizeof(*iqs269->keycode);
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun iqs269->keypad->name = "iqs269a_keypad";
1105*4882a593Smuzhiyun iqs269->keypad->id.bustype = BUS_I2C;
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun if (iqs269->hall_enable) {
1108*4882a593Smuzhiyun error = regmap_raw_read(iqs269->regmap, IQS269_SYS_FLAGS,
1109*4882a593Smuzhiyun &flags, sizeof(flags));
1110*4882a593Smuzhiyun if (error) {
1111*4882a593Smuzhiyun dev_err(&client->dev,
1112*4882a593Smuzhiyun "Failed to read initial status: %d\n", error);
1113*4882a593Smuzhiyun return error;
1114*4882a593Smuzhiyun }
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(iqs269_events); i++) {
1118*4882a593Smuzhiyun dir_mask = flags.states[IQS269_ST_OFFS_DIR];
1119*4882a593Smuzhiyun if (!iqs269_events[i].dir_up)
1120*4882a593Smuzhiyun dir_mask = ~dir_mask;
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun state = flags.states[iqs269_events[i].st_offs] & dir_mask;
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun sw_code = iqs269->switches[i].code;
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun for (j = 0; j < IQS269_NUM_CH; j++) {
1127*4882a593Smuzhiyun keycode = iqs269->keycode[i * IQS269_NUM_CH + j];
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun /*
1130*4882a593Smuzhiyun * Hall-effect sensing repurposes a pair of dedicated
1131*4882a593Smuzhiyun * channels, only one of which reports events.
1132*4882a593Smuzhiyun */
1133*4882a593Smuzhiyun switch (j) {
1134*4882a593Smuzhiyun case IQS269_CHx_HALL_ACTIVE:
1135*4882a593Smuzhiyun if (iqs269->hall_enable &&
1136*4882a593Smuzhiyun iqs269->switches[i].enabled) {
1137*4882a593Smuzhiyun input_set_capability(iqs269->keypad,
1138*4882a593Smuzhiyun EV_SW, sw_code);
1139*4882a593Smuzhiyun input_report_switch(iqs269->keypad,
1140*4882a593Smuzhiyun sw_code,
1141*4882a593Smuzhiyun state & BIT(j));
1142*4882a593Smuzhiyun }
1143*4882a593Smuzhiyun fallthrough;
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun case IQS269_CHx_HALL_INACTIVE:
1146*4882a593Smuzhiyun if (iqs269->hall_enable)
1147*4882a593Smuzhiyun continue;
1148*4882a593Smuzhiyun fallthrough;
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun default:
1151*4882a593Smuzhiyun if (keycode != KEY_RESERVED)
1152*4882a593Smuzhiyun input_set_capability(iqs269->keypad,
1153*4882a593Smuzhiyun EV_KEY, keycode);
1154*4882a593Smuzhiyun }
1155*4882a593Smuzhiyun }
1156*4882a593Smuzhiyun }
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun input_sync(iqs269->keypad);
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun error = input_register_device(iqs269->keypad);
1161*4882a593Smuzhiyun if (error) {
1162*4882a593Smuzhiyun dev_err(&client->dev, "Failed to register keypad: %d\n", error);
1163*4882a593Smuzhiyun return error;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun for (i = 0; i < IQS269_NUM_SL; i++) {
1167*4882a593Smuzhiyun if (!iqs269->sys_reg.slider_select[i])
1168*4882a593Smuzhiyun continue;
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun iqs269->slider[i] = devm_input_allocate_device(&client->dev);
1171*4882a593Smuzhiyun if (!iqs269->slider[i])
1172*4882a593Smuzhiyun return -ENOMEM;
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun iqs269->slider[i]->name = i ? "iqs269a_slider_1"
1175*4882a593Smuzhiyun : "iqs269a_slider_0";
1176*4882a593Smuzhiyun iqs269->slider[i]->id.bustype = BUS_I2C;
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun input_set_capability(iqs269->slider[i], EV_KEY, BTN_TOUCH);
1179*4882a593Smuzhiyun input_set_abs_params(iqs269->slider[i], ABS_X, 0, 255, 0, 0);
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun error = input_register_device(iqs269->slider[i]);
1182*4882a593Smuzhiyun if (error) {
1183*4882a593Smuzhiyun dev_err(&client->dev,
1184*4882a593Smuzhiyun "Failed to register slider %d: %d\n", i, error);
1185*4882a593Smuzhiyun return error;
1186*4882a593Smuzhiyun }
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun return 0;
1190*4882a593Smuzhiyun }
1191*4882a593Smuzhiyun
iqs269_report(struct iqs269_private * iqs269)1192*4882a593Smuzhiyun static int iqs269_report(struct iqs269_private *iqs269)
1193*4882a593Smuzhiyun {
1194*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
1195*4882a593Smuzhiyun struct iqs269_flags flags;
1196*4882a593Smuzhiyun unsigned int sw_code, keycode;
1197*4882a593Smuzhiyun int error, i, j;
1198*4882a593Smuzhiyun u8 slider_x[IQS269_NUM_SL];
1199*4882a593Smuzhiyun u8 dir_mask, state;
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun error = regmap_raw_read(iqs269->regmap, IQS269_SYS_FLAGS, &flags,
1202*4882a593Smuzhiyun sizeof(flags));
1203*4882a593Smuzhiyun if (error) {
1204*4882a593Smuzhiyun dev_err(&client->dev, "Failed to read device status: %d\n",
1205*4882a593Smuzhiyun error);
1206*4882a593Smuzhiyun return error;
1207*4882a593Smuzhiyun }
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun /*
1210*4882a593Smuzhiyun * The device resets itself if its own watchdog bites, which can happen
1211*4882a593Smuzhiyun * in the event of an I2C communication error. In this case, the device
1212*4882a593Smuzhiyun * asserts a SHOW_RESET interrupt and all registers must be restored.
1213*4882a593Smuzhiyun */
1214*4882a593Smuzhiyun if (be16_to_cpu(flags.system) & IQS269_SYS_FLAGS_SHOW_RESET) {
1215*4882a593Smuzhiyun dev_err(&client->dev, "Unexpected device reset\n");
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun error = iqs269_dev_init(iqs269);
1218*4882a593Smuzhiyun if (error)
1219*4882a593Smuzhiyun dev_err(&client->dev,
1220*4882a593Smuzhiyun "Failed to re-initialize device: %d\n", error);
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun return error;
1223*4882a593Smuzhiyun }
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun error = regmap_raw_read(iqs269->regmap, IQS269_SLIDER_X, slider_x,
1226*4882a593Smuzhiyun sizeof(slider_x));
1227*4882a593Smuzhiyun if (error) {
1228*4882a593Smuzhiyun dev_err(&client->dev, "Failed to read slider position: %d\n",
1229*4882a593Smuzhiyun error);
1230*4882a593Smuzhiyun return error;
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun for (i = 0; i < IQS269_NUM_SL; i++) {
1234*4882a593Smuzhiyun if (!iqs269->sys_reg.slider_select[i])
1235*4882a593Smuzhiyun continue;
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun /*
1238*4882a593Smuzhiyun * Report BTN_TOUCH if any channel that participates in the
1239*4882a593Smuzhiyun * slider is in a state of touch.
1240*4882a593Smuzhiyun */
1241*4882a593Smuzhiyun if (flags.states[IQS269_ST_OFFS_TOUCH] &
1242*4882a593Smuzhiyun iqs269->sys_reg.slider_select[i]) {
1243*4882a593Smuzhiyun input_report_key(iqs269->slider[i], BTN_TOUCH, 1);
1244*4882a593Smuzhiyun input_report_abs(iqs269->slider[i], ABS_X, slider_x[i]);
1245*4882a593Smuzhiyun } else {
1246*4882a593Smuzhiyun input_report_key(iqs269->slider[i], BTN_TOUCH, 0);
1247*4882a593Smuzhiyun }
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun input_sync(iqs269->slider[i]);
1250*4882a593Smuzhiyun }
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(iqs269_events); i++) {
1253*4882a593Smuzhiyun dir_mask = flags.states[IQS269_ST_OFFS_DIR];
1254*4882a593Smuzhiyun if (!iqs269_events[i].dir_up)
1255*4882a593Smuzhiyun dir_mask = ~dir_mask;
1256*4882a593Smuzhiyun
1257*4882a593Smuzhiyun state = flags.states[iqs269_events[i].st_offs] & dir_mask;
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun sw_code = iqs269->switches[i].code;
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun for (j = 0; j < IQS269_NUM_CH; j++) {
1262*4882a593Smuzhiyun keycode = iqs269->keycode[i * IQS269_NUM_CH + j];
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun switch (j) {
1265*4882a593Smuzhiyun case IQS269_CHx_HALL_ACTIVE:
1266*4882a593Smuzhiyun if (iqs269->hall_enable &&
1267*4882a593Smuzhiyun iqs269->switches[i].enabled)
1268*4882a593Smuzhiyun input_report_switch(iqs269->keypad,
1269*4882a593Smuzhiyun sw_code,
1270*4882a593Smuzhiyun state & BIT(j));
1271*4882a593Smuzhiyun fallthrough;
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun case IQS269_CHx_HALL_INACTIVE:
1274*4882a593Smuzhiyun if (iqs269->hall_enable)
1275*4882a593Smuzhiyun continue;
1276*4882a593Smuzhiyun fallthrough;
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun default:
1279*4882a593Smuzhiyun input_report_key(iqs269->keypad, keycode,
1280*4882a593Smuzhiyun state & BIT(j));
1281*4882a593Smuzhiyun }
1282*4882a593Smuzhiyun }
1283*4882a593Smuzhiyun }
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun input_sync(iqs269->keypad);
1286*4882a593Smuzhiyun
1287*4882a593Smuzhiyun return 0;
1288*4882a593Smuzhiyun }
1289*4882a593Smuzhiyun
iqs269_irq(int irq,void * context)1290*4882a593Smuzhiyun static irqreturn_t iqs269_irq(int irq, void *context)
1291*4882a593Smuzhiyun {
1292*4882a593Smuzhiyun struct iqs269_private *iqs269 = context;
1293*4882a593Smuzhiyun
1294*4882a593Smuzhiyun if (iqs269_report(iqs269))
1295*4882a593Smuzhiyun return IRQ_NONE;
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun /*
1298*4882a593Smuzhiyun * The device does not deassert its interrupt (RDY) pin until shortly
1299*4882a593Smuzhiyun * after receiving an I2C stop condition; the following delay ensures
1300*4882a593Smuzhiyun * the interrupt handler does not return before this time.
1301*4882a593Smuzhiyun */
1302*4882a593Smuzhiyun iqs269_irq_wait();
1303*4882a593Smuzhiyun
1304*4882a593Smuzhiyun return IRQ_HANDLED;
1305*4882a593Smuzhiyun }
1306*4882a593Smuzhiyun
counts_show(struct device * dev,struct device_attribute * attr,char * buf)1307*4882a593Smuzhiyun static ssize_t counts_show(struct device *dev,
1308*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1309*4882a593Smuzhiyun {
1310*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1311*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
1312*4882a593Smuzhiyun __le16 counts;
1313*4882a593Smuzhiyun int error;
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun if (!iqs269->ati_current || iqs269->hall_enable)
1316*4882a593Smuzhiyun return -EPERM;
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun /*
1319*4882a593Smuzhiyun * Unsolicited I2C communication prompts the device to assert its RDY
1320*4882a593Smuzhiyun * pin, so disable the interrupt line until the operation is finished
1321*4882a593Smuzhiyun * and RDY has been deasserted.
1322*4882a593Smuzhiyun */
1323*4882a593Smuzhiyun disable_irq(client->irq);
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun error = regmap_raw_read(iqs269->regmap,
1326*4882a593Smuzhiyun IQS269_CHx_COUNTS + iqs269->ch_num * 2,
1327*4882a593Smuzhiyun &counts, sizeof(counts));
1328*4882a593Smuzhiyun
1329*4882a593Smuzhiyun iqs269_irq_wait();
1330*4882a593Smuzhiyun enable_irq(client->irq);
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun if (error)
1333*4882a593Smuzhiyun return error;
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n", le16_to_cpu(counts));
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun
hall_bin_show(struct device * dev,struct device_attribute * attr,char * buf)1338*4882a593Smuzhiyun static ssize_t hall_bin_show(struct device *dev,
1339*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1340*4882a593Smuzhiyun {
1341*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1342*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
1343*4882a593Smuzhiyun unsigned int val;
1344*4882a593Smuzhiyun int error;
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun disable_irq(client->irq);
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun error = regmap_read(iqs269->regmap, IQS269_CAL_DATA_A, &val);
1349*4882a593Smuzhiyun
1350*4882a593Smuzhiyun iqs269_irq_wait();
1351*4882a593Smuzhiyun enable_irq(client->irq);
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun if (error)
1354*4882a593Smuzhiyun return error;
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun switch (iqs269->ch_reg[IQS269_CHx_HALL_ACTIVE].rx_enable &
1357*4882a593Smuzhiyun iqs269->ch_reg[IQS269_CHx_HALL_INACTIVE].rx_enable) {
1358*4882a593Smuzhiyun case IQS269_HALL_PAD_R:
1359*4882a593Smuzhiyun val &= IQS269_CAL_DATA_A_HALL_BIN_R_MASK;
1360*4882a593Smuzhiyun val >>= IQS269_CAL_DATA_A_HALL_BIN_R_SHIFT;
1361*4882a593Smuzhiyun break;
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun case IQS269_HALL_PAD_L:
1364*4882a593Smuzhiyun val &= IQS269_CAL_DATA_A_HALL_BIN_L_MASK;
1365*4882a593Smuzhiyun val >>= IQS269_CAL_DATA_A_HALL_BIN_L_SHIFT;
1366*4882a593Smuzhiyun break;
1367*4882a593Smuzhiyun
1368*4882a593Smuzhiyun default:
1369*4882a593Smuzhiyun return -EINVAL;
1370*4882a593Smuzhiyun }
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n", val);
1373*4882a593Smuzhiyun }
1374*4882a593Smuzhiyun
hall_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1375*4882a593Smuzhiyun static ssize_t hall_enable_show(struct device *dev,
1376*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1377*4882a593Smuzhiyun {
1378*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n", iqs269->hall_enable);
1381*4882a593Smuzhiyun }
1382*4882a593Smuzhiyun
hall_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1383*4882a593Smuzhiyun static ssize_t hall_enable_store(struct device *dev,
1384*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
1385*4882a593Smuzhiyun size_t count)
1386*4882a593Smuzhiyun {
1387*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1388*4882a593Smuzhiyun unsigned int val;
1389*4882a593Smuzhiyun int error;
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun error = kstrtouint(buf, 10, &val);
1392*4882a593Smuzhiyun if (error)
1393*4882a593Smuzhiyun return error;
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun iqs269->hall_enable = val;
1398*4882a593Smuzhiyun iqs269->ati_current = false;
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun return count;
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun
ch_number_show(struct device * dev,struct device_attribute * attr,char * buf)1405*4882a593Smuzhiyun static ssize_t ch_number_show(struct device *dev,
1406*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1407*4882a593Smuzhiyun {
1408*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n", iqs269->ch_num);
1411*4882a593Smuzhiyun }
1412*4882a593Smuzhiyun
ch_number_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1413*4882a593Smuzhiyun static ssize_t ch_number_store(struct device *dev,
1414*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
1415*4882a593Smuzhiyun size_t count)
1416*4882a593Smuzhiyun {
1417*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1418*4882a593Smuzhiyun unsigned int val;
1419*4882a593Smuzhiyun int error;
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun error = kstrtouint(buf, 10, &val);
1422*4882a593Smuzhiyun if (error)
1423*4882a593Smuzhiyun return error;
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun if (val >= IQS269_NUM_CH)
1426*4882a593Smuzhiyun return -EINVAL;
1427*4882a593Smuzhiyun
1428*4882a593Smuzhiyun iqs269->ch_num = val;
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun return count;
1431*4882a593Smuzhiyun }
1432*4882a593Smuzhiyun
rx_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1433*4882a593Smuzhiyun static ssize_t rx_enable_show(struct device *dev,
1434*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1435*4882a593Smuzhiyun {
1436*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n",
1439*4882a593Smuzhiyun iqs269->ch_reg[iqs269->ch_num].rx_enable);
1440*4882a593Smuzhiyun }
1441*4882a593Smuzhiyun
rx_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1442*4882a593Smuzhiyun static ssize_t rx_enable_store(struct device *dev,
1443*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
1444*4882a593Smuzhiyun size_t count)
1445*4882a593Smuzhiyun {
1446*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1447*4882a593Smuzhiyun unsigned int val;
1448*4882a593Smuzhiyun int error;
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun error = kstrtouint(buf, 10, &val);
1451*4882a593Smuzhiyun if (error)
1452*4882a593Smuzhiyun return error;
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun if (val > 0xFF)
1455*4882a593Smuzhiyun return -EINVAL;
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun mutex_lock(&iqs269->lock);
1458*4882a593Smuzhiyun
1459*4882a593Smuzhiyun iqs269->ch_reg[iqs269->ch_num].rx_enable = val;
1460*4882a593Smuzhiyun iqs269->ati_current = false;
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun mutex_unlock(&iqs269->lock);
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun return count;
1465*4882a593Smuzhiyun }
1466*4882a593Smuzhiyun
ati_mode_show(struct device * dev,struct device_attribute * attr,char * buf)1467*4882a593Smuzhiyun static ssize_t ati_mode_show(struct device *dev,
1468*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1469*4882a593Smuzhiyun {
1470*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1471*4882a593Smuzhiyun unsigned int val;
1472*4882a593Smuzhiyun int error;
1473*4882a593Smuzhiyun
1474*4882a593Smuzhiyun error = iqs269_ati_mode_get(iqs269, iqs269->ch_num, &val);
1475*4882a593Smuzhiyun if (error)
1476*4882a593Smuzhiyun return error;
1477*4882a593Smuzhiyun
1478*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n", val);
1479*4882a593Smuzhiyun }
1480*4882a593Smuzhiyun
ati_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1481*4882a593Smuzhiyun static ssize_t ati_mode_store(struct device *dev,
1482*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
1483*4882a593Smuzhiyun size_t count)
1484*4882a593Smuzhiyun {
1485*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1486*4882a593Smuzhiyun unsigned int val;
1487*4882a593Smuzhiyun int error;
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun error = kstrtouint(buf, 10, &val);
1490*4882a593Smuzhiyun if (error)
1491*4882a593Smuzhiyun return error;
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun error = iqs269_ati_mode_set(iqs269, iqs269->ch_num, val);
1494*4882a593Smuzhiyun if (error)
1495*4882a593Smuzhiyun return error;
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun return count;
1498*4882a593Smuzhiyun }
1499*4882a593Smuzhiyun
ati_base_show(struct device * dev,struct device_attribute * attr,char * buf)1500*4882a593Smuzhiyun static ssize_t ati_base_show(struct device *dev,
1501*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1502*4882a593Smuzhiyun {
1503*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1504*4882a593Smuzhiyun unsigned int val;
1505*4882a593Smuzhiyun int error;
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun error = iqs269_ati_base_get(iqs269, iqs269->ch_num, &val);
1508*4882a593Smuzhiyun if (error)
1509*4882a593Smuzhiyun return error;
1510*4882a593Smuzhiyun
1511*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n", val);
1512*4882a593Smuzhiyun }
1513*4882a593Smuzhiyun
ati_base_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1514*4882a593Smuzhiyun static ssize_t ati_base_store(struct device *dev,
1515*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
1516*4882a593Smuzhiyun size_t count)
1517*4882a593Smuzhiyun {
1518*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1519*4882a593Smuzhiyun unsigned int val;
1520*4882a593Smuzhiyun int error;
1521*4882a593Smuzhiyun
1522*4882a593Smuzhiyun error = kstrtouint(buf, 10, &val);
1523*4882a593Smuzhiyun if (error)
1524*4882a593Smuzhiyun return error;
1525*4882a593Smuzhiyun
1526*4882a593Smuzhiyun error = iqs269_ati_base_set(iqs269, iqs269->ch_num, val);
1527*4882a593Smuzhiyun if (error)
1528*4882a593Smuzhiyun return error;
1529*4882a593Smuzhiyun
1530*4882a593Smuzhiyun return count;
1531*4882a593Smuzhiyun }
1532*4882a593Smuzhiyun
ati_target_show(struct device * dev,struct device_attribute * attr,char * buf)1533*4882a593Smuzhiyun static ssize_t ati_target_show(struct device *dev,
1534*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1535*4882a593Smuzhiyun {
1536*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1537*4882a593Smuzhiyun unsigned int val;
1538*4882a593Smuzhiyun int error;
1539*4882a593Smuzhiyun
1540*4882a593Smuzhiyun error = iqs269_ati_target_get(iqs269, iqs269->ch_num, &val);
1541*4882a593Smuzhiyun if (error)
1542*4882a593Smuzhiyun return error;
1543*4882a593Smuzhiyun
1544*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n", val);
1545*4882a593Smuzhiyun }
1546*4882a593Smuzhiyun
ati_target_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1547*4882a593Smuzhiyun static ssize_t ati_target_store(struct device *dev,
1548*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
1549*4882a593Smuzhiyun size_t count)
1550*4882a593Smuzhiyun {
1551*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1552*4882a593Smuzhiyun unsigned int val;
1553*4882a593Smuzhiyun int error;
1554*4882a593Smuzhiyun
1555*4882a593Smuzhiyun error = kstrtouint(buf, 10, &val);
1556*4882a593Smuzhiyun if (error)
1557*4882a593Smuzhiyun return error;
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun error = iqs269_ati_target_set(iqs269, iqs269->ch_num, val);
1560*4882a593Smuzhiyun if (error)
1561*4882a593Smuzhiyun return error;
1562*4882a593Smuzhiyun
1563*4882a593Smuzhiyun return count;
1564*4882a593Smuzhiyun }
1565*4882a593Smuzhiyun
ati_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1566*4882a593Smuzhiyun static ssize_t ati_trigger_show(struct device *dev,
1567*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1568*4882a593Smuzhiyun {
1569*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1570*4882a593Smuzhiyun
1571*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%u\n", iqs269->ati_current);
1572*4882a593Smuzhiyun }
1573*4882a593Smuzhiyun
ati_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1574*4882a593Smuzhiyun static ssize_t ati_trigger_store(struct device *dev,
1575*4882a593Smuzhiyun struct device_attribute *attr, const char *buf,
1576*4882a593Smuzhiyun size_t count)
1577*4882a593Smuzhiyun {
1578*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1579*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
1580*4882a593Smuzhiyun unsigned int val;
1581*4882a593Smuzhiyun int error;
1582*4882a593Smuzhiyun
1583*4882a593Smuzhiyun error = kstrtouint(buf, 10, &val);
1584*4882a593Smuzhiyun if (error)
1585*4882a593Smuzhiyun return error;
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun if (!val)
1588*4882a593Smuzhiyun return count;
1589*4882a593Smuzhiyun
1590*4882a593Smuzhiyun disable_irq(client->irq);
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun error = iqs269_dev_init(iqs269);
1593*4882a593Smuzhiyun
1594*4882a593Smuzhiyun iqs269_irq_wait();
1595*4882a593Smuzhiyun enable_irq(client->irq);
1596*4882a593Smuzhiyun
1597*4882a593Smuzhiyun if (error)
1598*4882a593Smuzhiyun return error;
1599*4882a593Smuzhiyun
1600*4882a593Smuzhiyun return count;
1601*4882a593Smuzhiyun }
1602*4882a593Smuzhiyun
1603*4882a593Smuzhiyun static DEVICE_ATTR_RO(counts);
1604*4882a593Smuzhiyun static DEVICE_ATTR_RO(hall_bin);
1605*4882a593Smuzhiyun static DEVICE_ATTR_RW(hall_enable);
1606*4882a593Smuzhiyun static DEVICE_ATTR_RW(ch_number);
1607*4882a593Smuzhiyun static DEVICE_ATTR_RW(rx_enable);
1608*4882a593Smuzhiyun static DEVICE_ATTR_RW(ati_mode);
1609*4882a593Smuzhiyun static DEVICE_ATTR_RW(ati_base);
1610*4882a593Smuzhiyun static DEVICE_ATTR_RW(ati_target);
1611*4882a593Smuzhiyun static DEVICE_ATTR_RW(ati_trigger);
1612*4882a593Smuzhiyun
1613*4882a593Smuzhiyun static struct attribute *iqs269_attrs[] = {
1614*4882a593Smuzhiyun &dev_attr_counts.attr,
1615*4882a593Smuzhiyun &dev_attr_hall_bin.attr,
1616*4882a593Smuzhiyun &dev_attr_hall_enable.attr,
1617*4882a593Smuzhiyun &dev_attr_ch_number.attr,
1618*4882a593Smuzhiyun &dev_attr_rx_enable.attr,
1619*4882a593Smuzhiyun &dev_attr_ati_mode.attr,
1620*4882a593Smuzhiyun &dev_attr_ati_base.attr,
1621*4882a593Smuzhiyun &dev_attr_ati_target.attr,
1622*4882a593Smuzhiyun &dev_attr_ati_trigger.attr,
1623*4882a593Smuzhiyun NULL,
1624*4882a593Smuzhiyun };
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun static const struct attribute_group iqs269_attr_group = {
1627*4882a593Smuzhiyun .attrs = iqs269_attrs,
1628*4882a593Smuzhiyun };
1629*4882a593Smuzhiyun
1630*4882a593Smuzhiyun static const struct regmap_config iqs269_regmap_config = {
1631*4882a593Smuzhiyun .reg_bits = 8,
1632*4882a593Smuzhiyun .val_bits = 16,
1633*4882a593Smuzhiyun .max_register = IQS269_MAX_REG,
1634*4882a593Smuzhiyun };
1635*4882a593Smuzhiyun
iqs269_probe(struct i2c_client * client)1636*4882a593Smuzhiyun static int iqs269_probe(struct i2c_client *client)
1637*4882a593Smuzhiyun {
1638*4882a593Smuzhiyun struct iqs269_ver_info ver_info;
1639*4882a593Smuzhiyun struct iqs269_private *iqs269;
1640*4882a593Smuzhiyun int error;
1641*4882a593Smuzhiyun
1642*4882a593Smuzhiyun iqs269 = devm_kzalloc(&client->dev, sizeof(*iqs269), GFP_KERNEL);
1643*4882a593Smuzhiyun if (!iqs269)
1644*4882a593Smuzhiyun return -ENOMEM;
1645*4882a593Smuzhiyun
1646*4882a593Smuzhiyun i2c_set_clientdata(client, iqs269);
1647*4882a593Smuzhiyun iqs269->client = client;
1648*4882a593Smuzhiyun
1649*4882a593Smuzhiyun iqs269->regmap = devm_regmap_init_i2c(client, &iqs269_regmap_config);
1650*4882a593Smuzhiyun if (IS_ERR(iqs269->regmap)) {
1651*4882a593Smuzhiyun error = PTR_ERR(iqs269->regmap);
1652*4882a593Smuzhiyun dev_err(&client->dev, "Failed to initialize register map: %d\n",
1653*4882a593Smuzhiyun error);
1654*4882a593Smuzhiyun return error;
1655*4882a593Smuzhiyun }
1656*4882a593Smuzhiyun
1657*4882a593Smuzhiyun mutex_init(&iqs269->lock);
1658*4882a593Smuzhiyun
1659*4882a593Smuzhiyun error = regmap_raw_read(iqs269->regmap, IQS269_VER_INFO, &ver_info,
1660*4882a593Smuzhiyun sizeof(ver_info));
1661*4882a593Smuzhiyun if (error)
1662*4882a593Smuzhiyun return error;
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun if (ver_info.prod_num != IQS269_VER_INFO_PROD_NUM) {
1665*4882a593Smuzhiyun dev_err(&client->dev, "Unrecognized product number: 0x%02X\n",
1666*4882a593Smuzhiyun ver_info.prod_num);
1667*4882a593Smuzhiyun return -EINVAL;
1668*4882a593Smuzhiyun }
1669*4882a593Smuzhiyun
1670*4882a593Smuzhiyun error = iqs269_parse_prop(iqs269);
1671*4882a593Smuzhiyun if (error)
1672*4882a593Smuzhiyun return error;
1673*4882a593Smuzhiyun
1674*4882a593Smuzhiyun error = iqs269_dev_init(iqs269);
1675*4882a593Smuzhiyun if (error) {
1676*4882a593Smuzhiyun dev_err(&client->dev, "Failed to initialize device: %d\n",
1677*4882a593Smuzhiyun error);
1678*4882a593Smuzhiyun return error;
1679*4882a593Smuzhiyun }
1680*4882a593Smuzhiyun
1681*4882a593Smuzhiyun error = iqs269_input_init(iqs269);
1682*4882a593Smuzhiyun if (error)
1683*4882a593Smuzhiyun return error;
1684*4882a593Smuzhiyun
1685*4882a593Smuzhiyun error = devm_request_threaded_irq(&client->dev, client->irq,
1686*4882a593Smuzhiyun NULL, iqs269_irq, IRQF_ONESHOT,
1687*4882a593Smuzhiyun client->name, iqs269);
1688*4882a593Smuzhiyun if (error) {
1689*4882a593Smuzhiyun dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
1690*4882a593Smuzhiyun return error;
1691*4882a593Smuzhiyun }
1692*4882a593Smuzhiyun
1693*4882a593Smuzhiyun error = devm_device_add_group(&client->dev, &iqs269_attr_group);
1694*4882a593Smuzhiyun if (error)
1695*4882a593Smuzhiyun dev_err(&client->dev, "Failed to add attributes: %d\n", error);
1696*4882a593Smuzhiyun
1697*4882a593Smuzhiyun return error;
1698*4882a593Smuzhiyun }
1699*4882a593Smuzhiyun
iqs269_suspend(struct device * dev)1700*4882a593Smuzhiyun static int __maybe_unused iqs269_suspend(struct device *dev)
1701*4882a593Smuzhiyun {
1702*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1703*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
1704*4882a593Smuzhiyun unsigned int val;
1705*4882a593Smuzhiyun int error;
1706*4882a593Smuzhiyun
1707*4882a593Smuzhiyun if (!iqs269->suspend_mode)
1708*4882a593Smuzhiyun return 0;
1709*4882a593Smuzhiyun
1710*4882a593Smuzhiyun disable_irq(client->irq);
1711*4882a593Smuzhiyun
1712*4882a593Smuzhiyun /*
1713*4882a593Smuzhiyun * Automatic power mode switching must be disabled before the device is
1714*4882a593Smuzhiyun * forced into any particular power mode. In this case, the device will
1715*4882a593Smuzhiyun * transition into normal-power mode.
1716*4882a593Smuzhiyun */
1717*4882a593Smuzhiyun error = regmap_update_bits(iqs269->regmap, IQS269_SYS_SETTINGS,
1718*4882a593Smuzhiyun IQS269_SYS_SETTINGS_DIS_AUTO, ~0);
1719*4882a593Smuzhiyun if (error)
1720*4882a593Smuzhiyun goto err_irq;
1721*4882a593Smuzhiyun
1722*4882a593Smuzhiyun /*
1723*4882a593Smuzhiyun * The following check ensures the device has completed its transition
1724*4882a593Smuzhiyun * into normal-power mode before a manual mode switch is performed.
1725*4882a593Smuzhiyun */
1726*4882a593Smuzhiyun error = regmap_read_poll_timeout(iqs269->regmap, IQS269_SYS_FLAGS, val,
1727*4882a593Smuzhiyun !(val & IQS269_SYS_FLAGS_PWR_MODE_MASK),
1728*4882a593Smuzhiyun IQS269_PWR_MODE_POLL_SLEEP_US,
1729*4882a593Smuzhiyun IQS269_PWR_MODE_POLL_TIMEOUT_US);
1730*4882a593Smuzhiyun if (error)
1731*4882a593Smuzhiyun goto err_irq;
1732*4882a593Smuzhiyun
1733*4882a593Smuzhiyun error = regmap_update_bits(iqs269->regmap, IQS269_SYS_SETTINGS,
1734*4882a593Smuzhiyun IQS269_SYS_SETTINGS_PWR_MODE_MASK,
1735*4882a593Smuzhiyun iqs269->suspend_mode <<
1736*4882a593Smuzhiyun IQS269_SYS_SETTINGS_PWR_MODE_SHIFT);
1737*4882a593Smuzhiyun if (error)
1738*4882a593Smuzhiyun goto err_irq;
1739*4882a593Smuzhiyun
1740*4882a593Smuzhiyun /*
1741*4882a593Smuzhiyun * This last check ensures the device has completed its transition into
1742*4882a593Smuzhiyun * the desired power mode to prevent any spurious interrupts from being
1743*4882a593Smuzhiyun * triggered after iqs269_suspend has already returned.
1744*4882a593Smuzhiyun */
1745*4882a593Smuzhiyun error = regmap_read_poll_timeout(iqs269->regmap, IQS269_SYS_FLAGS, val,
1746*4882a593Smuzhiyun (val & IQS269_SYS_FLAGS_PWR_MODE_MASK)
1747*4882a593Smuzhiyun == (iqs269->suspend_mode <<
1748*4882a593Smuzhiyun IQS269_SYS_FLAGS_PWR_MODE_SHIFT),
1749*4882a593Smuzhiyun IQS269_PWR_MODE_POLL_SLEEP_US,
1750*4882a593Smuzhiyun IQS269_PWR_MODE_POLL_TIMEOUT_US);
1751*4882a593Smuzhiyun
1752*4882a593Smuzhiyun err_irq:
1753*4882a593Smuzhiyun iqs269_irq_wait();
1754*4882a593Smuzhiyun enable_irq(client->irq);
1755*4882a593Smuzhiyun
1756*4882a593Smuzhiyun return error;
1757*4882a593Smuzhiyun }
1758*4882a593Smuzhiyun
iqs269_resume(struct device * dev)1759*4882a593Smuzhiyun static int __maybe_unused iqs269_resume(struct device *dev)
1760*4882a593Smuzhiyun {
1761*4882a593Smuzhiyun struct iqs269_private *iqs269 = dev_get_drvdata(dev);
1762*4882a593Smuzhiyun struct i2c_client *client = iqs269->client;
1763*4882a593Smuzhiyun unsigned int val;
1764*4882a593Smuzhiyun int error;
1765*4882a593Smuzhiyun
1766*4882a593Smuzhiyun if (!iqs269->suspend_mode)
1767*4882a593Smuzhiyun return 0;
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun disable_irq(client->irq);
1770*4882a593Smuzhiyun
1771*4882a593Smuzhiyun error = regmap_update_bits(iqs269->regmap, IQS269_SYS_SETTINGS,
1772*4882a593Smuzhiyun IQS269_SYS_SETTINGS_PWR_MODE_MASK, 0);
1773*4882a593Smuzhiyun if (error)
1774*4882a593Smuzhiyun goto err_irq;
1775*4882a593Smuzhiyun
1776*4882a593Smuzhiyun /*
1777*4882a593Smuzhiyun * This check ensures the device has returned to normal-power mode
1778*4882a593Smuzhiyun * before automatic power mode switching is re-enabled.
1779*4882a593Smuzhiyun */
1780*4882a593Smuzhiyun error = regmap_read_poll_timeout(iqs269->regmap, IQS269_SYS_FLAGS, val,
1781*4882a593Smuzhiyun !(val & IQS269_SYS_FLAGS_PWR_MODE_MASK),
1782*4882a593Smuzhiyun IQS269_PWR_MODE_POLL_SLEEP_US,
1783*4882a593Smuzhiyun IQS269_PWR_MODE_POLL_TIMEOUT_US);
1784*4882a593Smuzhiyun if (error)
1785*4882a593Smuzhiyun goto err_irq;
1786*4882a593Smuzhiyun
1787*4882a593Smuzhiyun error = regmap_update_bits(iqs269->regmap, IQS269_SYS_SETTINGS,
1788*4882a593Smuzhiyun IQS269_SYS_SETTINGS_DIS_AUTO, 0);
1789*4882a593Smuzhiyun if (error)
1790*4882a593Smuzhiyun goto err_irq;
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun /*
1793*4882a593Smuzhiyun * This step reports any events that may have been "swallowed" as a
1794*4882a593Smuzhiyun * result of polling PWR_MODE (which automatically acknowledges any
1795*4882a593Smuzhiyun * pending interrupts).
1796*4882a593Smuzhiyun */
1797*4882a593Smuzhiyun error = iqs269_report(iqs269);
1798*4882a593Smuzhiyun
1799*4882a593Smuzhiyun err_irq:
1800*4882a593Smuzhiyun iqs269_irq_wait();
1801*4882a593Smuzhiyun enable_irq(client->irq);
1802*4882a593Smuzhiyun
1803*4882a593Smuzhiyun return error;
1804*4882a593Smuzhiyun }
1805*4882a593Smuzhiyun
1806*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(iqs269_pm, iqs269_suspend, iqs269_resume);
1807*4882a593Smuzhiyun
1808*4882a593Smuzhiyun static const struct of_device_id iqs269_of_match[] = {
1809*4882a593Smuzhiyun { .compatible = "azoteq,iqs269a" },
1810*4882a593Smuzhiyun { }
1811*4882a593Smuzhiyun };
1812*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, iqs269_of_match);
1813*4882a593Smuzhiyun
1814*4882a593Smuzhiyun static struct i2c_driver iqs269_i2c_driver = {
1815*4882a593Smuzhiyun .driver = {
1816*4882a593Smuzhiyun .name = "iqs269a",
1817*4882a593Smuzhiyun .of_match_table = iqs269_of_match,
1818*4882a593Smuzhiyun .pm = &iqs269_pm,
1819*4882a593Smuzhiyun },
1820*4882a593Smuzhiyun .probe_new = iqs269_probe,
1821*4882a593Smuzhiyun };
1822*4882a593Smuzhiyun module_i2c_driver(iqs269_i2c_driver);
1823*4882a593Smuzhiyun
1824*4882a593Smuzhiyun MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
1825*4882a593Smuzhiyun MODULE_DESCRIPTION("Azoteq IQS269A Capacitive Touch Controller");
1826*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1827