1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014 Broadcom Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
6*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
10*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11*4882a593Smuzhiyun * GNU General Public License for more details.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/bitops.h>
15*4882a593Smuzhiyun #include <linux/clk.h>
16*4882a593Smuzhiyun #include <linux/gfp.h>
17*4882a593Smuzhiyun #include <linux/io.h>
18*4882a593Smuzhiyun #include <linux/input.h>
19*4882a593Smuzhiyun #include <linux/input/matrix_keypad.h>
20*4882a593Smuzhiyun #include <linux/interrupt.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/of.h>
23*4882a593Smuzhiyun #include <linux/platform_device.h>
24*4882a593Smuzhiyun #include <linux/stddef.h>
25*4882a593Smuzhiyun #include <linux/types.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define DEFAULT_CLK_HZ 31250
28*4882a593Smuzhiyun #define MAX_ROWS 8
29*4882a593Smuzhiyun #define MAX_COLS 8
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Register/field definitions */
32*4882a593Smuzhiyun #define KPCR_OFFSET 0x00000080
33*4882a593Smuzhiyun #define KPCR_MODE 0x00000002
34*4882a593Smuzhiyun #define KPCR_MODE_SHIFT 1
35*4882a593Smuzhiyun #define KPCR_MODE_MASK 1
36*4882a593Smuzhiyun #define KPCR_ENABLE 0x00000001
37*4882a593Smuzhiyun #define KPCR_STATUSFILTERENABLE 0x00008000
38*4882a593Smuzhiyun #define KPCR_STATUSFILTERTYPE_SHIFT 12
39*4882a593Smuzhiyun #define KPCR_COLFILTERENABLE 0x00000800
40*4882a593Smuzhiyun #define KPCR_COLFILTERTYPE_SHIFT 8
41*4882a593Smuzhiyun #define KPCR_ROWWIDTH_SHIFT 20
42*4882a593Smuzhiyun #define KPCR_COLUMNWIDTH_SHIFT 16
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define KPIOR_OFFSET 0x00000084
45*4882a593Smuzhiyun #define KPIOR_ROWOCONTRL_SHIFT 24
46*4882a593Smuzhiyun #define KPIOR_ROWOCONTRL_MASK 0xFF000000
47*4882a593Smuzhiyun #define KPIOR_COLUMNOCONTRL_SHIFT 16
48*4882a593Smuzhiyun #define KPIOR_COLUMNOCONTRL_MASK 0x00FF0000
49*4882a593Smuzhiyun #define KPIOR_COLUMN_IO_DATA_SHIFT 0
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define KPEMR0_OFFSET 0x00000090
52*4882a593Smuzhiyun #define KPEMR1_OFFSET 0x00000094
53*4882a593Smuzhiyun #define KPEMR2_OFFSET 0x00000098
54*4882a593Smuzhiyun #define KPEMR3_OFFSET 0x0000009C
55*4882a593Smuzhiyun #define KPEMR_EDGETYPE_BOTH 3
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define KPSSR0_OFFSET 0x000000A0
58*4882a593Smuzhiyun #define KPSSR1_OFFSET 0x000000A4
59*4882a593Smuzhiyun #define KPSSRN_OFFSET(reg_n) (KPSSR0_OFFSET + 4 * (reg_n))
60*4882a593Smuzhiyun #define KPIMR0_OFFSET 0x000000B0
61*4882a593Smuzhiyun #define KPIMR1_OFFSET 0x000000B4
62*4882a593Smuzhiyun #define KPICR0_OFFSET 0x000000B8
63*4882a593Smuzhiyun #define KPICR1_OFFSET 0x000000BC
64*4882a593Smuzhiyun #define KPICRN_OFFSET(reg_n) (KPICR0_OFFSET + 4 * (reg_n))
65*4882a593Smuzhiyun #define KPISR0_OFFSET 0x000000C0
66*4882a593Smuzhiyun #define KPISR1_OFFSET 0x000000C4
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define KPCR_STATUSFILTERTYPE_MAX 7
69*4882a593Smuzhiyun #define KPCR_COLFILTERTYPE_MAX 7
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Macros to determine the row/column from a bit that is set in SSR0/1. */
72*4882a593Smuzhiyun #define BIT_TO_ROW_SSRN(bit_nr, reg_n) (((bit_nr) >> 3) + 4 * (reg_n))
73*4882a593Smuzhiyun #define BIT_TO_COL(bit_nr) ((bit_nr) % 8)
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Structure representing various run-time entities */
76*4882a593Smuzhiyun struct bcm_kp {
77*4882a593Smuzhiyun void __iomem *base;
78*4882a593Smuzhiyun int irq;
79*4882a593Smuzhiyun struct clk *clk;
80*4882a593Smuzhiyun struct input_dev *input_dev;
81*4882a593Smuzhiyun unsigned long last_state[2];
82*4882a593Smuzhiyun unsigned int n_rows;
83*4882a593Smuzhiyun unsigned int n_cols;
84*4882a593Smuzhiyun u32 kpcr;
85*4882a593Smuzhiyun u32 kpior;
86*4882a593Smuzhiyun u32 kpemr;
87*4882a593Smuzhiyun u32 imr0_val;
88*4882a593Smuzhiyun u32 imr1_val;
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun * Returns the keycode from the input device keymap given the row and
93*4882a593Smuzhiyun * column.
94*4882a593Smuzhiyun */
bcm_kp_get_keycode(struct bcm_kp * kp,int row,int col)95*4882a593Smuzhiyun static int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun unsigned int row_shift = get_count_order(kp->n_cols);
98*4882a593Smuzhiyun unsigned short *keymap = kp->input_dev->keycode;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
bcm_kp_report_keys(struct bcm_kp * kp,int reg_num,int pull_mode)103*4882a593Smuzhiyun static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun unsigned long state, change;
106*4882a593Smuzhiyun int bit_nr;
107*4882a593Smuzhiyun int key_press;
108*4882a593Smuzhiyun int row, col;
109*4882a593Smuzhiyun unsigned int keycode;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Clear interrupts */
112*4882a593Smuzhiyun writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num));
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun state = readl(kp->base + KPSSRN_OFFSET(reg_num));
115*4882a593Smuzhiyun change = kp->last_state[reg_num] ^ state;
116*4882a593Smuzhiyun kp->last_state[reg_num] = state;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
119*4882a593Smuzhiyun key_press = state & BIT(bit_nr);
120*4882a593Smuzhiyun /* The meaning of SSR register depends on pull mode. */
121*4882a593Smuzhiyun key_press = pull_mode ? !key_press : key_press;
122*4882a593Smuzhiyun row = BIT_TO_ROW_SSRN(bit_nr, reg_num);
123*4882a593Smuzhiyun col = BIT_TO_COL(bit_nr);
124*4882a593Smuzhiyun keycode = bcm_kp_get_keycode(kp, row, col);
125*4882a593Smuzhiyun input_report_key(kp->input_dev, keycode, key_press);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
bcm_kp_isr_thread(int irq,void * dev_id)129*4882a593Smuzhiyun static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun struct bcm_kp *kp = dev_id;
132*4882a593Smuzhiyun int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
133*4882a593Smuzhiyun int reg_num;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun for (reg_num = 0; reg_num <= 1; reg_num++)
136*4882a593Smuzhiyun bcm_kp_report_keys(kp, reg_num, pull_mode);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun input_sync(kp->input_dev);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return IRQ_HANDLED;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
bcm_kp_start(struct bcm_kp * kp)143*4882a593Smuzhiyun static int bcm_kp_start(struct bcm_kp *kp)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun int error;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun if (kp->clk) {
148*4882a593Smuzhiyun error = clk_prepare_enable(kp->clk);
149*4882a593Smuzhiyun if (error)
150*4882a593Smuzhiyun return error;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun writel(kp->kpior, kp->base + KPIOR_OFFSET);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
156*4882a593Smuzhiyun writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
159*4882a593Smuzhiyun writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
160*4882a593Smuzhiyun writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
161*4882a593Smuzhiyun writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
164*4882a593Smuzhiyun writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
167*4882a593Smuzhiyun kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return 0;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
bcm_kp_stop(const struct bcm_kp * kp)174*4882a593Smuzhiyun static void bcm_kp_stop(const struct bcm_kp *kp)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun u32 val;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun val = readl(kp->base + KPCR_OFFSET);
179*4882a593Smuzhiyun val &= ~KPCR_ENABLE;
180*4882a593Smuzhiyun writel(0, kp->base + KPCR_OFFSET);
181*4882a593Smuzhiyun writel(0, kp->base + KPIMR0_OFFSET);
182*4882a593Smuzhiyun writel(0, kp->base + KPIMR1_OFFSET);
183*4882a593Smuzhiyun writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
184*4882a593Smuzhiyun writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun if (kp->clk)
187*4882a593Smuzhiyun clk_disable_unprepare(kp->clk);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
bcm_kp_open(struct input_dev * dev)190*4882a593Smuzhiyun static int bcm_kp_open(struct input_dev *dev)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun struct bcm_kp *kp = input_get_drvdata(dev);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun return bcm_kp_start(kp);
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
bcm_kp_close(struct input_dev * dev)197*4882a593Smuzhiyun static void bcm_kp_close(struct input_dev *dev)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun struct bcm_kp *kp = input_get_drvdata(dev);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun bcm_kp_stop(kp);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
bcm_kp_matrix_key_parse_dt(struct bcm_kp * kp)204*4882a593Smuzhiyun static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct device *dev = kp->input_dev->dev.parent;
207*4882a593Smuzhiyun struct device_node *np = dev->of_node;
208*4882a593Smuzhiyun int error;
209*4882a593Smuzhiyun unsigned int dt_val;
210*4882a593Smuzhiyun unsigned int i;
211*4882a593Smuzhiyun unsigned int num_rows, col_mask, rows_set;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /* Initialize the KPCR Keypad Configuration Register */
214*4882a593Smuzhiyun kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun error = matrix_keypad_parse_properties(dev, &kp->n_rows, &kp->n_cols);
217*4882a593Smuzhiyun if (error) {
218*4882a593Smuzhiyun dev_err(dev, "failed to parse kp params\n");
219*4882a593Smuzhiyun return error;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /* Set row width for the ASIC block. */
223*4882a593Smuzhiyun kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* Set column width for the ASIC block. */
226*4882a593Smuzhiyun kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /* Configure the IMR registers */
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /*
231*4882a593Smuzhiyun * IMR registers contain interrupt enable bits for 8x8 matrix
232*4882a593Smuzhiyun * IMR0 register format: <row3> <row2> <row1> <row0>
233*4882a593Smuzhiyun * IMR1 register format: <row7> <row6> <row5> <row4>
234*4882a593Smuzhiyun */
235*4882a593Smuzhiyun col_mask = (1 << (kp->n_cols)) - 1;
236*4882a593Smuzhiyun num_rows = kp->n_rows;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun /* Set column bits in rows 0 to 3 in IMR0 */
239*4882a593Smuzhiyun kp->imr0_val = col_mask;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun rows_set = 1;
242*4882a593Smuzhiyun while (--num_rows && rows_set++ < 4)
243*4882a593Smuzhiyun kp->imr0_val |= kp->imr0_val << MAX_COLS;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /* Set column bits in rows 4 to 7 in IMR1 */
246*4882a593Smuzhiyun kp->imr1_val = 0;
247*4882a593Smuzhiyun if (num_rows) {
248*4882a593Smuzhiyun kp->imr1_val = col_mask;
249*4882a593Smuzhiyun while (--num_rows)
250*4882a593Smuzhiyun kp->imr1_val |= kp->imr1_val << MAX_COLS;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* Initialize the KPEMR Keypress Edge Mode Registers */
254*4882a593Smuzhiyun /* Trigger on both edges */
255*4882a593Smuzhiyun kp->kpemr = 0;
256*4882a593Smuzhiyun for (i = 0; i <= 30; i += 2)
257*4882a593Smuzhiyun kp->kpemr |= (KPEMR_EDGETYPE_BOTH << i);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun /*
260*4882a593Smuzhiyun * Obtain the Status filter debounce value and verify against the
261*4882a593Smuzhiyun * possible values specified in the DT binding.
262*4882a593Smuzhiyun */
263*4882a593Smuzhiyun of_property_read_u32(np, "status-debounce-filter-period", &dt_val);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
266*4882a593Smuzhiyun dev_err(dev, "Invalid Status filter debounce value %d\n",
267*4882a593Smuzhiyun dt_val);
268*4882a593Smuzhiyun return -EINVAL;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun /*
274*4882a593Smuzhiyun * Obtain the Column filter debounce value and verify against the
275*4882a593Smuzhiyun * possible values specified in the DT binding.
276*4882a593Smuzhiyun */
277*4882a593Smuzhiyun of_property_read_u32(np, "col-debounce-filter-period", &dt_val);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (dt_val > KPCR_COLFILTERTYPE_MAX) {
280*4882a593Smuzhiyun dev_err(dev, "Invalid Column filter debounce value %d\n",
281*4882a593Smuzhiyun dt_val);
282*4882a593Smuzhiyun return -EINVAL;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /*
288*4882a593Smuzhiyun * Determine between the row and column,
289*4882a593Smuzhiyun * which should be configured as output.
290*4882a593Smuzhiyun */
291*4882a593Smuzhiyun if (of_property_read_bool(np, "row-output-enabled")) {
292*4882a593Smuzhiyun /*
293*4882a593Smuzhiyun * Set RowOContrl or ColumnOContrl in KPIOR
294*4882a593Smuzhiyun * to the number of pins to drive as outputs
295*4882a593Smuzhiyun */
296*4882a593Smuzhiyun kp->kpior = ((1 << kp->n_rows) - 1) <<
297*4882a593Smuzhiyun KPIOR_ROWOCONTRL_SHIFT;
298*4882a593Smuzhiyun } else {
299*4882a593Smuzhiyun kp->kpior = ((1 << kp->n_cols) - 1) <<
300*4882a593Smuzhiyun KPIOR_COLUMNOCONTRL_SHIFT;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /*
304*4882a593Smuzhiyun * Determine if the scan pull up needs to be enabled
305*4882a593Smuzhiyun */
306*4882a593Smuzhiyun if (of_property_read_bool(np, "pull-up-enabled"))
307*4882a593Smuzhiyun kp->kpcr |= KPCR_MODE;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
310*4882a593Smuzhiyun kp->n_rows, kp->n_cols,
311*4882a593Smuzhiyun kp->kpcr, kp->kpior, kp->kpemr);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun return 0;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun
bcm_kp_probe(struct platform_device * pdev)317*4882a593Smuzhiyun static int bcm_kp_probe(struct platform_device *pdev)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun struct bcm_kp *kp;
320*4882a593Smuzhiyun struct input_dev *input_dev;
321*4882a593Smuzhiyun struct resource *res;
322*4882a593Smuzhiyun int error;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL);
325*4882a593Smuzhiyun if (!kp)
326*4882a593Smuzhiyun return -ENOMEM;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun input_dev = devm_input_allocate_device(&pdev->dev);
329*4882a593Smuzhiyun if (!input_dev) {
330*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to allocate the input device\n");
331*4882a593Smuzhiyun return -ENOMEM;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun __set_bit(EV_KEY, input_dev->evbit);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /* Enable auto repeat feature of Linux input subsystem */
337*4882a593Smuzhiyun if (of_property_read_bool(pdev->dev.of_node, "autorepeat"))
338*4882a593Smuzhiyun __set_bit(EV_REP, input_dev->evbit);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun input_dev->name = pdev->name;
341*4882a593Smuzhiyun input_dev->phys = "keypad/input0";
342*4882a593Smuzhiyun input_dev->dev.parent = &pdev->dev;
343*4882a593Smuzhiyun input_dev->open = bcm_kp_open;
344*4882a593Smuzhiyun input_dev->close = bcm_kp_close;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun input_dev->id.bustype = BUS_HOST;
347*4882a593Smuzhiyun input_dev->id.vendor = 0x0001;
348*4882a593Smuzhiyun input_dev->id.product = 0x0001;
349*4882a593Smuzhiyun input_dev->id.version = 0x0100;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun input_set_drvdata(input_dev, kp);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun kp->input_dev = input_dev;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun error = bcm_kp_matrix_key_parse_dt(kp);
356*4882a593Smuzhiyun if (error)
357*4882a593Smuzhiyun return error;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun error = matrix_keypad_build_keymap(NULL, NULL,
360*4882a593Smuzhiyun kp->n_rows, kp->n_cols,
361*4882a593Smuzhiyun NULL, input_dev);
362*4882a593Smuzhiyun if (error) {
363*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to build keymap\n");
364*4882a593Smuzhiyun return error;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /* Get the KEYPAD base address */
368*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
369*4882a593Smuzhiyun if (!res) {
370*4882a593Smuzhiyun dev_err(&pdev->dev, "Missing keypad base address resource\n");
371*4882a593Smuzhiyun return -ENODEV;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun kp->base = devm_ioremap_resource(&pdev->dev, res);
375*4882a593Smuzhiyun if (IS_ERR(kp->base))
376*4882a593Smuzhiyun return PTR_ERR(kp->base);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* Enable clock */
379*4882a593Smuzhiyun kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
380*4882a593Smuzhiyun if (IS_ERR(kp->clk)) {
381*4882a593Smuzhiyun error = PTR_ERR(kp->clk);
382*4882a593Smuzhiyun if (error != -ENOENT) {
383*4882a593Smuzhiyun if (error != -EPROBE_DEFER)
384*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to get clock\n");
385*4882a593Smuzhiyun return error;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun dev_dbg(&pdev->dev,
388*4882a593Smuzhiyun "No clock specified. Assuming it's enabled\n");
389*4882a593Smuzhiyun kp->clk = NULL;
390*4882a593Smuzhiyun } else {
391*4882a593Smuzhiyun unsigned int desired_rate;
392*4882a593Smuzhiyun long actual_rate;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun error = of_property_read_u32(pdev->dev.of_node,
395*4882a593Smuzhiyun "clock-frequency", &desired_rate);
396*4882a593Smuzhiyun if (error < 0)
397*4882a593Smuzhiyun desired_rate = DEFAULT_CLK_HZ;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun actual_rate = clk_round_rate(kp->clk, desired_rate);
400*4882a593Smuzhiyun if (actual_rate <= 0)
401*4882a593Smuzhiyun return -EINVAL;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun error = clk_set_rate(kp->clk, actual_rate);
404*4882a593Smuzhiyun if (error)
405*4882a593Smuzhiyun return error;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun error = clk_prepare_enable(kp->clk);
408*4882a593Smuzhiyun if (error)
409*4882a593Smuzhiyun return error;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun /* Put the kp into a known sane state */
413*4882a593Smuzhiyun bcm_kp_stop(kp);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun kp->irq = platform_get_irq(pdev, 0);
416*4882a593Smuzhiyun if (kp->irq < 0)
417*4882a593Smuzhiyun return -EINVAL;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun error = devm_request_threaded_irq(&pdev->dev, kp->irq,
420*4882a593Smuzhiyun NULL, bcm_kp_isr_thread,
421*4882a593Smuzhiyun IRQF_ONESHOT, pdev->name, kp);
422*4882a593Smuzhiyun if (error) {
423*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to request IRQ\n");
424*4882a593Smuzhiyun return error;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun error = input_register_device(input_dev);
428*4882a593Smuzhiyun if (error) {
429*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to register input device\n");
430*4882a593Smuzhiyun return error;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun return 0;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun static const struct of_device_id bcm_kp_of_match[] = {
437*4882a593Smuzhiyun { .compatible = "brcm,bcm-keypad" },
438*4882a593Smuzhiyun { },
439*4882a593Smuzhiyun };
440*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun static struct platform_driver bcm_kp_device_driver = {
443*4882a593Smuzhiyun .probe = bcm_kp_probe,
444*4882a593Smuzhiyun .driver = {
445*4882a593Smuzhiyun .name = "bcm-keypad",
446*4882a593Smuzhiyun .of_match_table = of_match_ptr(bcm_kp_of_match),
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun };
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun module_platform_driver(bcm_kp_device_driver);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun MODULE_AUTHOR("Broadcom Corporation");
453*4882a593Smuzhiyun MODULE_DESCRIPTION("BCM Keypad Driver");
454*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
455