xref: /OK3568_Linux_fs/kernel/drivers/infiniband/sw/siw/iwarp.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */
4*4882a593Smuzhiyun /* Copyright (c) 2008-2019, IBM Corporation */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _IWARP_H
7*4882a593Smuzhiyun #define _IWARP_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <rdma/rdma_user_cm.h> /* RDMA_MAX_PRIVATE_DATA */
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun #include <asm/byteorder.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define RDMAP_VERSION 1
14*4882a593Smuzhiyun #define DDP_VERSION 1
15*4882a593Smuzhiyun #define MPA_REVISION_1 1
16*4882a593Smuzhiyun #define MPA_REVISION_2 2
17*4882a593Smuzhiyun #define MPA_MAX_PRIVDATA RDMA_MAX_PRIVATE_DATA
18*4882a593Smuzhiyun #define MPA_KEY_REQ "MPA ID Req Frame"
19*4882a593Smuzhiyun #define MPA_KEY_REP "MPA ID Rep Frame"
20*4882a593Smuzhiyun #define MPA_IRD_ORD_MASK 0x3fff
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun struct mpa_rr_params {
23*4882a593Smuzhiyun 	__be16 bits;
24*4882a593Smuzhiyun 	__be16 pd_len;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun  * MPA request/response header bits & fields
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun enum {
31*4882a593Smuzhiyun 	MPA_RR_FLAG_MARKERS = cpu_to_be16(0x8000),
32*4882a593Smuzhiyun 	MPA_RR_FLAG_CRC = cpu_to_be16(0x4000),
33*4882a593Smuzhiyun 	MPA_RR_FLAG_REJECT = cpu_to_be16(0x2000),
34*4882a593Smuzhiyun 	MPA_RR_FLAG_ENHANCED = cpu_to_be16(0x1000),
35*4882a593Smuzhiyun 	MPA_RR_FLAG_GSO_EXP = cpu_to_be16(0x0800),
36*4882a593Smuzhiyun 	MPA_RR_MASK_REVISION = cpu_to_be16(0x00ff)
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun  * MPA request/reply header
41*4882a593Smuzhiyun  */
42*4882a593Smuzhiyun struct mpa_rr {
43*4882a593Smuzhiyun 	__u8 key[16];
44*4882a593Smuzhiyun 	struct mpa_rr_params params;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
__mpa_rr_set_revision(__be16 * bits,u8 rev)47*4882a593Smuzhiyun static inline void __mpa_rr_set_revision(__be16 *bits, u8 rev)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	*bits = (*bits & ~MPA_RR_MASK_REVISION) |
50*4882a593Smuzhiyun 		(cpu_to_be16(rev) & MPA_RR_MASK_REVISION);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
__mpa_rr_revision(__be16 mpa_rr_bits)53*4882a593Smuzhiyun static inline u8 __mpa_rr_revision(__be16 mpa_rr_bits)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	__be16 rev = mpa_rr_bits & MPA_RR_MASK_REVISION;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	return be16_to_cpu(rev);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun enum mpa_v2_ctrl {
61*4882a593Smuzhiyun 	MPA_V2_PEER_TO_PEER = cpu_to_be16(0x8000),
62*4882a593Smuzhiyun 	MPA_V2_ZERO_LENGTH_RTR = cpu_to_be16(0x4000),
63*4882a593Smuzhiyun 	MPA_V2_RDMA_WRITE_RTR = cpu_to_be16(0x8000),
64*4882a593Smuzhiyun 	MPA_V2_RDMA_READ_RTR = cpu_to_be16(0x4000),
65*4882a593Smuzhiyun 	MPA_V2_RDMA_NO_RTR = cpu_to_be16(0x0000),
66*4882a593Smuzhiyun 	MPA_V2_MASK_IRD_ORD = cpu_to_be16(0x3fff)
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun struct mpa_v2_data {
70*4882a593Smuzhiyun 	__be16 ird;
71*4882a593Smuzhiyun 	__be16 ord;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun struct mpa_marker {
75*4882a593Smuzhiyun 	__be16 rsvd;
76*4882a593Smuzhiyun 	__be16 fpdu_hmd; /* FPDU header-marker distance (= MPA's FPDUPTR) */
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun  * maximum MPA trailer
81*4882a593Smuzhiyun  */
82*4882a593Smuzhiyun struct mpa_trailer {
83*4882a593Smuzhiyun 	__u8 pad[4];
84*4882a593Smuzhiyun 	__be32 crc;
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define MPA_HDR_SIZE 2
88*4882a593Smuzhiyun #define MPA_CRC_SIZE 4
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun  * Common portion of iWARP headers (MPA, DDP, RDMAP)
92*4882a593Smuzhiyun  * for any FPDU
93*4882a593Smuzhiyun  */
94*4882a593Smuzhiyun struct iwarp_ctrl {
95*4882a593Smuzhiyun 	__be16 mpa_len;
96*4882a593Smuzhiyun 	__be16 ddp_rdmap_ctrl;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun  * DDP/RDMAP Hdr bits & fields
101*4882a593Smuzhiyun  */
102*4882a593Smuzhiyun enum {
103*4882a593Smuzhiyun 	DDP_FLAG_TAGGED = cpu_to_be16(0x8000),
104*4882a593Smuzhiyun 	DDP_FLAG_LAST = cpu_to_be16(0x4000),
105*4882a593Smuzhiyun 	DDP_MASK_RESERVED = cpu_to_be16(0x3C00),
106*4882a593Smuzhiyun 	DDP_MASK_VERSION = cpu_to_be16(0x0300),
107*4882a593Smuzhiyun 	RDMAP_MASK_VERSION = cpu_to_be16(0x00C0),
108*4882a593Smuzhiyun 	RDMAP_MASK_RESERVED = cpu_to_be16(0x0030),
109*4882a593Smuzhiyun 	RDMAP_MASK_OPCODE = cpu_to_be16(0x000f)
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun 
__ddp_get_version(struct iwarp_ctrl * ctrl)112*4882a593Smuzhiyun static inline u8 __ddp_get_version(struct iwarp_ctrl *ctrl)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	return be16_to_cpu(ctrl->ddp_rdmap_ctrl & DDP_MASK_VERSION) >> 8;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
__ddp_set_version(struct iwarp_ctrl * ctrl,u8 version)117*4882a593Smuzhiyun static inline void __ddp_set_version(struct iwarp_ctrl *ctrl, u8 version)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	ctrl->ddp_rdmap_ctrl =
120*4882a593Smuzhiyun 		(ctrl->ddp_rdmap_ctrl & ~DDP_MASK_VERSION) |
121*4882a593Smuzhiyun 		(cpu_to_be16((u16)version << 8) & DDP_MASK_VERSION);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
__rdmap_get_version(struct iwarp_ctrl * ctrl)124*4882a593Smuzhiyun static inline u8 __rdmap_get_version(struct iwarp_ctrl *ctrl)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun 	__be16 ver = ctrl->ddp_rdmap_ctrl & RDMAP_MASK_VERSION;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	return be16_to_cpu(ver) >> 6;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
__rdmap_set_version(struct iwarp_ctrl * ctrl,u8 version)131*4882a593Smuzhiyun static inline void __rdmap_set_version(struct iwarp_ctrl *ctrl, u8 version)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	ctrl->ddp_rdmap_ctrl = (ctrl->ddp_rdmap_ctrl & ~RDMAP_MASK_VERSION) |
134*4882a593Smuzhiyun 			       (cpu_to_be16(version << 6) & RDMAP_MASK_VERSION);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
__rdmap_get_opcode(struct iwarp_ctrl * ctrl)137*4882a593Smuzhiyun static inline u8 __rdmap_get_opcode(struct iwarp_ctrl *ctrl)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	return be16_to_cpu(ctrl->ddp_rdmap_ctrl & RDMAP_MASK_OPCODE);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
__rdmap_set_opcode(struct iwarp_ctrl * ctrl,u8 opcode)142*4882a593Smuzhiyun static inline void __rdmap_set_opcode(struct iwarp_ctrl *ctrl, u8 opcode)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	ctrl->ddp_rdmap_ctrl = (ctrl->ddp_rdmap_ctrl & ~RDMAP_MASK_OPCODE) |
145*4882a593Smuzhiyun 			       (cpu_to_be16(opcode) & RDMAP_MASK_OPCODE);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun struct iwarp_rdma_write {
149*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
150*4882a593Smuzhiyun 	__be32 sink_stag;
151*4882a593Smuzhiyun 	__be64 sink_to;
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun struct iwarp_rdma_rreq {
155*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
156*4882a593Smuzhiyun 	__be32 rsvd;
157*4882a593Smuzhiyun 	__be32 ddp_qn;
158*4882a593Smuzhiyun 	__be32 ddp_msn;
159*4882a593Smuzhiyun 	__be32 ddp_mo;
160*4882a593Smuzhiyun 	__be32 sink_stag;
161*4882a593Smuzhiyun 	__be64 sink_to;
162*4882a593Smuzhiyun 	__be32 read_size;
163*4882a593Smuzhiyun 	__be32 source_stag;
164*4882a593Smuzhiyun 	__be64 source_to;
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun struct iwarp_rdma_rresp {
168*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
169*4882a593Smuzhiyun 	__be32 sink_stag;
170*4882a593Smuzhiyun 	__be64 sink_to;
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun struct iwarp_send {
174*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
175*4882a593Smuzhiyun 	__be32 rsvd;
176*4882a593Smuzhiyun 	__be32 ddp_qn;
177*4882a593Smuzhiyun 	__be32 ddp_msn;
178*4882a593Smuzhiyun 	__be32 ddp_mo;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun struct iwarp_send_inv {
182*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
183*4882a593Smuzhiyun 	__be32 inval_stag;
184*4882a593Smuzhiyun 	__be32 ddp_qn;
185*4882a593Smuzhiyun 	__be32 ddp_msn;
186*4882a593Smuzhiyun 	__be32 ddp_mo;
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun struct iwarp_terminate {
190*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
191*4882a593Smuzhiyun 	__be32 rsvd;
192*4882a593Smuzhiyun 	__be32 ddp_qn;
193*4882a593Smuzhiyun 	__be32 ddp_msn;
194*4882a593Smuzhiyun 	__be32 ddp_mo;
195*4882a593Smuzhiyun #if defined(__LITTLE_ENDIAN_BITFIELD)
196*4882a593Smuzhiyun 	__be32 layer : 4;
197*4882a593Smuzhiyun 	__be32 etype : 4;
198*4882a593Smuzhiyun 	__be32 ecode : 8;
199*4882a593Smuzhiyun 	__be32 flag_m : 1;
200*4882a593Smuzhiyun 	__be32 flag_d : 1;
201*4882a593Smuzhiyun 	__be32 flag_r : 1;
202*4882a593Smuzhiyun 	__be32 reserved : 13;
203*4882a593Smuzhiyun #elif defined(__BIG_ENDIAN_BITFIELD)
204*4882a593Smuzhiyun 	__be32 reserved : 13;
205*4882a593Smuzhiyun 	__be32 flag_r : 1;
206*4882a593Smuzhiyun 	__be32 flag_d : 1;
207*4882a593Smuzhiyun 	__be32 flag_m : 1;
208*4882a593Smuzhiyun 	__be32 ecode : 8;
209*4882a593Smuzhiyun 	__be32 etype : 4;
210*4882a593Smuzhiyun 	__be32 layer : 4;
211*4882a593Smuzhiyun #else
212*4882a593Smuzhiyun #error "undefined byte order"
213*4882a593Smuzhiyun #endif
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun /*
217*4882a593Smuzhiyun  * Terminate Hdr bits & fields
218*4882a593Smuzhiyun  */
219*4882a593Smuzhiyun enum {
220*4882a593Smuzhiyun 	TERM_MASK_LAYER = cpu_to_be32(0xf0000000),
221*4882a593Smuzhiyun 	TERM_MASK_ETYPE = cpu_to_be32(0x0f000000),
222*4882a593Smuzhiyun 	TERM_MASK_ECODE = cpu_to_be32(0x00ff0000),
223*4882a593Smuzhiyun 	TERM_FLAG_M = cpu_to_be32(0x00008000),
224*4882a593Smuzhiyun 	TERM_FLAG_D = cpu_to_be32(0x00004000),
225*4882a593Smuzhiyun 	TERM_FLAG_R = cpu_to_be32(0x00002000),
226*4882a593Smuzhiyun 	TERM_MASK_RESVD = cpu_to_be32(0x00001fff)
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun 
__rdmap_term_layer(struct iwarp_terminate * term)229*4882a593Smuzhiyun static inline u8 __rdmap_term_layer(struct iwarp_terminate *term)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	return term->layer;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
__rdmap_term_set_layer(struct iwarp_terminate * term,u8 layer)234*4882a593Smuzhiyun static inline void __rdmap_term_set_layer(struct iwarp_terminate *term,
235*4882a593Smuzhiyun 					  u8 layer)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	term->layer = layer & 0xf;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun 
__rdmap_term_etype(struct iwarp_terminate * term)240*4882a593Smuzhiyun static inline u8 __rdmap_term_etype(struct iwarp_terminate *term)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	return term->etype;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun 
__rdmap_term_set_etype(struct iwarp_terminate * term,u8 etype)245*4882a593Smuzhiyun static inline void __rdmap_term_set_etype(struct iwarp_terminate *term,
246*4882a593Smuzhiyun 					  u8 etype)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 	term->etype = etype & 0xf;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun 
__rdmap_term_ecode(struct iwarp_terminate * term)251*4882a593Smuzhiyun static inline u8 __rdmap_term_ecode(struct iwarp_terminate *term)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	return term->ecode;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun 
__rdmap_term_set_ecode(struct iwarp_terminate * term,u8 ecode)256*4882a593Smuzhiyun static inline void __rdmap_term_set_ecode(struct iwarp_terminate *term,
257*4882a593Smuzhiyun 					  u8 ecode)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	term->ecode = ecode;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun /*
263*4882a593Smuzhiyun  * Common portion of iWARP headers (MPA, DDP, RDMAP)
264*4882a593Smuzhiyun  * for an FPDU carrying an untagged DDP segment
265*4882a593Smuzhiyun  */
266*4882a593Smuzhiyun struct iwarp_ctrl_untagged {
267*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
268*4882a593Smuzhiyun 	__be32 rsvd;
269*4882a593Smuzhiyun 	__be32 ddp_qn;
270*4882a593Smuzhiyun 	__be32 ddp_msn;
271*4882a593Smuzhiyun 	__be32 ddp_mo;
272*4882a593Smuzhiyun };
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun /*
275*4882a593Smuzhiyun  * Common portion of iWARP headers (MPA, DDP, RDMAP)
276*4882a593Smuzhiyun  * for an FPDU carrying a tagged DDP segment
277*4882a593Smuzhiyun  */
278*4882a593Smuzhiyun struct iwarp_ctrl_tagged {
279*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
280*4882a593Smuzhiyun 	__be32 ddp_stag;
281*4882a593Smuzhiyun 	__be64 ddp_to;
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun union iwarp_hdr {
285*4882a593Smuzhiyun 	struct iwarp_ctrl ctrl;
286*4882a593Smuzhiyun 	struct iwarp_ctrl_untagged c_untagged;
287*4882a593Smuzhiyun 	struct iwarp_ctrl_tagged c_tagged;
288*4882a593Smuzhiyun 	struct iwarp_rdma_write rwrite;
289*4882a593Smuzhiyun 	struct iwarp_rdma_rreq rreq;
290*4882a593Smuzhiyun 	struct iwarp_rdma_rresp rresp;
291*4882a593Smuzhiyun 	struct iwarp_terminate terminate;
292*4882a593Smuzhiyun 	struct iwarp_send send;
293*4882a593Smuzhiyun 	struct iwarp_send_inv send_inv;
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun enum term_elayer {
297*4882a593Smuzhiyun 	TERM_ERROR_LAYER_RDMAP = 0x00,
298*4882a593Smuzhiyun 	TERM_ERROR_LAYER_DDP = 0x01,
299*4882a593Smuzhiyun 	TERM_ERROR_LAYER_LLP = 0x02 /* eg., MPA */
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun enum ddp_etype {
303*4882a593Smuzhiyun 	DDP_ETYPE_CATASTROPHIC = 0x0,
304*4882a593Smuzhiyun 	DDP_ETYPE_TAGGED_BUF = 0x1,
305*4882a593Smuzhiyun 	DDP_ETYPE_UNTAGGED_BUF = 0x2,
306*4882a593Smuzhiyun 	DDP_ETYPE_RSVD = 0x3
307*4882a593Smuzhiyun };
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun enum ddp_ecode {
310*4882a593Smuzhiyun 	/* unspecified, set to zero */
311*4882a593Smuzhiyun 	DDP_ECODE_CATASTROPHIC = 0x00,
312*4882a593Smuzhiyun 	/* Tagged Buffer Errors */
313*4882a593Smuzhiyun 	DDP_ECODE_T_INVALID_STAG = 0x00,
314*4882a593Smuzhiyun 	DDP_ECODE_T_BASE_BOUNDS = 0x01,
315*4882a593Smuzhiyun 	DDP_ECODE_T_STAG_NOT_ASSOC = 0x02,
316*4882a593Smuzhiyun 	DDP_ECODE_T_TO_WRAP = 0x03,
317*4882a593Smuzhiyun 	DDP_ECODE_T_VERSION = 0x04,
318*4882a593Smuzhiyun 	/* Untagged Buffer Errors */
319*4882a593Smuzhiyun 	DDP_ECODE_UT_INVALID_QN = 0x01,
320*4882a593Smuzhiyun 	DDP_ECODE_UT_INVALID_MSN_NOBUF = 0x02,
321*4882a593Smuzhiyun 	DDP_ECODE_UT_INVALID_MSN_RANGE = 0x03,
322*4882a593Smuzhiyun 	DDP_ECODE_UT_INVALID_MO = 0x04,
323*4882a593Smuzhiyun 	DDP_ECODE_UT_MSG_TOOLONG = 0x05,
324*4882a593Smuzhiyun 	DDP_ECODE_UT_VERSION = 0x06
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun enum rdmap_untagged_qn {
328*4882a593Smuzhiyun 	RDMAP_UNTAGGED_QN_SEND = 0,
329*4882a593Smuzhiyun 	RDMAP_UNTAGGED_QN_RDMA_READ = 1,
330*4882a593Smuzhiyun 	RDMAP_UNTAGGED_QN_TERMINATE = 2,
331*4882a593Smuzhiyun 	RDMAP_UNTAGGED_QN_COUNT = 3
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun enum rdmap_etype {
335*4882a593Smuzhiyun 	RDMAP_ETYPE_CATASTROPHIC = 0x0,
336*4882a593Smuzhiyun 	RDMAP_ETYPE_REMOTE_PROTECTION = 0x1,
337*4882a593Smuzhiyun 	RDMAP_ETYPE_REMOTE_OPERATION = 0x2
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun enum rdmap_ecode {
341*4882a593Smuzhiyun 	RDMAP_ECODE_INVALID_STAG = 0x00,
342*4882a593Smuzhiyun 	RDMAP_ECODE_BASE_BOUNDS = 0x01,
343*4882a593Smuzhiyun 	RDMAP_ECODE_ACCESS_RIGHTS = 0x02,
344*4882a593Smuzhiyun 	RDMAP_ECODE_STAG_NOT_ASSOC = 0x03,
345*4882a593Smuzhiyun 	RDMAP_ECODE_TO_WRAP = 0x04,
346*4882a593Smuzhiyun 	RDMAP_ECODE_VERSION = 0x05,
347*4882a593Smuzhiyun 	RDMAP_ECODE_OPCODE = 0x06,
348*4882a593Smuzhiyun 	RDMAP_ECODE_CATASTROPHIC_STREAM = 0x07,
349*4882a593Smuzhiyun 	RDMAP_ECODE_CATASTROPHIC_GLOBAL = 0x08,
350*4882a593Smuzhiyun 	RDMAP_ECODE_CANNOT_INVALIDATE = 0x09,
351*4882a593Smuzhiyun 	RDMAP_ECODE_UNSPECIFIED = 0xff
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun enum llp_ecode {
355*4882a593Smuzhiyun 	LLP_ECODE_TCP_STREAM_LOST = 0x01, /* How to transfer this ?? */
356*4882a593Smuzhiyun 	LLP_ECODE_RECEIVED_CRC = 0x02,
357*4882a593Smuzhiyun 	LLP_ECODE_FPDU_START = 0x03,
358*4882a593Smuzhiyun 	LLP_ECODE_INVALID_REQ_RESP = 0x04,
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	/* Errors for Enhanced Connection Establishment only */
361*4882a593Smuzhiyun 	LLP_ECODE_LOCAL_CATASTROPHIC = 0x05,
362*4882a593Smuzhiyun 	LLP_ECODE_INSUFFICIENT_IRD = 0x06,
363*4882a593Smuzhiyun 	LLP_ECODE_NO_MATCHING_RTR = 0x07
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun enum llp_etype { LLP_ETYPE_MPA = 0x00 };
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun enum rdma_opcode {
369*4882a593Smuzhiyun 	RDMAP_RDMA_WRITE = 0x0,
370*4882a593Smuzhiyun 	RDMAP_RDMA_READ_REQ = 0x1,
371*4882a593Smuzhiyun 	RDMAP_RDMA_READ_RESP = 0x2,
372*4882a593Smuzhiyun 	RDMAP_SEND = 0x3,
373*4882a593Smuzhiyun 	RDMAP_SEND_INVAL = 0x4,
374*4882a593Smuzhiyun 	RDMAP_SEND_SE = 0x5,
375*4882a593Smuzhiyun 	RDMAP_SEND_SE_INVAL = 0x6,
376*4882a593Smuzhiyun 	RDMAP_TERMINATE = 0x7,
377*4882a593Smuzhiyun 	RDMAP_NOT_SUPPORTED = RDMAP_TERMINATE + 1
378*4882a593Smuzhiyun };
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun #endif
381