1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
4*4882a593Smuzhiyun * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef RXE_PARAM_H
8*4882a593Smuzhiyun #define RXE_PARAM_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <uapi/rdma/rdma_user_rxe.h>
11*4882a593Smuzhiyun
rxe_mtu_int_to_enum(int mtu)12*4882a593Smuzhiyun static inline enum ib_mtu rxe_mtu_int_to_enum(int mtu)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun if (mtu < 256)
15*4882a593Smuzhiyun return 0;
16*4882a593Smuzhiyun else if (mtu < 512)
17*4882a593Smuzhiyun return IB_MTU_256;
18*4882a593Smuzhiyun else if (mtu < 1024)
19*4882a593Smuzhiyun return IB_MTU_512;
20*4882a593Smuzhiyun else if (mtu < 2048)
21*4882a593Smuzhiyun return IB_MTU_1024;
22*4882a593Smuzhiyun else if (mtu < 4096)
23*4882a593Smuzhiyun return IB_MTU_2048;
24*4882a593Smuzhiyun else
25*4882a593Smuzhiyun return IB_MTU_4096;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Find the IB mtu for a given network MTU. */
eth_mtu_int_to_enum(int mtu)29*4882a593Smuzhiyun static inline enum ib_mtu eth_mtu_int_to_enum(int mtu)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun mtu -= RXE_MAX_HDR_LENGTH;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return rxe_mtu_int_to_enum(mtu);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* default/initial rxe device parameter settings */
37*4882a593Smuzhiyun enum rxe_device_param {
38*4882a593Smuzhiyun RXE_MAX_MR_SIZE = -1ull,
39*4882a593Smuzhiyun RXE_PAGE_SIZE_CAP = 0xfffff000,
40*4882a593Smuzhiyun RXE_MAX_QP = 0x10000,
41*4882a593Smuzhiyun RXE_MAX_QP_WR = 0x4000,
42*4882a593Smuzhiyun RXE_DEVICE_CAP_FLAGS = IB_DEVICE_BAD_PKEY_CNTR
43*4882a593Smuzhiyun | IB_DEVICE_BAD_QKEY_CNTR
44*4882a593Smuzhiyun | IB_DEVICE_AUTO_PATH_MIG
45*4882a593Smuzhiyun | IB_DEVICE_CHANGE_PHY_PORT
46*4882a593Smuzhiyun | IB_DEVICE_UD_AV_PORT_ENFORCE
47*4882a593Smuzhiyun | IB_DEVICE_PORT_ACTIVE_EVENT
48*4882a593Smuzhiyun | IB_DEVICE_SYS_IMAGE_GUID
49*4882a593Smuzhiyun | IB_DEVICE_RC_RNR_NAK_GEN
50*4882a593Smuzhiyun | IB_DEVICE_SRQ_RESIZE
51*4882a593Smuzhiyun | IB_DEVICE_MEM_MGT_EXTENSIONS
52*4882a593Smuzhiyun | IB_DEVICE_ALLOW_USER_UNREG,
53*4882a593Smuzhiyun RXE_MAX_SGE = 32,
54*4882a593Smuzhiyun RXE_MAX_WQE_SIZE = sizeof(struct rxe_send_wqe) +
55*4882a593Smuzhiyun sizeof(struct ib_sge) * RXE_MAX_SGE,
56*4882a593Smuzhiyun RXE_MAX_INLINE_DATA = RXE_MAX_WQE_SIZE -
57*4882a593Smuzhiyun sizeof(struct rxe_send_wqe),
58*4882a593Smuzhiyun RXE_MAX_SGE_RD = 32,
59*4882a593Smuzhiyun RXE_MAX_CQ = 16384,
60*4882a593Smuzhiyun RXE_MAX_LOG_CQE = 15,
61*4882a593Smuzhiyun RXE_MAX_MR = 256 * 1024,
62*4882a593Smuzhiyun RXE_MAX_PD = 0x7ffc,
63*4882a593Smuzhiyun RXE_MAX_QP_RD_ATOM = 128,
64*4882a593Smuzhiyun RXE_MAX_RES_RD_ATOM = 0x3f000,
65*4882a593Smuzhiyun RXE_MAX_QP_INIT_RD_ATOM = 128,
66*4882a593Smuzhiyun RXE_MAX_MCAST_GRP = 8192,
67*4882a593Smuzhiyun RXE_MAX_MCAST_QP_ATTACH = 56,
68*4882a593Smuzhiyun RXE_MAX_TOT_MCAST_QP_ATTACH = 0x70000,
69*4882a593Smuzhiyun RXE_MAX_AH = 100,
70*4882a593Smuzhiyun RXE_MAX_SRQ = 960,
71*4882a593Smuzhiyun RXE_MAX_SRQ_WR = 0x4000,
72*4882a593Smuzhiyun RXE_MIN_SRQ_WR = 1,
73*4882a593Smuzhiyun RXE_MAX_SRQ_SGE = 27,
74*4882a593Smuzhiyun RXE_MIN_SRQ_SGE = 1,
75*4882a593Smuzhiyun RXE_MAX_FMR_PAGE_LIST_LEN = 512,
76*4882a593Smuzhiyun RXE_MAX_PKEYS = 1,
77*4882a593Smuzhiyun RXE_LOCAL_CA_ACK_DELAY = 15,
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun RXE_MAX_UCONTEXT = 512,
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun RXE_NUM_PORT = 1,
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun RXE_MIN_QP_INDEX = 16,
84*4882a593Smuzhiyun RXE_MAX_QP_INDEX = 0x00020000,
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun RXE_MIN_SRQ_INDEX = 0x00020001,
87*4882a593Smuzhiyun RXE_MAX_SRQ_INDEX = 0x00040000,
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun RXE_MIN_MR_INDEX = 0x00000001,
90*4882a593Smuzhiyun RXE_MAX_MR_INDEX = 0x00040000,
91*4882a593Smuzhiyun RXE_MIN_MW_INDEX = 0x00040001,
92*4882a593Smuzhiyun RXE_MAX_MW_INDEX = 0x00060000,
93*4882a593Smuzhiyun RXE_MAX_PKT_PER_ACK = 64,
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun RXE_MAX_UNACKED_PSNS = 128,
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Max inflight SKBs per queue pair */
98*4882a593Smuzhiyun RXE_INFLIGHT_SKBS_PER_QP_HIGH = 64,
99*4882a593Smuzhiyun RXE_INFLIGHT_SKBS_PER_QP_LOW = 16,
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* Max number of interations of each tasklet
102*4882a593Smuzhiyun * before yielding the cpu to let other
103*4882a593Smuzhiyun * work make progress
104*4882a593Smuzhiyun */
105*4882a593Smuzhiyun RXE_MAX_ITERATIONS = 1024,
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Delay before calling arbiter timer */
108*4882a593Smuzhiyun RXE_NSEC_ARB_TIMER_DELAY = 200,
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* IBTA v1.4 A3.3.1 VENDOR INFORMATION section */
111*4882a593Smuzhiyun RXE_VENDOR_ID = 0XFFFFFF,
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* default/initial rxe port parameters */
115*4882a593Smuzhiyun enum rxe_port_param {
116*4882a593Smuzhiyun RXE_PORT_GID_TBL_LEN = 1024,
117*4882a593Smuzhiyun RXE_PORT_PORT_CAP_FLAGS = IB_PORT_CM_SUP,
118*4882a593Smuzhiyun RXE_PORT_MAX_MSG_SZ = 0x800000,
119*4882a593Smuzhiyun RXE_PORT_BAD_PKEY_CNTR = 0,
120*4882a593Smuzhiyun RXE_PORT_QKEY_VIOL_CNTR = 0,
121*4882a593Smuzhiyun RXE_PORT_LID = 0,
122*4882a593Smuzhiyun RXE_PORT_SM_LID = 0,
123*4882a593Smuzhiyun RXE_PORT_SM_SL = 0,
124*4882a593Smuzhiyun RXE_PORT_LMC = 0,
125*4882a593Smuzhiyun RXE_PORT_MAX_VL_NUM = 1,
126*4882a593Smuzhiyun RXE_PORT_SUBNET_TIMEOUT = 0,
127*4882a593Smuzhiyun RXE_PORT_INIT_TYPE_REPLY = 0,
128*4882a593Smuzhiyun RXE_PORT_ACTIVE_WIDTH = IB_WIDTH_1X,
129*4882a593Smuzhiyun RXE_PORT_ACTIVE_SPEED = 1,
130*4882a593Smuzhiyun RXE_PORT_PKEY_TBL_LEN = 1,
131*4882a593Smuzhiyun RXE_PORT_PHYS_STATE = IB_PORT_PHYS_STATE_POLLING,
132*4882a593Smuzhiyun RXE_PORT_SUBNET_PREFIX = 0xfe80000000000000ULL,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* default/initial port info parameters */
136*4882a593Smuzhiyun enum rxe_port_info_param {
137*4882a593Smuzhiyun RXE_PORT_INFO_VL_CAP = 4, /* 1-8 */
138*4882a593Smuzhiyun RXE_PORT_INFO_MTU_CAP = 5, /* 4096 */
139*4882a593Smuzhiyun RXE_PORT_INFO_OPER_VL = 1, /* 1 */
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #endif /* RXE_PARAM_H */
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